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The article studies a novel 2-bits-per-transistor mask-programmable read-only memory (mask ROM) device with gate-to-drain nonoverlapped implantation (NOI). Findings reveal the characteristics of NOI mask ROM, including 2-bits-per-transistor operation, body effects, hot carrier impact, and array layouts.

The characteristics of Ge junction diodes and gate-last p- and n-metal-oxide-semiconductor field-effect transistors with the atomic-layer-deposited-[Al.sub.2][O.sub.3] gate dielectrics are examined. The studies have shown that the relatively inferior n-FET has resulted from the larger source/drain contact resistance, higher surfaces states scattering, and lower substrate-doping concentration.

The experimental hole gate direct tunneling current of p-MOSFETs are described under shallow trench isolation (STI)-induced longitudinal compressive stress, which has not followed the trend caused by the strain-altered valence-band splitting alone. The strain-retarded oxide growth rate has enhanced hole direct tunneling and has reversed the conventional trend due to the strain-altered valence-band splitting.

A physics-based compact subthreshold current model is described for short-channel nanoscale double-gate MOSFETs. The electrostatics is dominated by capacitive coupling between the body electrodes, the potential is obtained as an analytical solution of the 2-D Laplace equation and the current modeling is based on drift-diffusion theory.

A huge drain current hysteresis and transient behavior observed during pseudo-MOSFET ([Psi]-MOSFET) drain current-gate voltage measurements is reported. Measurements suggest that the drain current hysteresis in mainly due to substrate deep depletion, with simulations confirming that transient behavior is dependent on substrate generation.

This paper presents a new hardware implementation of gate drive circuits applied to low-power neutral-point-clamped (NPC) multilevel three-phase inverters. The proposed circuit is based on commercially available MOS-gate driver ICs (MGDs) for large-scale applications, which may reduce the total cost of implementation of NPC inverters. Only one dc power supply is required to feed all the gate drivers for the three-phase system. Detailed design procedures are presented, which include the protection circuits for avoiding hazardous switching states of the power switches. Experimental results of a laboratory prototype demonstrate the validity of the proposed circuit. These results also suggest that for achieving safe operation of snubberless power switches during transients, a hybrid implementation of each NPC phase leg, consisting of MOSFETs with voltage ratings at half the dc bus voltage and of insulated gate bipolar transistors rated at the total dc bus voltage, is recommended. Index Terms--Charge pump technique, gate drive circuit, switch-voltage balancing, three-level neutral-point-clamped (NPC) inverter.

Electrodeposited Ni-Ge and NiGe/Ge Schottky diodes on highly doped Ge has shown low off current, which is suitable for Schottky barrier (SB) p-MOSFETs. The incorporation of high-quality Schottky diodes in the source/drain of a Ge channel PMOS has shown that a highly doped substrate is used to minimize the source-to-drain subthreshold leakage current.

A physical description of two specific aspects in drain-extended MOS transistors, that is, quasi-saturation and impact-ionization effects, is described and these factors are attributed to the Kirk effect. The model is validated by MATLAB program and has displayed excellent scalability for various transistor dimensions, drift-region doping concentration and voltage-handling capability.

A new experimental method is described for determining the backscattering coefficient and the ballistic ratio of n- and p-FDSOI and multigate nanodevices. Universal abaci are developed in order to accurately extract backscattering coefficients for n- and p-FDSOI MOSFETs both in linear and saturated regimes.

A newly designed low-sensitivity, low-bounce, high-linearity current-controlled oscillator (CCO) is described for a single-supply mixed-mode instrumentation system. The sensitivity of the proposed CCO is nearly independent of the power supply voltage that is less than a conventional current-starved oscillator.

Addressable arrays that use switches to isolate the devices being tested are limited in size and utility by the parasitic leakage caused by those switches. A new biasing technique that reduces the leakage of these switches has been studied to address this problem. Simulations performed in a 90 nm low-power technology predicted almost a two-decade drop in parasitic leakage of the array. Experimental data confirmed this improvement. 1 x 32 and 4 x 32 arrays using this biasing technique were used to investigate probe pad effects, device variability and geometry dependence. Index Terms--MOSFET array, parametric test, probe pads, source biasing, test structure design, variability.

In this work, a new electrical characterization method for MOSFETs using an in-wafer Kelvin-contact device structure is developed. The developed method can eliminate the parasitic series resistance such as resistance in source/drain terminals of MOSFETs, in metal wires on wafers and in a measurement system. Using the developed method, we can measure and analyze the short channel transistors' intrinsic current-voltage characteristics as well as the quantitative effects of the parasitic series resistance to the device performance, very stably and accurately. In addition, a framework for the characterization of inversion layer mobility in ultrathin gate insulator MOSFETs with large gate current is provided. Based on the framework, the developed method is introduced as a suitable mobility characterization method. Index Terms--Charge carrier mobility, contact resistance, electric variables measurement, MOSFETs.

A temperature-dependent RF large-signal model is constructed by modifying the Verilog-A code of the Angelov model for unique characteristics of GaN MOSHFETs. Different from the previously reported EEHEMT-based model, the present electro-thermal model can fit the temperature effects on threshold shift and transconductance degradation, the drain current in the linear region, and the gate capacitance near the cutoff region. As the result, the power, gain, efficiency, linearity, drain current, and gate current of both Class-A and Class-AB amplifiers are accurately simulated over a wide range of input powers, matching impedances, and ambient temperatures. Index Terms--Gallium compounds, MODFETs, MOSFETs, power amplifiers, pulse measurement, semiconductor device modeling, temperature measurement, thermal resistivity.

As the dimension of semiconductor device shrunk into nanometer scale (nanoscale), characteristic fluctuation is more pronounced, and become crucial for circuit design. In this paper, discrete-dopant-induced characteristic fluctuation of 16-nm-gate metal-oxide-semiconductor field effect transistors (MOSFET) circuit under high-frequency regime is quantitatively studied. The circuit gain, the 3 dB bandwidth and the unity-gain bandwidth of the tested nanoscale transistor circuit are calculated concurrently capturing the discrete-dopant-number-and discrete-dopant-position-induced fluctuations in the large-scale statistically sound 'atomistic' device/circuit coupled simulation. For the 16-nm-gate MOSFET circuit, the number of discrete dopants, varying from zero to 14, may result in 5.7 % variation of the circuit gain, 14.1% variation of the 3 dB bandwidth, and 10.4 % variation of the unity-gain bandwidth. To suppress the high-frequency characteristic fluctuations, an improved doping distribution along the longitudinal diffusion direction from the MOSFET's surface to substrate is further performed to examine the associated fluctuation. The improved vertical doping profile with less dopants locating near surface of channel effectively reduces the fluctuations of the circuit gain, the 3 dB bandwidth and the unity-gain bandwidth dramatically. Compared with the original doping profile, the reduction is 32.3%, 19.4% and 51.8%, respectively. This study provides an insight into random-dopant-induced intrinsic high-frequency characteristic fluctuations and verifies the potential fluctuation suppression technique on high-frequency characteristic fluctuations of nanoscale transistor circuit. Index Terms--Characteristic fluctuation, fluctuation suppression technique, high frequency, modeling and simulation, nanometer scale metal-oxide-semiconductor field effect transistors (MOSFET) device and circuit, random dopant effect.

The latent damages were investigated for Power MOSFETs irradiated by high LET heavy ions. It was demonstrated that the post irradiation leakage current in damaged gate oxide was determined by the initial gate stress after the irradiation and the damage was stable even after a million of gate stress repetition. Index Terms--Heavy ion, latent damage, power MOSFET.

This paper presents a detailed analysis of commercial trench power MOSFET responses to [Co.sup.60] irradiation of all key d.c. electrical test parameters. Charge trapping in the gate oxide causes the threshold voltage ([V.sub.TH]) to shift, which, in turn, accounts for most of the degradation exhibited by the device after irradiation. Index Terms--Total ionizing dose (TID), trench power MOSFET.

Irradiation tests on 90 nm CMOS devices at different total ionizing doses lead to new insights into degradation mechanisms in gate oxides and lateral isolation structures and into their impact on gate and drain current noise sources. The action of lateral parasitic transistors and their physical parameters are studied in different operating conditions. The main focus is on 1/f noise, which is one of the few parameters which are sizably affected by irradiation. Irradiation effects on the noise in the gate current are discussed in this paper for the first time. The analysis of the behavior of thick oxide I/O transistors provides a comparison both with thin oxide core devices and with previous, less scaled CMOS generations. Index Terms--Deep submicron, ionizing radiation, MOSFET, noise, shallow trench isolation (STI).

The effects of gate length and drain bias on the off-state drain leakage current of irradiated fully-depleted SOI n-channel MOSFETs are reported. The experimental results are interpreted using a model based on the combined effects of band-to-band tunneling (BBT) and the trapped charge in the buried oxide. For negative gate-source voltages, the drain leakage current increases with the drain voltage because the electric field in the gate-to-drain overlap region is increasing. The off-state current in these devices increases with total ionizing dose due to oxide trapped charge build up in the buried oxide, enhanced by the BBT mechanism. The experimental data show that these effects are more significant for devices with shorter gate-lengths. Simulation results suggest that the BBT-generated holes are more likely to drift all the way from the drain to the source in shorter devices, enhancing the drain leakage current, while they tend to tunnel across the gate oxide in longer devices. Index Terms--Band-to-band tunneling (BBT), fully depleted silicon-on-insulator (FDSOI), gate induced drain leakage current (GIDL), leakage current and total ionizing dose (TID), metal-oxide-semiconductor-field-effect transistor (MOSFET).

This paper presents the first comprehensive investigation of the impact of proton irradiation on the performance of high-voltage (HV) nMOS transistors implemented in a low-voltage (LV) SiGe BiCMOS technology. The effects of irradiation gate bias, irradiation substrate bias, and operating substrate bias on the radiation response of these transistors are examined. Experimental results show that the radiation-induced subthreshold leakage current under different irradiation biasing conditions remains negligible after exposure to a total dose of 600 krad(Si). We find that there are differences in the radiation response of LV and HV MOSFETs, suggesting that the mechanisms involved in causing degradation in LV and HV transistors could be of fundamentally different origins. Index Terms--High-voltage CMOS transistors, ionization damage, MOSFET, SiGe, total dose radiation effects.

We present new experimental results about channel hot carrier degradation of enclosed layout transistors as a function of previous accumulated total ionizing dose, stress temperature, and transistor geometry. We show that the parametric degradation follows a power law, whose exponent is higher than in conventional open layout transistors, possibly due to a different diffusion geometry of hydrogen. Through physical simulation we attribute this effect to the electric field at the device corners, which leads to a non-uniform impact ionization. Previous irradiation reduces the channel hot carrier degradation in MOSFETs with 5.2-nm gate oxide, while having a minor influence with 2.2-nm gate dielectric. Index Terms--CHC, enclosed layout transistor, hot-electrons, TID, X-ray.