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In this work, we developed a process to release the optical waveguides locally from the back side of a silicon-on-insulator wafer to enable a connection and an interaction between organic materials and photonic devices. The release procedure is realized by a local back-side etch followed by a chemical wet etch. Furthermore, certain process steps for a controlled removal of the buried oxide below the silicon device layer are introduced to protect the back end of line (BEOL) and to guarantee a compatibility with a photonic integrated circuit (PIC) technology. The presented approach gives perspective to a hybrid integration of organic materials into a PIC technology with a full BEOL for high-speed silicon-organic hybrid modulators and label-free biosensors.

Diversity in application makes the CMOS technologies interesting for solving the most complex requests from science and consumer electronics. The monolithic integration of MEMS devices into any CMOS technology is one of the most promising approach to reduce the parasitic effects by interconnects and small formfactors, at low production costs by wafer-level fabrication. In this work, an encapsulated RF-MEMS switch for mm-wave and sub-THz frequencies has been monolithically integrated into the AlCu-based Back-End-Of-Line (BEOL) of a 130 nm SiGe BiCMOS technology of IHP by modifications in the standard process flow and device design. The changes of the standard flow are detailed. Finally, a fully functional encapsulated RF-MEMS switch in a BiCMOS process is demonstrated.

The original version of this Article omitted an affiliation for M. Lisker. The correct affiliations for M. Lisker are listed below: IHP- Leibniz Institut für innovative Mikroelektronik, Im Technologiepark 25, 15236, Frankfurt (Oder), Germany Technical University of Applied Science Wildau, Hochschulring 1, 15745, Wildau, Germany The original Article and accompanying Supplementary Information file have been corrected.

One of the limiting factors of graphene integration into electronic, photonic, or sensing devices is the unavailability of large-scale graphene directly grown on the isolators. Therefore, it is necessary to transfer graphene from the donor growth wafers onto the isolating target wafers. In the present research, graphene was transferred from the chemical vapor deposited 200 mm Germanium/Silicon (Ge/Si) wafers onto isolating (SiO2/Si and Si3N4/Si) wafers by electrochemical delamination procedure, employing poly(methylmethacrylate) as an intermediate support layer. In order to influence the adhesion properties of graphene, the wettability properties of the target substrates were investigated in this study. To increase the adhesion of the graphene on the isolating surfaces, they were pre-treated with oxygen plasma prior the transfer process of graphene. The wetting contact angle measurements revealed the increase of the hydrophilicity after surface interaction with oxygen plasma, leading to improved adhesion of the graphene on 200 mm target wafers and possible proof-of-concept development of graphene-based devices in standard Si technologies.

We present an SOI-waveguide coupled germanium photodiode with very high OE -3 dB bandwidth of ≥110 GHz at reverse bias of 2 V. This performance is achieved by a novel construction in that the germanium is sandwiched in between two in-situ doped silicon regions. This fabrication approach allows for avoiding ion-implantation into the germanium, which is certainly beneficial for the bandwidth as minority carrier diffusion effects are strongly suppressed. A responsivity of >0.6 A/W at 1550 nm (-2 V) is achieved, while the dark current of this device yields to about 300 nA (-2 V). To our knowledge, this is the most advanced germanium photo detector in terms of bandwidth combined with state-of-the-art responsivity as well as moderate dark currents. We demonstrate that the novel photodiodes can be fabricated with high yield.

We present insights into processes of cleaning, patterning, encapsulation, and contacting graphene in a 200 mm wafer pilot line routinely used for the fabrication of integrated circuits in Si technologies. We demonstrate key process steps and discuss challenges and roadblocks which need to be overcome to enable integration of this material with Si technologies.

Two different approaches for contacting graphene in a 200 mm wafer silicon technology environment were tested. The key is the opportunity to create a thin SiN passivation layer on top of the graphene protecting it from the damage by plasma processes. The first approach uses pure Ni contacts with a thickness of 200 nm. For the second attempt, Ni is used as the contact metal which substitutes the Ti compared to a standard contact hole filling process. Accordingly, the contact hole filling of this “stacked via” approach is Ni/TiN/W. We demonstrate that the second “stacked Via” is beneficial and shows contact resistances of a wafer scale process with values below 200 Ohm µm.

The main challenges for Al-Al wafer bonding are the fast oxidation and the high roughness of the Al surface. This paper describes an optimized Al sputter-deposition process reducing the surface roughness to values below 2 nm. Based on this, a wafer level Al-Al thermo-compression bonding process is presented, where a surface treatment and the subsequent bonding are both performed in a high vacuum cluster. The patterned wafers were bonded with temperatures between 300 and 500 °C for 1 h using a bonding force of 60 kN. Scanning acoustic microscopy and transmission electron microscopy studies revealed a reliable bonding, an accurate alignment and a high uniformity for 200 mm wafers. The electrical characterization of contact chains with Al bonding pad sizes of 20×20 µm2 showed resistances lower than 50 mΩ per contact, which might indicate areas of oxide-free bonding.

In this work, the development of a Through-Silicon Via process module for multi-project wafer SiGe BiCMOS and silicon interposer is demonstrated. The TSV technology based on a via-middle approach is optimized to provide TSV process and design flexibility which is required for a multi-project wafer service. Different passive and active TSV-based components like a low-noise amplifier, RF interposer transmission lines and substrate-integrated waveguides are fabricated. The TSV process module enables a wide range of promising new applications by adding additional functionalities to conventional BiCMOS and interposer substrate technologies.

A CMOS compatible AlN/SiO2/Si3N4/Si(100) surface acoustic wave (SAW) device has been fabricated and will be compared with standard AlN/SiO2-based devices. The presented filter demonstrates high potential for CMOS integrated high-frequency SAW devices. The filter insertion loss could be improved to −12.8 dB. The device exhibits high crosstalk suppression of −50 dB on a standard Si-substrate (10 $\Omega $ cm). X-ray diffraction, (scanning) transmission electron microscopy, and energy dispersive X-ray spectroscopy studies correlate the signal quality with $c$ -axis orientation of aluminum nitride films on interdigitated transducer finger electrodes. Finite-element method simulations are in good agreement with the electric measurements and show typical Rayleigh particle displacement.

The development of a Through-Silicon Via process module within a high performance SiGe BiCMOS technology is demonstrated. The TSV technology module including both the TSV fabrication process itself, the temporary wafer bonding for BiCMOS thin wafer handling and the thin wafer backside processing is developed on 8-inch wafer level and the optimization of the different process steps are explained. This process module is fully compatible with the qualified SiGe BiCMOS technology environment which enables very uniform and reliable TSV backside fabrication adding new functionalities into IHPs high performance SiGe BiCMOS technologies applicable for thin wafer applications and 3D heterogeneous integration.

In this paper, wafer level transfer of graphene on to a dielectric substrate is demonstrated based on SiO 2 -SiO 2 fusion bonding and de-bonding processes. The developed technique allows to transfer graphene on 200 mm wafer without any contamination; thus CMOS compatible. The experimental data verifies the successful transfer of the graphene on to another substrate with high quality and a yield value of 98% with average 3.5 kΩ/□ sheet resistance. To the best of authors knowledge, it is the first time demonstration of the graphene transfer based on SiO 2 -SiO 2 fusion bonding and de-bonding process on 200 mm wafer level which would allow a complete integration of graphene material into a CMOS line and opens the way for new devices based on graphene material.

In this paper, a fully BiCMOS integrated microfluidic technology platform for Lab-on Chip (LoC) applications is presented. Fusion bonding and adhesive bonding techniques are applied to realize a 3-wafer-stack integration. A glass wafer is used on top of the BiCMOS wafer and the Si channel wafer to enable simultaneous optical and electrical measurements. An alignment accuracy of less than 1 µm between BiCMOS and channel wafer is achieved while having channel heights between 30 and 100 µm. All the microfluidic process integration steps are kept below 300 °C. The microfluidic inlet and the outlet are positioned on the backside of the wafer stack to provide both the optical inspection and the electrical measurements from the wafer's front side. The developed wafer level integration technique provides high throughput solutions for emerging chemical and biological LoC applications.

The demand for the high-density integrated memories is growing along with the scaling of the transistor technology nodes. To fabricate the reliable devices in advanced technologies, optimization of several process steps is necessary [1]. The capacitor, which is commonly a MIM (Metal-Insulator-Metal) module finds its application as a basic storage device in memories, filters, voltage limiters etc. The MIM module is also considered as an integral part of memory technologies such as DRAM, FeRAM, and RRAM. The MIM modules should demonstrate reliable operation through better performance and efficiency. And, it is realized through the parameters related to MIM module such as, low leakage current, less variability with respect to capacitance, high quality factor Q, lower defect density, low parasitic capacitance and many others [2]. Reactive-ion-etching plays a very important role in BEOL integration of MIM devices. The MIM module is created by dry etching through the MIM stack. Related to RRAM (Resistive Random Access Memory) applications the MIM stack consists of an additional buffer layer such as Ti or Hf [3]. These layers are easily oxidizable and the etching step could oxidize them from the sidewalls. Also, the residuals of the metal if remain on the sidewall could lead to leaky devices. Hence, an etch process which is not well optimized could damage the devices and in turn pose a threat to their functionality and reliability [4]. An improved MIM stack etch process is beneficial to reduce the above-mentioned damages. Several techniques were used in the past to cover the MIM devices with dielectric materials like SiO2 and SiN, which protects the devices from further process steps involved in the fabrication procedure [5]. In this work we demonstrate the effect of the improved etch process with a combination of SiNO spacers and encapsulation techniques for TiN/Ti/HfO2/TiN stacks. This stack is most popularly used in RRAM and, in this work, it is integrated into the BEOL of the 250 nm CMOS technology at IHP. To test the performance of the devices, the MIM stack was fabricated in three different approaches. In the first approach, photoresist is used as a mask to etch the MIM stack, the second one uses TiN hard mask and the third one uses TiN hard mask etch in addition to creation of SiNO spacers after the TiN/Ti etch. The encapsulation of MIM modules with SiNO is implemented in all the three approaches mentioned above. Special device structures with the TiN/Ti/HfO2/TiN stack are fabricated to test the variability of the MIM parameters on the entire wafer. Additionally, the switching operation was tested by means of DC voltage sweeps on the MIM RRAM devices which includes, forming, reset and set steps followed by 50 cycles of reset and set processes. The devices associated with the improved fabrication process steps exhibited less variability in terms of leakage current, capacitance and Q-factor values along the entire wafer. This reduction in the variability of the parameters corresponding to the MIM devices could be used for emerging applications. References G.S. Kar, A.Fantini, Y.Y. Chen, V. Paraschiv, B. Govorenau, H. Hody, N. Jossart, H.Tielens, S. Brus, O. Richard, T. Vandeweyer, D.J. Wouters, L. Altimime, M. Jurczak, i n Symposium on VLSI Technology (VLSIT), 2012 IEEE, pp. 157-158 E. Pérez, A. Grossi, C. Zambelli, M. K. Mahadevaiah, P. Olivo, and Ch. Wenger, in MTT-S International Microwave Workshop Series on Advanced Materials and Processes for RF and THz Applications (IMWS-AMP), 2018 IEEE, pp. 1-3 E. Pérez, M. K. Mahadevaiah, C. Zambelli, P. Olivo, and Ch. Wenger, Solid-State Electronics, (2019) V. B. Naik, J. H. Lim, K. Yamane, D. Zeng, H. Yang, N. Thiyagarajah, J. Kwon, N. L. Chung, R. Chao, T. Ling, K. Lee, in International Reliability Physics Symposium (IRPS), 2019 IEEE, pp. 2C-2 Y.S. Chen, H.Y. Lee, P.S. Chen, P.Y. Gu, W.H. Liu, W.S. Chen, Y.Y. Hsu, C.H. Tsai, F. Chen, M.J. Tsai, and C. Lien, Electron Device Letters, Vol. 32, Issue: 3, pp 390-392 (2011)

In this work, transmitters for broadband radio links are addressed in the frequency range 100...500 GHz, which are key building blocks for future wireless communication systems. What makes this work unique is that these components are to be realized by means of an InP-on-BiCMOS wafer-level process technology. In contrast to other attempts, the technology demonstrated here is based on preprocessed BiCMOS and transfer substrate (TS) InP HBT technologies, respectively. This allows to combine the favorable power performance of III-V circuits with the advantages of BiCMOS circuits such as complexity and integration density, without critical performance trade-offs of the individual technologies. Critical problems in such a technology are RF interconnects. DCand RF-interconnects between the InP and BiCMOS circuits have been tested, showing the feasibility of the wafer-level bond process for heterointegration of TS InP and BiCMOS. For that purpose a 4-metal Al back-end was built on the silicon wafer with silicon dioxide as interlayer dielectric. After the wafer bond process the TS InP with 3-metal Au in benzocyclobutene (BCB) as interlayer dielectric has been realized in top of the processed BiCMOS to test the best transmission line configuration. The BiCMOS backend needed some adaptation for the wafer-bond process in terms of planarization of the passivation. The standard process uses a SiO2and a SiN-layer as passivation stack. For the planarization of the top-metal 2 level (TM2 in Fig.1, 3μm Al thickness) a thick SiO2 was deposited by HDP and PECVD. It was planarized by chemical mechanical polishing (CMP) and finally etched back until the Top-Metal 2 pads reach the surface. The TS InP HBT process has been adapted to contact this top surface. A backside polish process was developed to enable backside lithography. The backside lithography allows to produce bond alignment marks with a front to back side misalignment smaller than 300 nm. After that the 200 mm wafers were cut into four 3” wafers to enable the bond process with the 3” preprocessed InP wafers with subsequent removal of the unused InP by wet chemical etching. The wafer bond process and the electrical measurements at the finished wafers were carried out at the FBH. We demonstrate the feasibility of InP HBT / Si BiCMOS integration with a wafer bonding accuracy < 10 μm resulting in low DC contact resistance of about 1 Ohm. RF measurements (Fig. 2) demonstrated low insertion loss of the BiCMOS-InP via transitions (G2TM2) compared with a reference line (GD-G2) completely in BCB, and the simulated losses.

Filament-type HfO2-based RRAM has been considered as one of the most promising candidates for future non-volatile memories. Further improvement of the stability, particularly at the “OFF” state, of such devices is mainly hindered by resistance variation induced by the uncontrolled oxygen vacancies distribution and filament growth in HfO2 films. We report highly stable endurance of TiN/Ti/HfO2/Si-tip RRAM devices using a CMOS compatible nanotip method. Simulations indicate that the nanotip bottom electrode provides a local confinement for the electrical field and ionic current density; thus a nano-confinement for the oxygen vacancy distribution and nano-filament location is created by this approach. Conductive atomic force microscopy measurements confirm that the filaments form only on the nanotip region. Resistance switching by using pulses shows highly stable endurance for both ON and OFF modes, thanks to the geometric confinement of the conductive path and filament only above the nanotip. This nano-engineering approach opens a new pathway to realize forming-free RRAM devices with improved stability and reliability.

We investigate the use of perfluorodecyltrichlorosilane-based self-assembled monolayer as seeding layer for chemical vapour deposition of HfO2 on large area CVD graphene. The deposition and evolution of the FDTS-based seed layer is investigated by X-ray photoelectron spectroscopy, Auger electron spectroscopy, and transmission electron microscopy. Crystalline quality of graphene transferred from Cu is monitored during formation of the seed layer as well as the HfO2 growth using Raman spectroscopy. We demonstrate that FDTS-based seed layer significantly improves nucleation of HfO2 layers so that graphene can be coated in a conformal way with HfO2 layers as thin as 10 nm. Proof-of-concept experiments on 200 mm wafers presented here validate applicability of the proposed approach to wafer scale graphene device fabrication.

Back-end-of-line integrated 1 × μm2 TiN/HfO2/Ti/TiN MIM memory devices in a 0.25- μm complementary metal-oxide-semiconductor technology were built to investigate the conduction mechanism and the resistive switching behavior as a function of temperature. The temperature-dependent I- V characteristics in fresh devices are attributed to the Poole-Frenkel mechanism with an extracted trap energy level at φ ≈ 0.2 eV below the HfO2 conduction band. The trap level is associated with positively charged oxygen vacancies. The electroformed memory cells show a stable bipolar switching behavior in the temperature range from 213-413 K. The off -state current increases with temperature, whereas the on-state current can be described by a weak metallic behavior. Furthermore, the results suggest that the I-V cycling not only induces significant changes in the electrical properties of the MIM memory devices, i.e., the increase in the off-state current, but also stronger temperature dependence. The temperature effect on the on-state and off-state characteristics is modeled within the framework of the quantum point-contact model for dielectric breakdown using an effective temperature-dependent confinement potential.

Summary The generation of surface acoustic waves using a process, which is compatible with standard BEOL fabrication was demonstrated. In this process, the inter-digitated acoustic transducers are embedded in a silicon dioxide matrix, which is subsequently coated with the piezoelectric material ZnO. The delay lines with sub-μm wavelength fabricated by using this process achieve resonance frequencies in the range of 1 to 4 GHz, thus opening the door for the monolithic integration of acoustic devices in the (Bi)CMOS technology. In addition, the reliable bipolar resistive switching characteristics of TiN/HfO 2 /Ti/TiN based MIM diodes processed by a BiCMOS technology compatible process flow is demonstrated. The voltages, which are required to switch the devise from the On into the Off state and vise versa are + 1 V respectively - 1 V. The resistance ratio R OFF / R ON is in the range of 5. Acknowledgments This work was supported by the grant from German BMBF (grant No. 13N9891). ECS Transactions, 33 (6) 823-829 (2010)828

The process of epitaxial SiGe layers are getting attractive as they offer a variety of advanced microelectronics devices compatible with silicon processing technology [1-3]. The large research effort of the last decade has focused on the growth of high quality strained SiGe layers. In particular, SiGe superlattice containing high Ge concentration is demanded in order to improve performances of the devices. Recently, IHP has achieved a significant breakthrough in SiGe/Si MQW processing technology [4]. The developed high quality of superlattice of SiGe/Si MQW structure containing 50% Ge has been successfully processed (Fig. 1) and presented as a potential thermistor material with its high performance for uncooled microbolometer applications [5]. The prototype of thermistor device with 50% Ge in SiGe wells exhibited an outstanding TCR of -5.5 %/K and a K1/f value of 3.4 × 10-15 for 200 µm× 200 µm pixel size, respectively, showing a concurrent achievement of a very high TCR and a low 1/f noise performance. One of the main challenge of SiGe/Si MQW structures is the high resistance values including high Ge concentration makes it difficult to integrate as a detector material in a complete microbolometer device. Large pixel resistances cause not only high noises and hence lower sensitivity but also a challenge to design and maximize the performance of the ROICs [6, 7]. A method to optimize and tune the resistance of the detector material in microbolometers is in-situ doping of quantum well layers in order to enhance the combined detector and ROIC performance. In [8], Boron (B) doping level in SiGe quantum wells are optimized in order to keep the pixel resistance of the thermistor in acceptable values for an ROIC design. B doping of SiGe MQWs is used for the resistance tuning of the detector. The main challenge of the method is simultaneous achievement of enough doping in the SiGe region of the MQWs while keeping the barrier intrinsic silicons non-doped. The initial pixel resistance of 3 period of SiGe/Si MQWs with 50% Ge concentration of 21 MΩ is reduced 210 kΩ for 25 × 25 µm2 pixel size by the optimization of in-situ B doping level in SiGe layers of the MQW stack [8]. The optimized B doping density of ~1 × 1018 cm-3 in SiGe wells did not cause any significant change in the TCR value whereas the 1/f noise performance is even enhanced due to the in-situ doping process. All the aforementioned results shows the successful demonstration of intrinsic thermistor based on SiGe/Si MQWs including 50% Ge with an acceptable pixel resistances. Although the successful demonstration of SiGe MQWs has been performed for high performance microbolometer applications, a full integration of the high performance SiGe/Si MQW based detector into a standard CMOS process is still challenging. SiGe/Si MQW process requires higher temperatures than the temperature budget of the post processing of CMOS process. Therefore, the transfer of the optimized detector structure to a CMOS/BiCMOS wafer needs a special layer transfer process (i.e. wafer bonding). More critically, due to the vertical working principle mechanism of the detector device, there is a challenge for full integration of the optimized detector structure into standard BiCMOS process because the suspended detector device needs to be contacted by both sides In this work, the recent progress on SiGe/Si type high performance detector structures will be presented. The process optimization of the detector by means of high TCR, low 1/f noise and appropriate resistance will be detailed. The method of integrating the developed SiGe/Si MQW structures into a 130 nm BiCMOS process will be provided. The integration method is based on the oxide-oxide fusion bonding of ROIC and detector wafer followed by post processing of the bonded wafer stack. The details of thermal conductance optimization of the microbolometer together with the mechanical stress optimization, required for the suspended detector device, will also be given. Finally, the low-pressure hermetic packaging of the microbolometer structure will also be proposed. Figure 1

Thin HfO2 films were grown as high-k dielectrics for Metal–Insulator–Metal applications by Atomic Vapor Deposition on 8 inch TiN/Si substrates using pure tetrakis(ethylmethylamido)hafnium precursor. Influence of deposition temperature (320–400 °C) and process pressure (2–10 mbar) on the structural and electrical properties of HfO2 was investigated. X-ray diffraction analysis showed that HfO2 layers, grown at 320 °C were amorphous, while at 400 °C the films crystallized in cubic phase. Electrical properties, such as capacitance density, capacitance–voltage linearity, dielectric constant, leakage current density and breakdown voltage are also affected by the deposition temperature. Finally, TiN/HfO2/TiN stacks, integrated in the Back-End-of-Line process, possess 3 times higher capacitance density compared to standard TiN/Si3N4/TiN capacitors. Good step coverage (> 90%) is achieved on structured wafers with aspect ratio of 2 when HfO2 layers are deposited at 320 °C and 4 mbar.

We demonstrate tunable Schottky barrier height and record photo-responsivity in a new-concept device made of a single-layer CVD graphene transferred onto a matrix of nanotips patterned on n-type Si wafer. The original layout, where nano-sized graphene/Si heterojunctions alternate to graphene areas exposed to the electric field of the Si substrate, which acts both as diode cathode and transistor gate, results in a two-terminal barristor with single-bias control of the Schottky barrier. The nanotip patterning favors light absorption, and the enhancement of the electric field at the tip apex improves photo-charge separation and enables internal gain by impact ionization. These features render the device a photodetector with responsivity (3 A/W for white LED light at 3 mW/cm2 intensity) almost an order of magnitude higher than commercial photodiodes. We extensively characterize the voltage and the temperature dependence of the device parameters and prove that the multi-junction approach does not add extra-inhomogeneity to the Schottky barrier height distribution. This work represents a significant advance in the realization of graphene/Si Schottky devices for optoelectronic applications., Comment: Research paper, 22 pages, 7 figures

An advanced photonic BiCMOS process is demonstrated capable, on the receiver side, for 100 Gb/s optical line rate. Key components of this process are monolithically integrated wave-guide Ge photodiodes showing more than 70 GHz bandwidth and 1 A/W responsivity, and SiGe HBTs with fT/fmax values of 240/290 GHz.

This work addresses a 1T1R RRAM architecture, which allows for the precise and reliable control of the forming/set current by using an access transistor. The 1T1R devices were fabricated in a modified [email protected] CMOS technology. The memory cells show stable resistive switching in dc as well as pulse-induced mode with an endurance of 10^3 and 10^2cycles, respectively. The variation of pulse widths as a function of amplitudes in 1R devices confirmed the set process distribution over a wide range of pulse widths ([email protected]), whereas the reset process variation is confined ([email protected]).

We introduce an approach that combines a 3” InP-DHBT transferred-substrate process with a SiGe-BiCMOS process. First, silicon and InP wafers are processed separately in different fabs. The silicon wafer runs through the complete 0.25 μm BiCMOS production process with five metal layers aluminum/tungsten back-end-of-line using silicon dioxide as dielectric. The processing was adapted for the following wafer bond process by planarization of the topmost metal level. This process flow was improved by using a SiN CMP stop layer on top of the metal layer stack, comparable to trench fill planarization. In that way a low surface topography was reached, this guarantees proper bonding results. Different mm-wave circuits operating at frequencies up to 246 GHz were produced to demonstrate the capability of the process flow.

The research on millimeter-wave circuits is driven by applications such as radar imaging and wideband communications. For some applications SiGe hetero junction bipolar transistors (HBTs) are limited in output power, determined by the physical properties of silicon. For SiGe devices with transit frequencies of 180 GHz a breakdown voltage BVCEO of 2.0 V can be measured. The increase in breakdown voltage means always a decrease in transit frequency. On the other hand, silicon is the leading material of modern semiconductor technology. It offers a high level of integration density and yield. SiGe-HBT device speed has increased to hundreds of gigahertz, however limited in output power compared to III-V semiconductor devices. Thus, merging the qualities of both III-V and Si technology will enable a new class of high-performance ICs. Our approach combines a 3” InP-DHBT transferred-substrate process [1] with a SiGe-BiCMOS process [2]. At first, silicon and InP wafers are processed separately. The silicon wafer runs through the complete production process with front-end and back-end in a 0.25 µm BiCMOS process with a five metal layers aluminum/tungsten back-end using silicon dioxide as interlayer dielectric and an additional tungsten local interconnect. The back-end-process was specially adapted for the following wafer bond process by planarization of the topmost metal (TM2) level. The InP wafer has a semi-completed front-end and one metal level of gold and benzocyclobutene (BCB) as the dielectric. At this stage the front-to-front bond process is performed (see Fig. 1 a). The ground metallization (Gd) of the InP wafer is embedded in BCB to achieve a surface step height of less than 100 nm. Prior to wafer bonding both wafers are spin coated with BCB. After a BCB curing process the two wafers are aligned and bonded. After the bond process the InP substrate is etched by HCl to expose the InP-DHBT structures (see Fig. 1 a). The vias between the InP and SiGe-BiCMOS structures are formed by inductively coupled plasma (ICP) reactive ion etching (RIE) dry etching through the BCB using SF6. Then they are electrically connected using a gold electroplating process (see Fig. 1 b). To demonstrate the capabilities of the heterointegration scheme an integrated signal source at 164 GHz was designed and fabricated [3]. It is an example of the different combinations of BiCMOS and InP circuit building blocks. It is shown in Fig. 2. The source consists of a fundamental voltage-controlled oscillator (VCO) in BiCMOS technology (left side in Fig. 2) which is interconnected by an optimized high frequency via transition to a doubler-amplifier combination in InP technology (right side of Fig. 2). Recently, the influences of the wafer bonding and the finalization of the InP-DHBT process on SiGe devices were investigated. It was found that the impact on the BiCMOS devices is rather small. The forward Gummel plot of a SiGe-HBT before and after hetero integration is shown in Fig. 3. There is a slight increase of the base current at low emitter-base voltages caused by leakage currents due to electrostatic discharges in etching processes in the post bonding procedure. But these changes are marginal. Nevertheless, options to remove these effects are being discussed, such as moderate anneal sequences (the post-fabrication temperature is limited to below 250°C due to the presence of BCB) and modifications to the post-waferbonding plasma etch recipes. References [1] T. Kraemer, M. Rudolph, F.J. Schmueckle, J. Wuerfl, and G. Traenkle, IEEE Transactions on Electron Devices, 56 (9), (2009), pp. 1897 – 1903 [2] H. Rücker, B. Heinemann, and A. Fox, Proc. Silicon Monolithic Integrated Circuits on RF Systems (SiRF 2012), 133 (2012) [3] T. Jensen, T. Al-Sawaf, M. Lisker, S. Glisic, M. Elkhouly, T. Kraemer, I. Ostermay, C. Meliani, B. Tillack, V. Krozer, and W. Heinrich, EuMIC (2013), pp. 244-247

Dielectrophoresis (DEP) is an established method for the spatial manipulation of microscopical particles. We demonstrate the temporal and permanent immobilization of polystyrene nanoparticles and protein molecules with sizes ranging from 4 nm to 500 nm. For this, regular arrays of silicon based nanoelectrodes were developed with tip diameters of 10 nm and 50 nm. No chemical modifications of molecules, particles or surfaces were needed. This opens up potentially important applications of DEP in biosensing and cell research.

A monolithically integrated 25Gbps receiver is shown as a demonstrator for a novel photonic BiCMOS process which allows for dense co-integration of 200GHz bipolar transistors and CMOS devices with waveguides, couplers, and Ge photodiodes.

A major challenge in biomaterials research is the regulation of protein adsorption which is a key factor for controlling the subsequent cell adhesion at implant surfaces. The aim of the present study was to control the adsorption of fibronectin (FN) and the attachment of MG-63 osteoblasts with an electronic nanostructure. Shallow doping line lattices with a period of 260 nm were produced for this purpose by implantation of phosphorous in silicon wafers. Protein coverage was determined after incubating the substrate with FN by means of an immunostaining procedure and the measurement of the fluorescence intensity with a TECAN analyzer. We observed an increased amount of adsorbed FN on the nanostructure compared to control substrates. MG-63 osteoblasts were cultivated for 24h on FN-incubated substrates and their morphology was assessed by SEM. Preferred orientation and elongation of the cells in direction of the doping lattice lines was observed on FN-coated nanostructures., {"references":["C.J. Bettinger, R. Langer, J.T. Borenstein, Engineering Substrate\nTopography at the Micro- and Nanoscale to Control Cell Function,\nAngew. Chem. Int. Ed. 48 (2009) 5406-5415.","C. Galli, M.C. Coen, R. Hauert, V.L. Katanaev, M.P. Wymann, P.\nGröning, L. Schlapbach, Protein adsorption on topographically\nnanostructured titanium, Surface Science 474 (2001) L180-L184.","P. Roach, D. Farrar, C.C. Perry, Surface Tailoring for Controlled Protein\nAdsorption: Effect of Topography at the Nanometer Scale and\nChemistry, J. Am. Chem. Soc. 128 (2006) 3939-3945.","P. Elter, R. Lange, U. Beck, Atomic force microscopy studies of the\ninfluence of convex and concave nanostructures on the adsorption of\nfibronectin, Colloids and surfaces 89 (2012) 139-146.","G.B. Sigal, M. Mrksich, G.M. Whitesides, Effect of Surface Wettability\non the Adsorption of Proteins and Detergents, J. Am. Chem. Soc. 120\n(1998) 3464-3473.","Y. Arima, H. Iwata, Effect of wettability and surface functional groups\non protein adsorption and cell adhesion using well-defined mixed selfassembled\nmonolayers, Biomaterials 28 (2007) 3074-3082.","M. Birkholz, P. Zaumseil, J. Bauer, D. Bolze, G. Weidner, Small-angle\nreciprocal space mapping of surface relief gratings, Materials science &\nengineering 27 (2007) 1154-1157.","D. Knoll, K. Ehwald, B. Heinemann, A. Fox, K. Blum, H. Rucker, F.\nFurnhammer, B. Senapati, R. Barth, U. Haak, W. Hoppner, J. Drews, R.\nKurps, S. Marschmeyer, H. Richter, T. Grabolla, B. Kuck, O. Fursenko,\nP. Schley, R. Scholz, B. Tillack, Y. Yamamoto, K. Kopke, H. Wulf, D.\nWolansky, W. Winkler, A flexible, low-cost, high performance SiGe:C\nBiCMOS process with a one-mask HBT module, pp. 783-786.","D. Knoll, B. Heinemann, R. Barth, K. Blum, J. Borngraber, J. Drews,\nK.-E. Ehwald, G. Fischer, A. Fox, T. Grabolla, U. Haak, W. Hoppner, F.\nKorndorfer, B. Kuck, S. Marschmeyer, H. Richter, H. Rucker, P. Schley,\nD. Schmidt, R. Scholz, B. Senapati, B. Tillack, W. Winkler, D.\nWolansky, C. Wolf, H.-E. Wulf, Y. Yamamoto, P. Zaumseil, A modular,\nlow-cost SiGe:C BiCMOS process featuring high-f/sub T/ and high\nBV/sub CEO/ transistors, pp. 241-244.\n[10] F. Grinnell, M.K. Feld, Fibronectin adsorption on hydrophilic and\nhydrophobic surfaces detected by antibody binding and analyzed during\ncell adhesion in serum-containing medium, J. Biol. Chem.257 (1982)\n4888-4893."]}

Integrated AlN/SiO 2 /Si(100) delay lines for Rayleigh surface acoustic waves (SAWs) with resonant frequencies up to 3.4 GHz were fabricated using a new CMOS compatible concept. Atomic force microscopy (AFM) and transmission electron microscopy (TEM) images were done to characterize the piezoelectric AlN layer. The roughness of the AlN surface is less than 3 nm. Due to the extremely flat AlN surface, it is possible to produce frequency filters with low losses due to the surface roughness. Furthermore, S-parameter measurements of SAW filters with different substrate resistivities were performed. Large substrate resistivities of 4000 Ωcm lead to a high out-of-band insertion loss due to the reduced capacitive coupling to the Silicon substrate, which is an important parameter for SAW applications. An additional SiO 2 layer can further increase the out-of-band insertion loss.

This work reports the bipolar resistive switching behavior of more than 100 back-end-of-line (BEOL) integrated 600×600nm2 TiN/HfO 2 /Ti/TiN MIM devices in a 4 kbit memory array. Reliable current-voltage switching characteristics were only observed for devices with a thickness ratio of 1 (10 nm HfO 2 /10nm Ti), indicating the importance of the interface chemistry of the Ti/HfO 2 interface. Moreover, the devices show good inter-cell uniformity and thus demonstrate promising prospects for embedded non-volatile memory (eNVM) applications.

A waveguide coupled Ge PIN photodiode showing 0.7A/W responsivity and 13GHz optical bandwidth at a low dark current of 12mA/cm2 is presented. Its unique features facilitate integration in a high-performance, photonic BiCMOS process.

Bipolar resistive switching in TiN/HfO2/Ti/TiN devices using a CMOS technology process is demonstrated. The performance metrics include a retention time >105 s and a cycling endurance in dc sweep mode >102. By controlling either the set current Iset or by setting an appropriate stop voltage Vstop, the devices hold the potential for multilevel operation. The results suggest that HfO2-based MIM devices with Si CMOS compatible metal electrodes may be well suited for future embedded nonvolatile memory applications.

Graphene based electron field emitter arrays consisting of cone-shaped silicon tips, a thin Al2O3 tunnel barrier, and graphene top electrode are fabricated. Due to the monolayered graphene top electrode, the electrons are able to tunnel through the Al2O3 layer and emit into the vacuum. The temperature behavior of the tunnel leakage current as well as the emission current is characterized.

Integrated AlN/SiO2/Si (1 0 0) delay lines for Rayleigh surface acoustic waves (SAWs) with resonant frequencies up to 3.4 GHz were fabricated using a new CMOS compatible concept. Different thicknesses of textured AlN films with wurtzite structure were deposited on tungsten-based interdigital transducers embedded in a SiO2 layer by reactive pulse dc-sputtering at a temperature of 200 °C. Rocking curves of the films indicate c-axis (0 0 0 1) oriented, textured piezoelectric AlN films with a full-width at half-maximum of 1.88°. The determined propagation loss and coupling factor K2 of these SAW devices are 0.07 dB/λ and 0.78%, respectively. Different Rayleigh modes with acoustic velocities up to 5770 m s−1 are observed. By varying the wavelength, number of fingers as well as the length (i.e., the separation between the transducers) of the delay lines, the impact of several physical parameters on the frequency responses (S11, S21) was studied. The influence of the AlN thickness and of the orientation of the delay lines on the silicon (1 0 0) wafers was also investigated. Finite element method simulations were applied to model the resonant frequencies, giving resonant frequencies in reasonable agreement with the experimental data.

We demonstrate the electrical generation of GHz surface acoustic waves (SAWs) on silicon chips using a process entirely compatible with standard CMOS fabrication. In this process, the interdigitated acoustic transducers are embedded in a silicon dioxide layer, which is subsequently coated with a piezoelectric ZnO film. We show that delay lines with sub-μm wavelength fabricated using this process reach resonance frequencies approaching 4 GHz.

The authors demonstrate bipolar resistive switching in TiN/HfO2/Ti(top)/TiN devices using a (Bi) complementary metal-oxide semiconductor (CMOS) compatible technology process. The device performance includes a cycling endurance in dc sweeping mode >103. The results suggest that HfO2-based metal-insulator-metal devices with Si CMOS compatible metal electrodes may be well suited for future embedded nonvolatile memory applications. However, hysteretic current-voltage characteristics were only observed for a Ti top adlayer, whereas a Ti bottom adlayer integration did not show any resistive switching effect. Using x-ray photoelectron spectroscopy, the authors examined the interface chemistry of the Ti/HfO2 interface. It is clearly observed that Ti top adlayer deposition results in an increased nitrogen- and oxygen-gettering activity in contrast to Ti bottom adlayer. It follows that the formation of a nonstoichiometric HfO2 layer at the Ti/HfO2 interface is crucial for resistive switching.