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In this paper, we address the problem of predicting complex, nonlinear spatio-temporal dynamics when available data are recorded at irregularly spaced sparse spatial locations. Most of the existing deep learning models for modelling spatio-temporal dynamics are either designed for data in a regular grid or struggle to uncover the spatial relations from sparse and irregularly spaced data sites. We propose a deep learning model that learns to predict unknown spatio-temporal dynamics using data from sparsely-distributed data sites. We base our approach on the radial basis function (RBF) collocation method which is often used for meshfree solution of partial differential equations. The RBF framework allows us to unravel the observed spatio-temporal function and learn the spatial interactions among data sites on the RBF-space. The learned spatial features are then used to compose multilevel transformations of the raw observations and predict its evolution in future time steps. We demonstrate the advantage of our approach using both synthetic and real-world climate data. This article is part of the theme issue 'Data-driven prediction in dynamical systems'. [ABSTRACT FROM AUTHOR]

In this work, we present a Quantum Hopfield Associative Memory (QHAM) and demonstrate its capabilities in simulation and hardware using IBM Quantum Experience.. The QHAM is based on a quantum neuron design which can be utilized for many different machine learning applications and can be implemented on real quantum hardware without requiring mid-circuit measurement or reset operations. We analyze the accuracy of the neuron and the full QHAM considering hardware errors via simulation with hardware noise models as well as with implementation on the 15-qubit ibmq_16_melbourne device. The quantum neuron and the QHAM are shown to be resilient to noise and require low qubit overhead and gate complexity. We benchmark the QHAM by testing its effective memory capacity and demonstrate its capabilities in the NISQ-era of quantum hardware. This demonstration of the first functional QHAM to be implemented in NISQ-era quantum hardware is a significant step in machine learning at the leading edge of quantum computing. [ABSTRACT FROM AUTHOR]

Background: Systemic thromboembolism is a known complication of rheumatic mitral stenosis (RMS) in sinus rhythm (SR). Left atrial appendage (LAA), the commonest site of thrombus formation is usually hypocontractile (inactive) in such patients. We aimed to study the prevalence of LAA inactivity (LAAI) in severe RMS and assess its independent predictors. Methods: The study population consisted of 100 patients of severe RMS in SR. Transthoracic and transesophageal echocardiography were done to assess LAA contractile function. Patients with LAA‐peak emptying velocity < 25 cm/seconds were defined as having LAAI. Results: The mean age of study subjects was 31.66±8.69 years and 56% were females. 73% patients had LAAI (Group A), while remaining 27% had normal LAA function (Group B). Mitral‐valve area (MVA) and lateral annulus systolic velocity (Sa‐wave) were significantly lower while mitral valve mean gradient (MVMG) and serum fibrinogen were significantly higher (all p‐values < 0.001) in group A patients. On multivariate binary logistic regression analysis, MVMG (p < 0.001), Sa‐wave (p = 0.02), and serum fibrinogen (p = 0.005) were independent predictors of LAAI. Optimal cut‐off values of MVMG, Sa‐wave and serum fibrinogen for predicting LAAI were 11.5 mm Hg, 6.8 cm/seconds and 300 mg/dl, respectively. Sixty‐Seven (90.55%) patients in group A compared to 13(48.1%) in group B had LA/LAA smoke. LAAI was the only independent predictor of left atrium (LA)/LAA smoke with or without associated thrombus. Conclusion: There is high prevalence of LAAI in patients of severe MS in SR. MVMG, Sa‐wave, and serum fibrinogen levels are independent predictors of LAAI. LAAI is an independent predictor of LA/LAA smoke with or without associated thrombus. [ABSTRACT FROM AUTHOR]

This paper presents an on-chip digitally programmable thermal coupling emulation framework, referred to as the field-programmable thermal emulator (FPTE), for online characterization of power pattern, time-varying thermal field, and associated changes in the electrical characteristics of the transistors. A test chip was designed in 130-nm CMOS to validate the test structure. The measurement results demonstrated the ability of FPTE to emulate various power patterns and capture the effects on temperature and circuit performance. The test chip is used to explore and identify thermal coupling. The potential application of FPTE moves beyond thermal package tests and is capable of being used as chip-level thermal condition prediction and management infrastructure. [ABSTRACT FROM PUBLISHER]

This paper presents a dynamic voltage scaling (DVS) compatible single-inductor multiple-output (SIMO) voltage regulation module that enables smaller passives for a given output power, while maintaining power quality (low output ripple), suppressing cross regulation, and improving efficiency at high switching frequency. First, continuous-conduction mode (CCM) operation is utilized to deliver higher output power for a smaller inductance; the cross-regulation in CCM operation is suppressed using a novel power-weighted CCM controller. Second, a modified power stage filter is presented using floating capacitors that utilize the Miller effect to reduce the switching frequency of the output, while maintaining the power quality. The operating principles, stability, and circuit level design of the proposed SIMO VR are presented. The design is demonstrated through a 130-nm CMOS test chip that generates four outputs, each ranging from 200 to 600 mV, from a 1.2-V input. The measurements demonstrate a 20-MHz operation, the pulse width modulation signal of the power stage with 500-nH inductor, and 1-μF total load capacitance, while delivering a output power density of 150 mW/μH·μF. The test chip demonstrates DVS speed of 120 mV/μs, 73% peak efficiency at a load of 40 mA, and as high as 40% efficiency improvement using the modified power filer. [ABSTRACT FROM AUTHOR]

Self-powered wireless sensors require power delivery systems capable of harvesting from very low input voltage while consuming minimal bias current. This paper presents a multistage boost regulator capable of generating 3 V to supply RF blocks in self-powered wireless sensors from 10 mV input voltage. The bias power consumption is minimized using automated bias gating. The efficiency of the multistage conversion at a high conversion ratio is enhanced through the regulation and control of the intermediate-node voltage. A test chip, fabricated in 130 nm CMOS, demonstrates functional operation from as low as 10 mV input and consumes 190 nA bias current. Single-stage boost regulator demonstrates Peak efficiency of 89%, while the cascaded two stage peaks at 72%. In the cascaded system, the variable intermediate-node voltage operation shows up to 9% efficiency improvement over fixed intermediate-node voltage when operating at high conversion ratio. [ABSTRACT FROM PUBLISHER]

With continued technology scaling and increased power and thermal densities, processor operation and performance are increasingly dominated by physical phenomena. Microarchitectural approaches to mitigate these effects must be based on a profound understanding of how the physics is manifested in microarchitectural executions and system-level properties, such as performance, energy efficiency, or lifetime reliability. This requires a modeling and simulation environment that incorporates multiple physical phenomena and their concurrent interactions with microarchitecture. In this paper, we introduce an integrated power, thermal, and reliability modeling framework, KitFox. The goal of KitFox framework is to facilitate research explorations at the intersection of applications, microarchitectures, and various physical phenomena, including energy, power, thermal, cooling, and reliability. The KitFox framework implements a standard interface to bridge multiple physical models, where individual models are encapsulated into libraries and are interchangeable. This paper describes the design methodology of the library framework that orchestrates various implementations of physical models and standardized interface to cycle-level microarchitecture simulators. Several use cases are presented to demonstrate the range of modeling capabilities of KitFox. [ABSTRACT FROM PUBLISHER]

3-D integrated circuits (3-D ICs) are expected to have shorter wirelength, better performance, and less power consumption than 2-D ICs. These benefits come from die stacking and use of through-silicon vias (TSVs) fabricated for interconnections across dies. However, the use of TSVs has several negative impacts such as area and capacitance overhead. To predict the quality of 3-D ICs more accurately, TSV-aware 3-D wirelength distribution models considering the negative impacts were developed. In this paper, we apply an optimal buffer insertion algorithm to the TSV-aware 3-D wirelength distribution models and present various prediction results on wirelength, delay, and power consumption of 3-D ICs. We also apply the framework to 2-D and 3-D ICs built with various combinations of process and TSV technologies and predict the quality of today and future 3-D ICs. [ABSTRACT FROM PUBLISHER]

An inductive boost regulator is presented that can harvest energy over a wide input voltage range. The wide input range is enabled by a current-based analog oscillator capable of providing very high duty cycle. The analog control circuits are designed to operate at subthreshold voltage to enable low voltage all electronic autonomous startup. A test chip designed in 130-nm CMOS demonstrates energy harvesting from as low as 12-mV input while biased by an external 1-V battery and autonomous (without using any additional device or battery) startup above 305 mV at output. The design typically consumes 3.5-μA standby current, achieves peak efficiency of 82%, and can regulate output from 0.66 to 3.3 V. The booster is coupled with a thermoelectric generator and the integrated system delivers output power of 6 μW at ~2 °C temperature difference to a maximum of 12 mW at ~50 °C temperature difference. [ABSTRACT FROM AUTHOR]

The Internet of Things provides exciting new capabilities as well as an alternative model for semiconductors--the deployment of vast numbers of small chips-but its success will require solving new VLSI design challenges. [ABSTRACT FROM PUBLISHER]

We present an analysis of the relationship between input images and energy consumption in error tolerant image processing. Under aggressive voltage scaling, the output image quality of image processing depends on input images for two reasons: 1) error tolerance among images is naturally disparate in terms of perceptual image quality assessment, and 2) the error rate under aggressive voltage scaling varies by input image types. Based on both effects, the supply voltage can be optimized for a given quality requirement so as to achieve ultralow power/energy dissipation. Our analysis demonstrates the significance of the accurate delay estimation, which depends on not only combinational inputs but also the previous state of the logic. We present a new sequential model for accurate error estimation. Based on the model, our experimental results demonstrate that different input image types lead to very different output quality. We also present the effect of process variation on the relationship between input image and output quality. The dependence of energy consumption on input images provides a new perspective for low-power multimedia and image processing system design. [ABSTRACT FROM PUBLISHER]

In this paper, we present analytical models for fast estimation of coupling capacitance of square-shaped through-silicon vias (TSVs) in three-dimensional integrated circuits (3D ICs). Errors between our model and Synopsys Raphael simulation on regular TSV structures remain less than 6.03% while the computation time of our model for capacitance estimation is negligible. We also develop a simple capacitance estimation technique to extract TSV-to-TSV coupling capacitance in general layouts. Average errors between our model and Raphael simulation on random TSV structures is 5.06%–8.24%, and maximum errors remain less than 18.91% which is tolerable for fast capacitance estimation in computer-aided design area. [ABSTRACT FROM PUBLISHER]

We present a generic data-driven nonparametric analyzer (GDNA) to estimate the impact of process variations device properties and circuit functionalities in nanometer technologies. The mathematical framework of GDNA uses a kernel estimator that eliminates the need for a priori assumption of nature of variation (i.e., no a priori choice is required for the density of a random variable). Furthermore, a generic tail probability estimator is developed that uses the kernel estimator to predict low occurrence probabilities using a small set of observed samples. Verifications using statistical simulations show that GDNA can reliably predict variability in device/circuit properties and hence facilitate technology development and circuit design under process variation. [ABSTRACT FROM AUTHOR]

In this paper, we present a postsilicon-tuning technique to improve parametric yield of SRAM array using body bias (BB). First, we show that, although parametric failures in SRAM are due to local random intradie variations, the parametric failures increase at extreme interdie corners. Next, we show that proper BB can reduce different types of parametric failures. Finally, we show that adaptive application of BB to different dies, based on their interdie corners, reduces the total number of parametric failures in those dies. This helps to repair the faulty dies at different interdie corners, thereby improving SRAM yield. We show that postsilicon-tuning using BB can result in significant yield enhancement for SRAM (8%-25% in predictive 70-nm technology). [ABSTRACT FROM AUTHOR]

Abstract: Double gate (DG) FETs have emerged as the most promising technology for sub-50nm transistor design. However, analysis and control of the gate tunneling leakage in DGFET is necessary to fully exploit their advantages. In this paper we have modeled (numerically and analytically) and analyzed gate-to-channel leakage in different DGFET structures, viz., doped body symmetric device (SymDG) with polysilicon gates, intrinsic body symmetric device with metal gates (MGDG) and intrinsic body asymmetric device (AsymDG) with different front and back gate materials. It is observed that, use of (near-mid-gap) metal gate and intrinsic body can result in 3–4× reduction in gate-to-channel leakage compared to the SymDG structure. [Copyright &y& Elsevier]

In this paper, we propose a methodology to model and optimize FinFET devices for robust and low-power SRAMs. We propose to optimize the gate sidewall offset spacer thickness to simultaneously minimize leakage current and drain capacitance to on-current ratio in FinFET. With the source/drain extension doping controlled at the outer edges of the spacer, the thickness of the spacer determines the channel length. Optimization reduces the sensitivity of the device threshold voltage to the fluctuations in silicon thickness (by 32%) and gate length (by 73%). Our analysis shows that optimization of spacer thickness results in 65% reduction in SRAM cell leakage and improves cell read-failure probability (by 200 ×) compared to conventional FinFET SRAM. Access time of an SRAM cell designed with optimized devices is comparable to conventional SRAM. We also compared the optimized-spacer-thickness SRAM cell with one designed using longer gate length and minimum-spacer-thickness transistors. The long-channel-device-based SRAM cell is marginally robust than optimized SRAM; however, increased gate-edge direct-tunneling leakage and parasitic capacitances degrade the power consumption and access time. [ABSTRACT FROM AUTHOR]

This paper models and analyzes subthreshold and gate leakage currents in different double-gate (DG) devices, namely, a doped body symmetric device with polysilicon gates, an intrinsic body symmetric device with metal gates, and an intrinsic body asymmetric device with different front and back gate materials. The effect of variations in device parameters on the leakage components is also analyzed. Using the developed models, digital circuits (logic gates and static random access memory cells) designed with different DG structures are also analyzed. The analysis shows that the use of (near mid-gap) metal gate and intrinsic body devices significantly reduces both the total leakage and its sensitivity to parametric variations in DG devices and circuits. [ABSTRACT FROM AUTHOR]

In nanoscale complementary metal-oxide-semiconductor (CMOS) devices, a significant increase in subthreshold, gate, and reverse-biased junction band-to-band-tunneling (BTBT) leakage results in large leakage power in logic circuits. Leakage components interact with each other at the device level (through device geometry and the doping profile) and at the circuit level (through the node voltages). Due to the circuit-level interaction of the different leakage components, the leakage of a logic gate depends on the circuit topology, i.e., the number and the nature of the other logic gates connected to its input and output. In this paper, the effect of loading on a leakage of a circuit is analyzed for the first time. The authors have also proposed a method to accurately estimate the total leakage in a logic circuit from its logic-level description considering the impact of loading and transistor stacking. [ABSTRACT FROM AUTHOR]

In this paper, we have analyzed and modeled failure probabilities (access-time failure, read/write failure, and hold failure) of synchronous random-access memory (SRAM) cells due to process-parameter variations. A method to predict the yield of a memory chip based on the cell-failure probability is proposed. A methodology to statistically design the SRAM cell and the memory organization is proposed using the failure-probability and the yield-prediction models. The developed design strategy statistically sizes different transistors of the SRAM cell and optimizes the number of redundant columns to be used in the SRAM array, to minimize the failure probability of a memory chip under area and leakage constraints. The developed method can be used in an early stage of a design cycle to enhance memory yield in nanometer regime. [ABSTRACT FROM AUTHOR]

Dramatic increase of subthreshold, gate and reverse biased junction band-to-band-tunneling (BTBT) leakage in scaled devices results in the drastic increase of total leakage power in a logic circuit In this paper, a methodology for accurate estimation of the total leakage in a logic circuit based on the compact modeling of the different leakage current in nanoscaled bulk CMOS devices has been developed. Current models have been developed based on the device geometry, two-dimensional doping profile, and operating temperature. A circuit-level model of junction BTBT leakage has been developed. Simple models of the subthreshold current and the gate current have been presented. Also, the impact of quantum mechanical behavior of substrate electrons, on the circuit leakage has been analyzed. Using the compact current model, a transistor has been modeled as a stun of current sources (SCS). The SCS transistor model has been used to estimate the total leakage in simple logic gates and complex logic circuits (designed with transistors of 25-nm effective length) at room and elevated temperatures. [ABSTRACT FROM AUTHOR]

The high leakage current in deep submicron regimes is becoming a significant contributor to the power dissipation of CMOS circuits as the threshold voltage, channel length, and gate oxide thickness are reduced. Consequently, the identification and modeling of different leakage components is very important for the estimation and reduction of leakage power, especially in the low power applications. This paper explores the various transistor intrinsic leakage mechanisms including the weak inversion, the drain-induced barrier lowering, the gate-induced drain leakage, and the gate oxide tunneling. [ABSTRACT FROM AUTHOR]

This article presents a low-overhead energy harvesting and delivery system (EHDS) with pulse frequency modulated (PFM) integrated voltage regulator (IVR) power conversion and self-tuned maximization of system output power. A novel load-inclusive time-based maximum power point tracking (LI-TB-MPPT) is developed to provide centralized tuning of PFM-IVR operation based on both source capabilities and load demand on-the-fly, and a configurable fractional sample and hold circuit provides adaptive harvesting window control. The proposed EHDS enables robust harvesting while relieving the use of high passives, with over two orders of magnitude reduction, at the cost of only slight decrease in end-to-end efficiency compared to prior works. Furthermore, a low-overhead wake-up assist circuit utilizes cold-configuration of harvesting sources for efficient and accelerated cold-start. The proposed EHDS is demonstrated in a 65 nm CMOS process with commercial photovoltaic energy harvesting modules. Using only 1.2 and 1 $\mu$ H of passives, measured results show a peak 74.9% end-to-end efficiency (simulated up to 85% at 47 $\mu$ H) and a fast startup time of 3.8 ms. Up to 15% increase in conversion efficiency against load and input voltage variations is achieved with LI-TB-MPPT. The results demonstrate a compact solution for self-sustained cost-restricted stand-alone systems. [ABSTRACT FROM AUTHOR]

Obstruction in supracardiac total anomalous pulmonary venous connection (TAPVC) may be seen in 50% of cases. We describe here successful echocardiographic diagnosis of obstruction at an unusual and undescribed location in a supracardiac TAPVC. The patient was successfully managed by surgery. [ABSTRACT FROM AUTHOR]

Spatio-temporal dynamics of physical processes are generally modeled using partial differential equations (PDEs). Though the core dynamics follows some principles of physics, real-world physical processes are often driven by unknown external sources. In such cases, developing a purely analytical model becomes very difficult and data-driven modeling can be of assistance. In this paper, we present a hybrid framework combining physics-based numerical models with deep learning for source identification and forecasting of spatio-temporal dynamical systems with unobservable time-varying external sources. We formulate our model PhICNet as a convolutional recurrent neural network (RNN) which is end-to-end trainable for spatio-temporal evolution prediction of dynamical systems and learns the source behavior as an internal state of the RNN. Experimental results show that the proposed model can forecast the dynamics for a relatively long time and identify the sources as well. [ABSTRACT FROM AUTHOR]

Background: COVID-19 vaccines are highly immunogenic but cardiovascular effects of these vaccines have not been properly elucidated. Objectives: To determine impact of COVID-19 vaccination on mortality following acute myocardial infarction (AMI). Methods: This was a single center retrospective observation study among patients with AMI enrolled in the the North India ST-Elevation Myocardial Infarction (NORIN-STEMI) registry. In all the enrolled patients, data regarding patient's vaccination status including details on type of vaccine, date of vaccination and adverse effects were obtained. All enrolled subjects were followed up for a period of six months. The primary outcome of the study was all-cause mortality both at one month and at six months of follow-up. Propensity-weighted score logistic regression model using inverse probability of treatment weighting was used to determine the impact of vaccination status on all-cause mortality. Results: A total of 1578 subjects were enrolled in the study of whom 1086(68.8%) were vaccinated against COVID-19 while 492(31.2%) were unvaccinated. Analysis of the temporal trends of occurrence of AMI post vaccination did not show a specific clustering of AMI at any particular time. On 30-day follow-up, all-cause mortality occurred in 201(12.7%) patients with adjusted odds of mortality being significantly lower in vaccinated group (adjusted odds ratio[aOR]: 0.58, 95% CI: 0.47–0.71). Similarly, at six months of follow-up, vaccinated AMI group had lower odds of mortality(aOR: 0.54, 95% CI: 0.44 to 0.65) as compared to non-vaccinated group. Conclusions: COVID-19 vaccines have shown to decrease all-cause mortality at 30 days and six months following AMI. [ABSTRACT FROM AUTHOR]

The article presents a case study of a 21-year-old male diagnosed with post-traumatic ruptures hepatic artery pseudoaneurysm (HAP). It is noted that the patients was reported to have blunt trauma to his right abdomen and chest with clinical peritonitis features. It points out that he underwent emergency hepatic artery embolization to treat his HAP.

Phenytoin, a class IB anti-arrhythmic agent, is considered the drug of choice for ventricular arrhythmias due to digoxin toxicity. We report successful reversion of polymorphic ventricular tachycardia secondary to amiodarone toxicity by phenytoin administration that was resistant to the conventional drugs (magnesium sulphate, lidocaine and atropine). [ABSTRACT FROM AUTHOR]

Reports on the case of an 18-year-old lady patient presented with Takayasu arteritis. Medical history of the patient; Result of her medical examination; Involvement of the coronary artery in patients with Takayasu arteritis.

Carbon nanotube field-effect transistors (CNFETs) are being extensively studied as possible successors to CMOS. Novel device structures have been fabricated and device slmulators have been developed to estimate their performance in a sub-10-nm transistor era. This paper presents a novel method of circuit-compatible modeling of single-walled semiconducting CNFETs in their ultimate performance limit, For the first time, both the I-V and the CV characteristics of the device have been efficiently modeled for circuit simulations. The model so developed has been used to simulate arithmetic and logic blocks using HSPICE. [ABSTRACT FROM AUTHOR]

Underwater sound propagation is primarily driven by a nonlinear forward model relating variability of the ocean sound speed profile (SSP) to the acoustic observations (e.g., eigenray arrival times). Ocean acoustic tomography (OAT) methods aim at reconstructing SSP variations (with respect to a reference environment) from changes of the acoustic measurements between multiple source-receiver pairs. This article investigates the performance of three different OAT methods: (1) model-based methods (i.e., classical ray-based OAT using a linearized forward model), (2) data-driven methods (such as deep learning) to directly learn the inverse model, and (3) a hybrid solution [i.e., the neural adjoint (NA) method], which combines deep learning of the forward model with a standard recursive optimization to estimate SSPs. Additionally, synthetic SSPs were generated to augment the variability of the training set. These methods were tested with modeled ray arrivals calculated for a downward refracting environment with mild fluctuations of the thermocline. Idealized towed and fixed source configurations are considered. Results indicate that merging data-driven and model-based methods can benefit OAT predictions depending on the selected sensing configurations and actual ray coverage of the water column. But ultimately, the robustness of OAT predictions depends on the dynamics of the SSP variations. [ABSTRACT FROM AUTHOR]

High-performance computing-based electromagnetic (EM) emulators are used to simulate real-time complex EM wave interactions between multiple radar targets, transmitters, and receivers. The radar cross section (RCS) of the radar targets are required to be stored as a table; however, the needed storage size increases dramatically with the angle and frequency sampling density. In this article, we present an innovative approach of constructing a concise spherical harmonic-based anisotropic point scatterer model that the emulators can use as part of the computations. The point scatterer model is constructed directly from the precomputed RCS data. First, we use only the monostatic RCS data and compute the spherical harmonic-based monostatic point scatterer model by solving a linear least-squares problem which has a group sparsity constraint. Then, we further compute the spherical harmonic-based bistatic point scatterer model using the full bistatic RCS data. The problem is formulated as a bilinear least-squares problem. The problem is solved using the normalized iterative algorithm, which linearly solves two parameters in a back and forth manner. The results show that the point scatterer model can effectively represent the bistatic RCS data of a radar target. [ABSTRACT FROM AUTHOR]

This paper presents a voltage regulator topology, implemented using low-voltage devices, for converting high input voltage (>4.5 V) to low output voltages with fine-grain control (0.3 to 1 V). The topology merges a Dickson's switched-capacitor stage with a current-mode inductive buck stage, and optimizes the frequency of operations to reduce the overall passive size. The proposed two-stage hybrid regulator, designed in 130-nm standard digital process, operates from 4.8 to 6 V at input and regulates output voltage as low as 0.3 V with a maximum output power of 90 mW and a peak efficiency of 69%. [ABSTRACT FROM PUBLISHER]

Specialized accelerators have become prevalent in many mobile computing platforms for their ability to perform certain tasks, such as image processing, at a lower power cost than a generalized CPU or GPU. In this article, the authors focus on using cellular neural networks (CNNs) as a specialized accelerator. CNN is a neural computing paradigm that is well suited for image processing applications. However, hardware implementations were originally developed to handle only relatively small image sizes. The authors propose SP-CNN, an architecture and a multiplexing algorithm that provides scalability to CNN applications. The authors demonstrate the proposed multiplexing algorithms over a set of six image processing benchmarks and present a performance analysis of SP-CNN. [ABSTRACT FROM PUBLISHER]

This paper studies the application of tunnel FET (TFET) in designing a low power and robust cellular neural network (CNN)-based associative memory (AM). The lower leakage, steeper switching slope, and higher output resistance of TFET are exploited in designing an ultralow-power TFET-based operational transconductance amplifier (OTA). A TFET-OTA is utilized as a programmable synaptic weight multiplier for CNN. The ultralow-power of TFET-OTA enables a higher connectivity network even at a lower power, and thereby improves the memory capacity and input pattern noise tolerance of CNN-AM for low power applications. The TFET-based higher connectivity CNN also exploits the unique characteristics of TFET to improve the throughput efficiency of CNN-AM. [ABSTRACT FROM AUTHOR]

This article presents an integrated circuits (ICs) for authentication with visible-light-based interrogation. The design uses an on-chip DC–DC boost regulator that wakes up and supplies remaining circuits via visible light upon interrogation. The data transfer is also performed via visible-light-based communication using on-chip photodiodes. An on-chip PRINCE cipher is used for encryption to provide counterfeit resistance. A prototype test-chip fabricated in 65 nm complementary metal-oxcide-semiconductor (CMOS) consumes 2.29 μW standby power and achieves 53.8 kb/s data receive rate demonstrating ultralow-power interrogation. Measurements of electromagnetic emission-based side-channel attack show that 280000 encryptions are necessary to reveal the secret key of the tag. [ABSTRACT FROM AUTHOR]

This paper investigates the design of logarithmic CMOS image sensor with 3-D integrated image compression unit. The image sensor consists of a pixel array, column circuits, an array of analog-to-digital converters, a frame memory (image buffer) array, and a signal processing unit for image compression. This paper analyzes the correlation between the power dissipation in the image compression unit and the spatial noise characteristics of the photodiode array in the 3-D image sensor. The coupled power, performance, thermal, and noise analysis is performed considering 180-nm CMOS technology. The coupled analysis shows that, due to die-to-die thermal coupling, 3-D stacking of the image compression unit, although provides for better energy efficiency, results in a strong interaction between image quality, desired image throughput, and environmental factors, such as lighting conditions or available channel bandwidth. [ABSTRACT FROM AUTHOR]

In this article, we present an effective methodology for co-design, co-analysis, and the system-level optimization of chiplet/interposer power delivery network (PDN) in 2.5-D integrated chip (IC) designs. In our methodology, we first generate a commercial-grade heterogeneous 2.5-D IC designs including full signal routing and power delivery. We then perform our PDN co-analysis in frequency and time domains on the entire PDN to evaluate various mechanisms added to our PDN designs. Based on our co-analysis results, we perform the system-level optimization on both interposer and chiplet PDNs with the stable performance of power delivery. Finally, we perform power, performance, and area (PPA) analysis and power integrity (PI) on our 2.5-D designs and discuss tradeoffs in chiplet and interposer levels due to PDN optimization. Our experiments show 27.17% improvement in the overall IR-drop in the optimized 2.5-D IC design by increasing the interposer PDN occupancy by 5.52% and inserting the additional PDN grids in chiplet designs. However, we also observe tradeoffs in terms of PPA and PI. By PDN optimization, the optimized design has an 11.6% increase of the total power, while the area of 2.5-D design remains the same. Moreover, from the perspective of PI, the tradeoffs are shown by 0.6% reduction of power efficiency, 32.6% higher output ripple, and 31.5% higher initial ringing because of an inductive behavior of interposer PDN in the optimized design. [ABSTRACT FROM AUTHOR]

This paper presents a design methodology for robust and low-energy clock networks for ultralow voltage (ULV) circuits. We show that both clock slew and skew play important roles in achieving high maximum operating frequency (F\max) and low clock energy in ULV circuits. In addition, clock networks in ULV circuits are highly sensitive to process variations. We propose a variation-aware methodology that controls both clock skew and slew to maximize F\max and minimize clock power. In addition, we implement dynamic programming (DP)-based ULV clock routing and buffering methods (deferred merging and embedding) for deterministic and statistical conditions. Experimental results show that our clock network design method achieves lower energy (more than 20% savings) at comparable or even higher F\max compared with the existing methods. [ABSTRACT FROM AUTHOR]

In this paper, a proactive thermal management technique called "power multiplexing" is explored for many-core processors. Power multiplexing involves redistribution of the locations of active cores at regular time intervals to obtain uniform thermal profile with low peak temperature. Three different migration policies namely random, cyclic, and global coolest replace have been employed for power multiplexing and their efficacy in reducing the peak temperature and thermal gradient on chip is investigated. For a given migration frequency, global coolest replace policy is found to be the most effective among the three policies considered as this policy provides 10° C reduction in peak temperature and 20°C reduction in maximum spatial temperature difference on a 256 core chip. Power configuration on the chip is characterized by a parameter called "proximity index" which emerges as an important parameter to represent the spatial power distribution on a chip. We also notice that the overall performance of the chip could be improved by 10% using global multiplexing. [ABSTRACT FROM AUTHOR]

The efficient usage of thermoelectric (TE) devices for microelectronics cooling application requires investigation and remedy of various obstacles such as integration of these devices with electronic package, parasitic contact resistances, and utilization of appropriate current pulses. We develop a computational model to investigate the effect of steady state and transient mode of operation of ultrathin thermoelectric cooler (TEC) devices on hot-spot cooling considering the effect of crucial thermal and electrical contact resistances. Our analysis shows that the transient pulses can be very effective in reducing the hot-spot temperature by 6–7^\circC in addition to the cooling achieved by the steady state current through the TEC device. We correlate the important characteristics of the transient temperature behavior of hot-spot under the TEC operation such as the maximum temperature drop (\Delta T\max), time taken to achieve \Delta T\max and temperature overshoot after turning off pulse current with the electrical and thermal contact resistances and Seebeck coefficient of the TE material. It has been observed that thermal and electrical contact resistances play a very crucial role in the performance of TEC devices as high values of these resistances can significantly diminish the effect of Peltier cooling during steady state operation. The effect of these parasitic resistances is even higher for the transient cooling of hot-spots by the pulsed current through the TEC device. High Seebeck coefficient of TE materials is desirable as it increases the figure of merit of TE devices. However, cooling capabilities of heat sink may become bottleneck to realize the benefits of very high Seebeck coefficient as the back heat flow from the hot side to cold side of TEC device diminishes the degree of cooling achieved by these ultrathin TECs. [ABSTRACT FROM PUBLISHER]

Under inter-die and intra-die parameter variations, the delay of a pipelined circuit follows a statistical distribution. This paper presents analytical models to estimate yield for a pipelined design based on delay distributions of individual pipe stages. Using the proposed models, it is shown that a change in logic depth and an imbalance between stage yields can improve the design yield and the area of a pipeline a circuit. A novel statistical methodology is developed to enhance yield of a pipelined circuit under an area constraint. Based on the concept of area borrowing, the results show that incorporating a proper imbalance among stage areas in a four-stage pipeline improves design yield up to 15.4% for the same area (and reduces area up to 8.4% under a yield constraint) compared with a balanced design. [ABSTRACT FROM AUTHOR]

Objectives: Myocardial injury during active coronavirus disease‐2019 (COVID‐19) infection is well described; however, its persistence during recovery is unclear. We assessed left ventricle (LV) global longitudinal strain (GLS) using speckle tracking echocardiography (STE) in COVID‐19 recovered patients and its correlation with various parameters. Methods: A total of 134 subjects within 30–45 days post recovery from COVID‐19 infection and normal LV ejection fraction were enrolled. Routine blood investigations, inflammatory markers (on admission) and comprehensive echocardiography including STE were done for all. Results: Of the 134 subjects, 121 (90.3%) were symptomatic during COVID‐19 illness and were categorized as mild: 61 (45.5%), moderate: 50 (37.3%) and severe: 10 (7.5%) COVID‐19 illness. Asymptomatic COVID‐19 infection was reported in 13 (9.7%) patients. Subclinical LV and right ventricle (RV) dysfunction were seen in 40 (29.9%) and 14 (10.5%) patients, respectively. Impaired LVGLS was reported in 1 (7.7%), 8 (13.1%), 22 (44%) and 9 (90%) subjects with asymptomatic, mild, moderate and severe disease, respectively. LVGLS was significantly lower in patients recovered from severe illness(mild: ‐21 ± 3.4%; moderate: ‐18.1 ± 6.9%; severe: ‐15.5 ± 3.1%; p < 0.0001). Subjects with reduced LVGLS had significantly higher interleukin‐6 (p < 0.0001), C‐reactive protein (p = 0.001), lactate dehydrogenase (p = 0.009), serum ferritin (p = 0.03), and troponin (p = 0.01) levels during index admission. Conclusions: Subclinical LV dysfunction was seen in nearly a third of recovered COVID‐19 patients while 10.5% had RV dysfunction. Our study suggests a need for closer follow‐up among COVID‐19 recovered subjects to elucidate long‐term cardiovascular outcomes. [ABSTRACT FROM AUTHOR]

Heart hand syndromes are characterized by radial abnormalities and associated defects in the heart. We here describe an extremely rare heart hand syndrome known as Baller-Gerold syndrome. [ABSTRACT FROM AUTHOR]

Heart hand syndromes are characterized by radial abnormalities and associated defects in the heart. We here describe an extremely rare heart hand syndrome known as Baller-Gerold syndrome. [ABSTRACT FROM AUTHOR]

Percutaneous transvenous mitral commissurotomy is an effective and safe alternative to surgical treatment, in selected patients of rheumatic mitral stenosis. It is usually performed under fluoroscopic guidance in the catheterization laboratory. We report the successful performance of emergency mitral commissurotomy by the Inoue balloon at bedside under sole transthoracic echocardiographic guidance in a critically ill patient. [ABSTRACT FROM AUTHOR]

TREHAN, V.,et al.: Nonsurgical Management of Cardiac Tamponade Caused by a Temporary Pacemaker Lead. Right ventricular perforation secondary to temporary pacemaker lead, resulting in cardiac tamponade, is a rare but life-threatening complication. Surgery is usually the definitive management described for such cases. We describe successful sealing of such a perforation by percutaneous instillation of cyanoacrylate glue, through a guiding catheter in the pericardial sac at the perforation site.(PACE 2005; 28:242–244) [ABSTRACT FROM AUTHOR]