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The promise of quantum computing lies in harnessing programmable quantum devices for practical applications such as efficient simulation of quantum materials and condensed matter systems. One important task is the simulation of geometrically frustrated magnets in which topological phenomena can emerge from competition between quantum and thermal fluctuations. Here we report on experimental observations of equilibration in such simulations, measured on up to 1440 qubits with microsecond resolution. By initializing the system in a state with topological obstruction, we observe quantum annealing (QA) equilibration timescales in excess of one microsecond. Measurements indicate a dynamical advantage in the quantum simulation compared with spatially local update dynamics of path-integral Monte Carlo (PIMC). The advantage increases with both system size and inverse temperature, exceeding a million-fold speedup over an efficient CPU implementation. PIMC is a leading classical method for such simulations, and a scaling advantage of this type was recently shown to be impossible in certain restricted settings. This is therefore an important piece of experimental evidence that PIMC does not simulate QA dynamics even for sign-problem-free Hamiltonians, and that near-term quantum devices can be used to accelerate computational tasks of practical relevance., Experimental demonstration of quantum speedup that scales with the system size is the goal of near-term quantum computing. Here, the authors demonstrate such scaling advantage for a D-Wave quantum annealer over analogous classical algorithms in simulations of frustrated quantum magnets.

An overview of quantum computers based on the annealing paradigm and manufactured by D-Wave is given. An introductory survey of this approach to quantum computing (QC), together with a snapshot of what is known about performance, is presented. Evidence-based predictions about developments in this region of the QC space are presented.

Understanding magnetic phases in quantum mechanical systems is one of the essential goals in condensed matter physics, and the advent of prototype quantum simulation hardware has provided new tools for experimentally probing such systems. We report on the experimental realization of a quantum simulation of interacting Ising spins on three-dimensional cubic lattices up to dimensions 8 × 8 × 8 on a D-Wave processor (D-Wave Systems, Burnaby, Canada). The ability to control and read out the state of individual spins provides direct access to several order parameters, which we used to determine the lattice's magnetic phases as well as critical disorder and one of its universal exponents. By tuning the degree of disorder and effective transverse magnetic field, we observed phase transitions between a paramagnetic, an antiferromagnetic, and a spin-glass phase.

Quantum annealing (QA) is a heuristic algorithm for finding low-energy configurations of a system, with applications in optimization, machine learning, and quantum simulation. Up to now, all implementations of QA have been limited to qubits coupled via a single degree of freedom. This gives rise to a stoquastic Hamiltonian that has no sign problem in quantum Monte Carlo (QMC) simulations. In this paper, we report implementation and measurements of two superconducting flux qubits coupled via two canonically conjugate degrees of freedom (charge and flux) to achieve a nonstoquastic Hamiltonian. Such coupling can enhance performance of QA processors, extend the range of quantum simulations. We perform microwave spectroscopy to extract circuit parameters and show that the charge coupling manifests itself as a YY interaction in the computational basis. We observe destructive interference in quantum coherent oscillations between the computational basis states of the two-qubit system. Finally, we show that the extracted Hamiltonian is nonstoquastic over a wide range of parameters., Comment: 15 pages, 12 figures

The celebrated work of Berezinskii, Kosterlitz and Thouless in the 1970s revealed exotic phases of matter governed by topological properties of low-dimensional materials such as thin films of superfluids and superconductors. Key to this phenomenon is the appearance and interaction of vortices and antivortices in an angular degree of freedom---typified by the classical XY model---due to thermal fluctuations. In the 2D Ising model this angular degree of freedom is absent in the classical case, but with the addition of a transverse field it can emerge from the interplay between frustration and quantum fluctuations. Consequently a Kosterlitz-Thouless (KT) phase transition has been predicted in the quantum system by theory and simulation. Here we demonstrate a large-scale quantum simulation of this phenomenon in a network of 1,800 in situ programmable superconducting flux qubits arranged in a fully-frustrated square-octagonal lattice. Essential to the critical behavior, we observe the emergence of a complex order parameter with continuous rotational symmetry, and the onset of quasi-long-range order as the system approaches a critical temperature. We use a simple but previously undemonstrated approach to statistical estimation with an annealing-based quantum processor, performing Monte Carlo sampling in a chain of reverse quantum annealing protocols. Observations are consistent with classical simulations across a range of Hamiltonian parameters. We anticipate that our approach of using a quantum processor as a programmable magnetic lattice will find widespread use in the simulation and development of exotic materials., 17 pages, 15 figures

We have developed a quantum annealing processor, based on an array of tunable coupled rf-SQUID flux qubits, fabricated in a superconducting integrated circuit process. Implementing this type of processor at a scale of 512 qubits and 1472 programmable interqubit couplers and operating at ~ 20 mK has required attention to a number of considerations that one may ignore at the smaller scale of a few dozen or so devices. Here, we discuss some of these considerations, and the delicate balance necessary for the construction of a practical processor that respects the demanding physical requirements imposed by a quantum algorithm. In particular, we will review some of the design tradeoffs at play in the floor planning of the physical layout, driven by the desire to have an algorithmically useful set of interqubit couplers, and the simultaneous need to embed programmable control circuitry into the processor fabric. In this context, we have developed a new ultralow-power embedded superconducting digital-to-analog flux converter (DAC) used to program the processor with zero static power dissipation, optimized to achieve maximum flux storage density per unit area. The 512 single-stage, 3520 two-stage, and 512 three-stage flux DACs are controlled with an XYZ addressing scheme requiring 56 wires. Our estimate of on-chip dissipated energy for worst-case reprogramming of the whole processor is ~ 65 fJ. Several chips based on this architecture have been fabricated and operated successfully at our facility, as well as two outside facilities (see, for example, the recent reporting by Jones).

We have developed a low Jc (100-1000 A/cm2) submicrometer Nb integrated circuit fabrication process for SQUID-based quantum computing applications. The baseline process consists of 7 masking steps including Pd-Au resistor, Nb/Al-AlOx/Nb trilayer, two Nb wiring layers and two sputtered SiO2 dielectric layers. We have also fabricated wafers with an Nb ground plane. Using deep-UV lithography, inductively coupled plasma etch tools, and self-aligned lift-off for device definition, we routinely achieve micrometer lines and spaces with 400 nm minimum junction dimensions. Room temperature testing is used to select wafers in process and junction annealing has been calibrated for trimming current density. We will describe the process which has been used to produce circuits with over 100 junctions.

D-Wave's quantum processors require a high-fidelity readout architecture for fast and accurate operation. The need for cold operation precludes readout methods with significant dissipation. The readout architecture must be scalable and compatible with an inherently dense qubit circuit layout. Superconducting microresonators have been successfully utilized as detection elements for a wide variety of applications, enabling superior multiplexing factors. In existing designs, resonators undergo a non-uniform shift in frequency and sensitivity with fabrication imperfections, ultimately limiting effective bandwidth utilization. We overcome this drawback by implementing independent control of both frequency and sensitivity. We describe the design of the detector and report experimental results demonstrating its resilience to fabrication tolerances.

Single flux quantum (SFQ) electronics is extremely fast and has very low on-chip power dissipation. SFQ VLSI is an excellent candidate for high-performance computing and other applications requiring extremely high-speed signal processing. Despite this, SFQ technology has generally not been accepted for system implementation. We argue that this is due, at least in part, to the use of outdated tools to produce SFQ circuits and chips. Assuming the use of tools equivalent to those employed in the semiconductor industry, we estimate the density of Josephson junctions, circuit speed, and power dissipation that could be achieved with SFQ technology. Today, CMOS lithography is at 90?65?nm with about 20 layers. Assuming equivalent technology, aggressively increasing the current density above 100?kA?cm?2 to achieve junction speeds approximately 1000?GHz, and reducing device footprints by converting device profiles from planar to vertical, one could expect to integrate about 250?M Josephson junctions cm?2 into SFQ digital circuits. This should enable circuit operation with clock frequencies above 200?GHz and place approximately 20?K gates within a radius of one clock period. As a result, complete microprocessors, including integrated memory registers, could be fabricated on a single chip.

We describe a recent demonstration of a Multiply-Accumulate (MAC) unit, the core of digital signal processor that implements programmable band-pass signal filtering. This MAC unit can be clocked at 20 GHz and is capable of performing 2.5 billion MAC operations per second for 7-bit data samples and 16-bit filter coefficients arriving in bit-serial mode. The unit was designed using VHDL for functional verification and timing optimization and it was implemented in Northrop Grumman Space Technology's (NGST's) 8 kA/cm/sup 2/ J110E Niobium process. We also describe our design approach, which resulted in this successful demonstration, and discuss lessons learned, particularly the risks associated with fringe field magnetic coupling between bias and signal lines.

We describe recent demonstration of a superconductor oscillator/counter A/D Converter up through 12 GS/s with 3 effective bits of signal-to-noise ratio at that sample rate, along with analysis of its performance. Measurements are described for an A/D converter implemented in Northrop Grumman Space Technology's 4 kA/cm/sup 2/ J110D Niobium process. This A/D Converter incorporates a new technique for defining the aperture using inter-Josephson transmission line SFQ repulsion. This technique is described here.

This paper describes our programme to develop and demonstrate ultra-high performance single flux quantum (SFQ) VLSI technology that will enable superconducting digital processors for petaFLOPS-scale computing. In the hybrid technology, multi-threaded architecture, the computational engine to power a petaFLOPS machine at affordable power will consist of 4096 SFQ multi-chip processors, with 50 to 100 GHz clock frequency and associated cryogenic RAM. We present the superconducting technology requirements, progress to date and our plan to meet these requirements. We improved SFQ Nb VLSI by two generations, to a 8 kA cm−2, 1.25 µm junction process, incorporated new CAD tools into our methodology, demonstrated methods for recycling the bias current and data communication at speeds up to 60 Gb s−1, both on and between chips through passive transmission lines. FLUX-1 is the most ambitious project implemented in SFQ technology to date, a prototype general-purpose 8 bit microprocessor chip. We are testing the FLUX-1 chip (5K gates, 20 GHz clock) and designing a 32 bit floating-point SFQ multiplier with vector-register memory. We report correct operation of the complete stripline-connected gate library with large bias margins, as well as several larger functional units used in FLUX-1. The next stage will be an SFQ multi-processor machine. Important challenges include further reducing chip supply current and on-chip power dissipation, developing at least 64 kbit, sub-nanosecond cryogenic RAM chips, developing thermally and electrically efficient high data rate cryogenic-to-ambient input/output technology and improving Nb VLSI to increase gate density.

First-in, first-out (FIFO) buffers load and unload data using separate clocks that may be incoherent. We explore the application of FIFOs to circular shift registers, serial memory, and data re-clocking. We describe two different FIFO implementations in RSFQ. One employs classic handshaking using the Muller C-element. The other employs physical back-pressure based on repulsion of stored single flux quanta in a JTL. Both implementations use seven Josephson junctions, and a single bias resistor, per cell. The bias resistor can be reduced to an arbitrarily low value, thereby eliminating static power dissipation.

The Flux-1 chip is an RSFQ implementation of a small general-purpose processing engine with target clock frequency of 20 GHz and over 5000 gates (over 60 K Josephson junctions) connected in an irregular pattern. The scale of this design task forced us to re-think conventional RSFQ design methodology and implement new approaches suitable for digital systems of this level of complexity and beyond. This paper presents lessons learned from the Flux-1 effort, mostly concentrating on chip physical design. Here we discuss our approach to the circuit design and verification of individual gates, gate interconnect using passive transmission lines and use of CAD tools for design automation and verification.

This paper discusses the major challenges and solutions in designing high-performance superconductor processors in the context of the on-going collaboration between SUNY Stony Brook, TRW, and the JPL (NASA). It presents the architecture and organization of the first 8-bit FLUX-1 RSFQ microprocessor with a target clock frequency of 20 GHz fabricated in TRW's 4 kA/cm/sup 2/, 1.75-/spl mu/m Josephson junction technology in 2001-2002. A new parallel partitioned architecture has been developed for FLUX-1 in order to fill its long processing pipelines with operations, and reduce interconnect delays. The latest version of FLUX-1, called FLUX-1R, with improved circuit design characteristics and decreased power dissipation was fabricated in July 2002. FLUX-1R contains 63,107 Josephson junctions on a 10.35 mm /spl times/10.65 mm die with flip-chip packaging. The chip is currently under testing at TRW.

Entanglement lies at the core of quantum algorithms designed to solve problems that are intractable by classical approaches. One such algorithm, quantum annealing (QA), provides a promising path to a practical quantum processor. We have built a series of scalable QA processors consisting of networks of manufactured interacting spins (qubits). Here, we use qubit tunneling spectroscopy to measure the energy eigenspectrum of two- and eight-qubit systems within one such processor, demonstrating quantum coherence in these systems. We present experimental evidence that, during a critical portion of QA, the qubits become entangled and that entanglement persists even as these systems reach equilibrium with a thermal environment. Our results provide an encouraging sign that QA is a viable technology for large-scale quantum computing., Comment: 13 pages, 8 figures, contact corresponding author for Supplementary Information

Rapid Single Flux Quantum (RSFQ) logic is well-known for its ultra-high switching speed and extremely low power consumption. In this paper, we present two original experiments to demonstrate that it's also a reliable technology and its reliability is sufficient even for such a large-scale system as a proposed petaflops-scale HTMT computer. We have measured the bit error rate (BER) for a circular register of inverters representing a critical path of a 64-bit integer adder, and timing jitter in a 200 Josephson junction (JJ) long transmission line, imitating a branch of a clock distribution tree, both being important and representative building blocks of the HTMT computer. For the adder critical path we have demonstrated the highest clock frequency of 17 GHz, latency of 860 ps and BER of 10/sup -19/ for 3.5 /spl mu/m technology of HYPRES, Inc. The value of timing jitter was 200 fs per JJ for 1.5 /spl mu/m technology of TRW, Inc. These figures are in good agreement with our simulations.

We describe the design and implementation of a single-chip microprocessor based on LTS Rapid Single-Flux-Quantum (RSFQ) technology. Two such chips are to be used in a dual-processor module, being developed by a SUNY-TRW collaboration as a spin-off of the HTMT project. Each FLUX chip represents a simple 16-bit 2-way long-instruction-word (LIW) microprocessor with a pipelined instruction memory of 30-bit instructions, decode and issue units, 8 integer ALUs interlaced with 8 registers, and input/output ports through which two FLUX chips can communicate with each other at a 7-GHz communication rate over a multi-layer MCM. The FLUX instruction set consists of /spl sim/25 instructions. High performance is reached with a scalable design featuring (1) a very high clock rate, (2) localized, regular and ultrapipelined processing in registers with very short wires, (3) instruction-level parallelism utilization with bit-level resolution of data hazards. A 16-bit implementation of FLUX processor consists of /spl sim/90,000 Josephson junctions on a /spl sim/10 mm/spl times/15 mm chip area. Our estimates show that the processor will be able to operate at clock frequencies up to 20 GHz when implemented using TRW's 4 kA/cm/sup 2/, 1.75-/spl mu/m Nb-trilayer technology.

Rapid Single-Flux-Quantum (RSFQ) logic, based on the representation of digital bits by single quanta of magnetic flux in superconducting loops, may combine several-hundred-GHz speed with extremely low power dissipation (close to 10-18 Joule/bit) and very simple fabrication technology. The drawbacks of this technology include the necessity of deep (liquid-helium-level) cooling of RSFQ circuits and the rudimentary level of the currently available fabrication and testing facilities. The objective of this paper is to review RSFQ device physics and also discuss in brief the prospects of future development of this technology in the light of the tradeoff between its advantages and handicaps.

We present a design for parallel pipelined carry-lookahead Kogge-Stone 32and 64-bit integer adders with the traditional concurrent flow timing scheme, and the results of its gate-level logical simulation using a VHDL model, with parameters reduced from the physical-level simulation of RSFQ cells. The design uses only five different types of bit processing blocks and is easily scalable to any length of the operands. The multi-pulse logic representation together with interchanging logical polarity between pipeline stages is used to simplify the design of the blocks, which contain only two types of clocked RSFQ gates: an inverter and a D-flip-flop. Simulations show that in the absence of thermal fluctuations and random parameter spread the clock frequency of the adder implemented in the projected 0.8 /spl mu/m Nb-trilayer technology could be as high as 150 GHz. However, an approximate account of these factors shows that in order to achieve a 99% adder fabrication yield and a 10/sup -25/ adder error rate the maximal frequency should be reduced to 60 GHz for 1.5% Josephson junction spread and to 52 GHz for 3% spread. Adder latency is close to 260 ps for 32 bits and 320 ps for 64 bits. We plan to re-design the adders to increase their speed.

We discuss a preliminary design of a Rapid Single-Flux-Quantum (RSFQ) subsystem for general-purpose computers with petaflops-scale performance. The subsystem is being developed at Stony Brook within the framework of the Hybrid Technology MultiThreading (HTMT) project. COOL-0 design is based on 0.8-/spl mu/m RSFQ technology which enables the implementation of superconductor processing elements (SPELLs) operating at clock frequencies up to 100 GHz pipelined cryo-memory (CRAM) with 30 ps cycle time and interprocessor network (CNET) with a bandwidth of 30 Gbps per channel. The main architectural challenge is an almost 1,000-fold speed difference between the RSFQ processors and room-temperature SRAM comprising the second level of the HTMT memory hierarchy. The proposed solution to the problem is hardware support for two-level multithreading and block transfer techniques in SPELLs. Our preliminary estimates show that an RSFQ subsystem with 4 K SPELLs and a 4-Gbyte CRAM may be sufficient to achieve the performance close to 0.5 petaflops for computationally intensive program kernels. COOL-0 would occupy a physical space of about 0.5 m/sup 3/ and dissipate power as low as 250 Watts (at helium temperature). These numbers present a dramatic improvement compared to a hypothetical purely-semiconductor petaflops-scale computer.

We present a revised version of our previous RSFQ (Rapid Single Flux Quantum) microprocessor architecture and discuss approaches that we are using in the design of its functional units. In particular, the data processing pipeline built of D/sup 2/ cells, a 16-bit pipelined register block and an all-RSFQ self-reset decoder suitable for pipelined implementation are described in detail. Methods of VHDL description and verification of RSFQ circuitry are also discussed.

Efforts to develop useful quantum computers have been blocked primarily by environmental noise. Quantum annealing is a scheme of quantum computation that is predicted to be more robust against noise, because despite the thermal environment mixing the system's state in the energy basis, the system partially retains coherence in the computational basis, and hence is able to establish well-defined eigenstates. Here we examine the environment's effect on quantum annealing using 16 qubits of a superconducting quantum processor. For a problem instance with an isolated small-gap anticrossing between the lowest two energy levels, we experimentally demonstrate that, even with annealing times eight orders of magnitude longer than the predicted single-qubit decoherence time, the probabilities of performing a successful computation are similar to those expected for a fully coherent system. Moreover, for the problem studied, we show that quantum annealing can take advantage of a thermal environment to achieve a speedup factor of up to 1,000 over a closed system.

We are discussing a general-purpose microprocessor architecture that is suitable for implementation using the Rapid Single-Flux-Quantum (RSFQ) family of logic-memory circuits. While the microprocessor provides a functionally complete RISC instruction set with 16-bit words, a bit-serial self-timed approach makes it simple enough to be fabricated using the current Josephson junction technology. Our plans are to design, fabricate and test a completely operational prototype of this system. >

We describe a quantum tunneling spectroscopy technique that requires only low-bandwidth control. The method involves coupling a probe qubit to the system under study to create a localized probe state. The energy of the probe state is then scanned with respect to the unperturbed energy levels of the probed system. Incoherent tunneling transitions that flip the state of the probe qubit occur when the energy bias of the probe is close to an eigenenergy of the probed system. Monitoring these transitions allows the reconstruction of the probed system eigenspectrum. We demonstrate this method on an rf SQUID flux qubit.

We have developed a method for extracting the high-frequency noise spectral density of an rf-SQUID flux qubit from macroscopic resonant tunneling (MRT) rate measurements. The extracted noise spectral density is consistent with that of an ohmic environment up to frequencies $~$4 GHz. We have also derived an expression for the MRT line shape expected for a noise spectral density consisting of such a broadband ohmic component and an additional strongly peaked low-frequency component. This hybrid model provides an excellent fit to experimental data across a range of tunneling amplitudes and temperatures.

Several novel circuits of the rapid single-flux-quantum (RSFQ) family of Josephson-junction digital devices have been designed, fabricated using a 2.5- mu m 1000-A/cm/sup 2/ Nb trilayer technology, and tested at low frequencies. Numerical simulation and measurements have shown that these circuits have considerably wider parameter margins, due to application of several novel design methods. The authors have also carried out an experiment to measure the rate of errors in a simple RSFQ circuit including an inverter, confluence buffer, and Josephson transmission line. Near the middle of the parameter window at 4.2 K, the error probability was definitely lower than 3*10/sup -15/ per logic operation, despite experimentation with rudimentary shielding and filtering. >

Superconducting circuits have played an essential role in realizing quantum mechanical phenomena in macroscopic systems. One such example is the observation of macroscopic resonant tunneling (MRT) of magnetic flux between the lowest energy states of single rf-SQUID flux qubits, as demonstrated by several groups [1–4]. These measurements provide both a clear signature of quantum mechanics in a macroscopic circuit at a finite temperature and in the presence of noise and a direct means of determining the tunneling energy between states. Theoretical descriptions of the MRT rate have been presented [5, 6] and indicate a direct connection between the profile of the MRT rate peaks and properties of the environment. Analogous measurements of the tunneling of magnetization in nanomagnets [7, 8] suggest that MRT is responsible for dynamics in these materials as well. In this work, we extend measurements of MRT to inductively coupled pairs of flux qubits. We present experimental observations of tunneling between the two lowest energy states of the coupled system for several coupling strengths. These data yield two-qubit energy gaps that match those predicted by the independently calibrated Hamiltonian of the coupled system. Moreover, measurements of the two-qubit energy gap are used to infer sin

Many interesting but practically intractable problems can be reduced to that of finding the ground state of a system of interacting spins. It is believed that the ground state of some naturally occurring spin systems can be effectively attained through a process called quantum annealing. Johnson et al. use quantum annealing to find the ground state of an artificial Ising spin system comprised of an array of eight superconducting flux qubits with programmable spin–spin couplings. With an increased number of spins, the system may provide a practical physical means to implement quantum algorithms, possibly enabling more effective approaches towards solving certain classes of hard combinatorial optimization problems. Many interesting but practically intractable problems can be reduced to that of finding the ground state of a system of interacting spins; however, finding such a ground state remains computationally difficult1. It is believed that the ground state of some naturally occurring spin systems can be effectively attained through a process called quantum annealing2,3. If it could be harnessed, quantum annealing might improve on known methods for solving certain types of problem4,5. However, physical investigation of quantum annealing has been largely confined to microscopic spins in condensed-matter systems6,7,8,9,10,11,12. Here we use quantum annealing to find the ground state of an artificial Ising spin system comprising an array of eight superconducting flux quantum bits with programmable spin–spin couplings. We observe a clear signature of quantum annealing, distinguishable from classical thermal annealing through the temperature dependence of the time at which the system dynamics freezes. Our implementation can be configured in situ to realize a wide variety of different spin networks, each of which can be monitored as it moves towards a low-energy configuration13,14. This programmable artificial spin network bridges the gap between the theoretical study of ideal isolated spin networks and the experimental investigation of bulk magnetic samples. Moreover, with an increased number of spins, such a system may provide a practical physical means to implement a quantum algorithm, possibly allowing more-effective approaches to solving certain classes of hard combinatorial optimization problems.

Adiabatic quantum optimization offers a new method for solving hard optimization problems. In this paper we calculate median adiabatic times (in seconds) determined by the minimum gap during the adiabatic quantum optimization for an NP-hard Ising spin glass instance class with up to 128 binary variables. Using parameters obtained from a realistic superconducting adiabatic quantum processor, we extract the minimum gap and matrix elements using high performance Quantum Monte Carlo simulations on a large-scale Internet-based computing platform. We compare the median adiabatic times with the median running times of two classical solvers and find that, for the considered problem sizes, the adiabatic times for the simulated processor architecture are about 4 and 6 orders of magnitude shorter than the two classical solvers' times. This shows that if the adiabatic time scale were to determine the computation time, adiabatic quantum optimization would be significantly superior to those classical solvers for median spin glass problems of at least up to 128 qubits. We also discuss important additional constraints that affect the performance of a realistic system.

A novel rf-SQUID flux qubit that is robust against fabrication variations in Josephson junction critical currents and device inductance has been implemented. Measurements of the persistent current and of the tunneling energy between the two lowest lying states, both in the coherent and incoherent regime, are presented. These experimental results are shown to be in agreement with predictions of a quantum mechanical Hamiltonian whose parameters were independently calibrated, thus justifying the identification of this device as a flux qubit. In addition, measurements of the flux and critical current noise spectral densities are presented that indicate that these devices with Nb wiring are comparable to the best Al wiring rf-SQUIDs reported in the literature thusfar, with a $1/f$ flux noise spectral density at $1 $Hz of $1.3^{+0.7}_{-0.5} \mu\Phi_0/\sqrt{\text{Hz}}$. An explicit formula for converting the observed flux noise spectral density into a free induction decay time for a flux qubit biased to its optimal point and operated in the energy eigenbasis is presented., Comment: 20 pages, 16 figures

We report an experimental measurement of Landau-Zener transitions on an individual flux qubit within a multiqubit superconducting chip. The method used isolates a single qubit, tunes its tunneling amplitude $\ensuremath{\Delta}$ into the limit where $\ensuremath{\Delta}$ is much less than both the temperature $T$ and the decoherence-induced energy level broadening, and forces it to undergo a Landau-Zener transition. We find that the behavior of the qubit agrees to a high degree of accuracy with theoretical predictions for Landau-Zener transition probabilities for a double-well quantum system coupled to a nonMarkovian $1/f$ magnetic flux noise.

An improved tunable coupling element for building networks of coupled rf-SQUID flux qubits has been experimentally demonstrated. This new form of coupler, based upon the compound Josephson junction rf-SQUID, provides a sign and magnitude tunable mutual inductance between qubits with minimal nonlinear crosstalk from the coupler tuning parameter into the qubits. Quantitative agreement is shown between an effective one-dimensional model of the coupler's potential and measurements of the coupler persistent current and susceptibility., 5 pages, 5 figures. Updated text and Figure 4

We have designed, fabricated and operated a scalable system for applying independently programmable time-independent, and limited time-dependent flux biases to control superconducting devices in an integrated circuit. Here we report on the operation of a system designed to supply 64 flux biases to devices in a circuit designed to be a unit cell for a superconducting adiabatic quantum optimization system. The system requires six digital address lines, two power lines, and a handful of global analog lines., Comment: 14 pages, 15 figures

We have designed, fabricated and tested an XY-addressable readout system that is specifically tailored for the reading of superconducting flux qubits in an integrated circuit that could enable adiabatic quantum optimization. In such a system, the flux qubits only need to be read at the end of an adiabatic evolution when quantum mechanical tunneling has been suppressed, thus simplifying many aspects of the readout process. The readout architecture for an $N$-qubit adiabatic quantum optimization system comprises $N$ hysteretic dc SQUIDs and $N$ rf SQUID latches controlled by $2\sqrt{N} + 2$ bias lines. The latching elements are coupled to the qubits and the dc SQUIDs are then coupled to the latching elements. This readout scheme provides two key advantages: First, the latching elements provide exceptional flux sensitivity that significantly exceeds what may be achieved by directly coupling the flux qubits to the dc SQUIDs using a practical mutual inductance. Second, the states of the latching elements are robust against the influence of ac currents generated by the switching of the hysteretic dc SQUIDs, thus allowing one to interrogate the latching elements repeatedly so as to mitigate the effects of stochastic switching of the dc SQUIDs. We demonstrate that it is possible to achieve single qubit read error rates of $, Updated for clarity, final version

A general method for directly measuring the low-frequency flux noise (below 10 Hz) in compound Josephson junction superconducting flux qubits has been used to study a series of 85 devices of varying design. The variation in flux noise across sets of qubits with identical designs was observed to be small. However, the levels of flux noise systematically varied between qubit designs with strong dependence upon qubit wiring length and wiring width. Furthermore, qubits fabricated above a superconducting ground plane yielded lower noise than qubits without such a layer. These results support the hypothesis that localized magnetic impurities in the vicinity of the qubit wiring are a key source of low frequency flux noise in superconducting devices., Comment: 5 pages, 5 figures

Superconducting microresonators have been successfully utilized as detection elements for a wide variety of applications. With multiplexing factors exceeding 1,000 detectors per transmission line, they are the most scalable low-temperature detector technology demonstrated to date. For high-throughput applications, fewer detectors can be coupled to a single wire but utilize a larger per-detector bandwidth. For all existing designs, fluctuations in fabrication tolerances result in a non-uniform shift in resonance frequency and sensitivity, which ultimately limits the efficiency of band-width utilization. Here we present the design, implementation, and initial characterization of a superconducting microresonator readout integrating two tunable inductances per detector. We demonstrate that these tuning elements provide independent control of both the detector frequency and sensitivity, allowing us to maximize the transmission line bandwidth utilization. Finally we discuss the integration of these detectors in a multilayer fabrication stack for high-speed readout of the D-Wave quantum processor, highlighting the use of control and routing circuitry composed of single flux-quantum loops to minimize the number of control wires at the lowest temperature stage., 8 pages, 9 figures

Macroscopic resonant tunneling between the two lowest lying states of a bistable RF-SQUID is used to characterize noise in a flux qubit. Measurements of the incoherent decay rate as a function of flux bias revealed a Gaussian shaped profile that is not peaked at the resonance point, but is shifted to a bias at which the initial well is higher than the target well. The r.m.s. amplitude of the noise, which is proportional to the decoherence rate 1/T_2^*, was observed to be weakly dependent on temperature below 70 mK. Analysis of these results indicates that the dominant source of low frequency (1/f) flux noise in this device is a quantum mechanical environment in thermal equilibrium., 4 pages 4 figures

We experimentally confirm the functionality of a coupling element for flux-based superconducting qubits, with a coupling strength $J$ whose sign and magnitude can be tuned {\it in situ}. To measure the effective $J$, the groundstate of a coupled two-qubit system has been mapped as a function of the local magnetic fields applied to each qubit. The state of the system is determined by directly reading out the individual qubits while tunneling is suppressed. These measurements demonstrate that $J$ can be tuned from antiferromagnetic through zero to ferromagnetic., Updated text and figures

A simple test circuit of the rapid single‐flux‐quantum (RSFQ) logic family has been implemented in a planarized all‐refractory technology using only two superconducting layers and small Nb/AlOx/Nb Josephson junctions (nominally 1.5×1.5 μm2) with critical current density jc≊6 kA/cm2. A special layout design of the integrated circuit (including a SFQ pulse generator, Josephson transmission line, and T flip–flop) was used to reduce 3D inductances resulting from absence of the ground plane. For samples with various junction parameters, the maximum frequency of the SFQ pulse train, which could be divided by 2 by the flip–flop, ranged from 200 to 370 GHz.

The goal of the present effort is the further development of ultrafast "Rapid Single-Flux-Quantum"(RSFQ) devices and circuits based on the storage, transfer, and processing of digital bits encoded by single quanta of magnetic flux. This approach offers several key advantages over other possible digital superconductor technologies, most importantly an extremely high operation speed and extremely low power consumption.

In this paper we describe a simple and efficient ray casting engine that is suitable for the rapid exploration of irregular grids composed of tetrahedra cells, or other cell complexes where cells have been broken up into faces. In our method, in a preprocessing phase, all the cells are broken into their corresponding faces. Visibility determination is performed after all the faces have been transformed into screen space; here we compute for each pixel an ordered list of the stabbing boundary faces. The final phase is the actual ray casting, which is performed independently for each pixel, and is basically a walk in the cell complex inside each component of the stabbing ordered list. For color calculations, a simple analytical lighting model is applied to each intersection of ray and cell. Our algorithm is simple, and our implementation fast and robust.

Post-layout automatic analysis of Flux-1 microprocessor, a representative random logic RSFQ chip of more than 5000 gate complexity, allowed us to extract important layout parameters such as gate density, Josephson junction density and gate/wiring/unused area ratios. A scaling model is presented to predict the area required to layout a given number of random logic gates. When applied to Flux-1 chip itself, which occupies 88.6 mm/sup 2/ in the current TRWs 4 kA/cm/sup 2/ J110D technology, this model predicts that it can be shrunk by almost a factor of two in area to 49 mm/sup 2/ if moved to a next-generation J110E technology with 8 kA/cm/sup 2/ junctions. This information enables us to confidently floorplan random logic chips to be implemented in future advanced JJ technologies. It can also provide directions for JJ technology improvements leading to the maximum positive impact on RSFQ chip density.

Recent progress in the design of a superconductor digital system for high-performance computing, based on the RSFQ logic family, is briefly outlined.

A practical strategy for synchronizing the properties of compound Josephson junction rf-SQUID qubits on a multiqubit chip has been demonstrated. The impacts of small ($\sim1%$) fabrication variations in qubit inductance and critical current can be minimized by the application of a custom tuned flux offset to the CJJ structure of each qubit. This strategy allows for simultaneous synchronization of the qubit persistent current and tunnel splitting over a range of external bias parameters that is relevant for the implementation of an adiabatic quantum processor.