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This article belongs to the Special Issue MOCAST 2021; International audience; In this paper, we present a thorough analysis of parasitic coupling effects between different electrodes for a 3D Sequential Integration circuit example comprising stacked devices. More specifically, this study is performed for a BackSide Illuminated, 4T-APS, 3D Sequential Integration pixel with both its photodiode and Transfer Gate at the bottom tier and the other parts of the circuit on the top tier. The effects of voltage bias and 3D inter-tier contacts are studied by using TCAD simulations. Coupling-induced electrical parameter variations are compared against variations due to temperature change, revealing that these two effects can cause similar levels of readout error for the top-tier readout circuit. On the bright side, we also demonstrate that in the case of a rolling shutter pixel readout, the coupling effect becomes nearly negligible. Therefore, we estimate that the presence of an inter-tier ground plane, normally used for electrical isolation, is not strictly mandatory for Monolithic 3D pixels.

Effects of additional thermal budget associated with a three-dimensional (3D) fabrication sequence are evaluated for the total-ionizing dose radiation response of fully depleted silicon-on-insulator (FD-SOI) MOSFETs. Current-voltage and low-frequency (1/ ${f}$ ) noise measurements are compared for (1) conventional planar FD-SOI MOSFETs, and (2) MOSFETs formed in the bottom layer of the 3D process and subjected to the process steps associated with formation of a second active layer. Similar radiation-induced voltage shifts and increases of 1/ ${f}$ noise are observed after irradiation for both types of structures. These similar changes in response show that the additional thermal processing involved with 3D fabrication has little effect on border-trap densities and radiation-induced charge trapping in gate and/or buried oxides of MOSFETs formed in the bottom layer of the 3D process.

The aim of this paper is to present the 3D-sequential integration and its main prospective application sectors. The presentation will also give a synoptic view of all the key enabling process steps required to build high performance Si CMOS integrated by 3D-sequential with thermal budget preserving the integrity of active devices and interconnects and will sketch a status and prospect on current low temperature device performance.

This study investigates the inter-tier coupling, for a Back-Side Illuminated (BSI) 4-Transistor (4T) pixel with its diode and Transfer Gate on the bottom tier and the rest of its circuitry on the top tier of a 3D Sequential Integration (3DSI) process. Variations due to coupling are compared with variations due to temperature, showing that both effects may result in a readout error of the same order of magnitude for the top-tier readout circuit. Nevertheless, we demonstrate that in a typical rolling readout, the sequence of the pixel control signals makes the coupling effect nearly negligible. As a result, we suggest that the fabrication of an inter-tier ground plane for electrical isolation is not strictly necessary for Monolithic 3D pixels when the readout top tier is directly stacked on the photodiode bottom tier.

RF performance and intertier coupling of CMOS processed in 3-D sequential integration are investigated. pMOS transistor fabricated with a 500 °C thermal budget features good RF figures of merit with ${f}_{t} =105$ GHz and ${f}_{\text {max}} =175$ GHz for a gate length of 45 nm and ${V}_{\text {DD}} = -1$ V. Moreover, we demonstrate that the low- ${k}$ SiCO oxide spacer and low polysilicon gate resistance obtained with the low temperature process contribute to ${f}_{\text {max}}$ results that are better than high temperature process (above 1000°). Finally, we illustrate the crosstalk effects and the influence of the low-tier transistor gate voltage ${V}_{\text {G}}$ on the top-tier threshold voltage ${V}_{T}$ . We also show that a polysilicon ground shield integrated under the top-tier transistor substantially attenuates the intertier RF field coupling effects.

We fabricated junction less and inversion-mode monocrystalline nanowire nMOSFETs down to L=18nm gate length and W=20nm width. We demonstrate record performance of nanowire junction less transistors for analog applications: $A_{VT}=1.4mV \cdot \mu$ m matching, $A_{v0}=62dB$ gain (L=200nm), $f_{T}=126GHz$ cut-off frequency and $f_{MAX}=182GHz$ maximum operating frequency (L=35nm). Junction Less transistor performances even exceed those of inversion-mode ones in terms of back-bias capability, low-frequency noise, hotcarrier degradation and fMAX. This is explained by junction less physics: channel length modulation, bulk conduction and high channel-depth sensitivity to back bias.

International audience; This work presents statistical measurements on the effects of the electrostatic coupling on the on-current, off-current and low frequency noise characteristics of individual top-tier devices, due to bottom-tier devices being biased. No inter-tier coupling impact was observed on device low-frequency noise regardless the transistor area. While for analog applications the coupling-induced ΔVt, ΔIoff and ΔIon might reach high values, it is demonstrated that regarding digital applications, the coupling-induced fluctuations are well below the mismatch effects. TCAD and SPICE simulations were used to fully understand the phenomenon, to predict the effects at SRAM bitcell level and to propose guidelines to contain the inter-tier electrostatic coupling: the coupling effect can be limited either by increasing the Inter-Layer Dielectric (ILD) thickness or through a top/bottom transistor misalignment.

International audience; Monolithic 3D (M3D) stands now as the ultimate technology to side step Moore's Law stagnation. Due to its nanoscale Monolithic Inter-tier Via (MIV), M3D enables an ultrahigh density interconnect between Logic and Memory that is required in the field of highly energy efficient 3D integrated circuits (3D-ICs) designed for new abundant data computing systems. At design level, M3D still suffers from a lack of commercial tools, especially for Place and Route, precluding the capability to provide signoff M3D GDS. In this paper, we introduce M3D-ADTCO, an architecture, design and technology co-optimization platform aimed at providing signoff M3D GDS. It relies on a M3D Process Design Kit and the use of a commercial Place and Route tool. We demonstrate an area reduction of 23.61 % at iso performance and power compared to a 2D RISC-V micro-controller based System on Chip (SoC) while creating space to increase (2x) the RISC-V instruction memory.

To take fully advantage of Junctionless transistor (JLT) low-cost and low-temperature features we investigate a 475 degC process to create onto a wafer a thin poly-Si layer on insulator. We fabricated a 13nm doped (Phosphorous, 1E19 at/cm3) poly-silicon film featuring excellent roughness values (Rmax= 1.6nm and RMS=0.2nm). Guidelines for grain size optimization using nanosecond (ns) laser annealing are given.

International audience; For the first time, an in-depth analysis of the intertier dynamic coupling and RF crosstalk of digital circuits in 3D sequential integration enables to conclude on the need of a Ground Plane (GP) for various applications. Experiments in conjunction with TCAD simulations reveal the parasitic capacitances responsible for the dynamic coupling effects and their impact is investigated for a 3D sequential 2-bitcell SRAM cell circuit configuration. Furthermore, we show a greater than 20dB suppression up to 100GHz of the inter-tier RF crosstalk, achieved by the addition of a strategically designed polysilicon Ground Plane between active device layers enabling the possibility of heterogeneous 3DSI integration without metallic Ground Plane. We propose a technological solution to create experimentally a 34nm-thick polysilicon GP of 1.8x10 20 at/cm 3 n-doping and 295Ω/sq sheet resistance.

3D sequential integration motivates the development of low temperature technological modules. Alternatively to classical non-selective annealing techniques, sub-microsecond laser annealing allows high temperature treatment of a sub-micrometer surface region while keeping the underneath structures at much lower temperature. In this contribution, we present recent advances in ultra-violet nanosecond laser annealing targeting monolithic 3D integration. Emphasis will be put on the demonstration of dopant activation in thin implanted SOI structures, simulating source and drain regions. Cu / ULK interconnects stability upon nanosecond laser annealing is also investigated.

3D sequential integration, such as CoolCubeź, allows to stack vertically layer of devices. Levels of interconnection, also called intermediate Back-End-Of-Line, are needed between successive layers of transistors to avoid routing congestion. Thus, thermal stability of the dielectrics must be studied in order to fulfil the CoolCubeź requirement: at least to be stable up to 500°C during 2h. Consequently, the stability of several barrier layers and oxide based materials has been studied through optical characterizations (ellipsometry, Fourier Transform InfraRed spectroscopy and ellipsometric-porosimetry). SiCO (k=4.5), in replacement of standard SiCNH (k=5.6) material as barrier layer seems very promising. Regarding the inter-layer dielectric stability, the state-of-the-art porous SiOCH (k=2.5) stays suitable for a thermal budget of 500°C, 2h. Display Omitted

International audience; We fabricated and characterized 14nm planar Fully-Depleted-Silicon-On-Insulator (FDSOI) 0.078µm² Static Random Access Memory (SRAM) cells. Temporal and spatial variability as well as sensibility to temperature, supply voltage (VDD) and back bias (Vwell) are extracted. These data evidence that the 14nm SRAM is read-limited, which could be improved by a smart back-bias management [1]. In this work we demonstrate a 50mV Static Noise Margin (SNM) variability improvement (at VDD=0.8V) by back-biasing, without additional Bias Temperature Instability (BTI) stress. Such an assist technique can be eventually leveraged at fine-grain by 3D monolithic integration, owing to local back-planes.

For the first time, we propose a 3D-monolithic SRAM architecture with a local back-plane for top-tier transistors enabling local back-bias assist techniques without area penalty as well as the capability to route two additional row-wise signals on individual back-planes. Experimental data are extracted from a 14nm planar Fully-Depleted-Silicon-on-Insulator (FDSOI) $0.078\mu \mathrm{m}^{2}$ SRAM in order to properly model 3D top-tier cells. Simulations show this technique yields a 7% bitline capacitance reduction, a 12%/16% read/write access time improvement at $V_{DD}=0.8\mathrm{V}$ and a reduction of minimum operating voltage $V_{min}$ by 60mV at $6\sigma$ w.r.t. planar SRAMs.

International audience; This work presents for the first time an analytical study of the electrostatic coupling between bottom and top layer of 3D sequential integration devices, regarding its impact on both static and noise behavior. The effect is demonstrated experimentally through statistical measurements, and TCAD simulations are used to further examine its properties and propose ways for the limitation of inter-tier coupling. It is demonstrated that regarding digital applications, the coupling-induced fluctuations are well within the mismatch variation level.

Image Sensors will get more and more pervasive into their environment. In the context of Automotive and IoT, low cost image sensors, with high quality pixels, will embed more and more smart functions, such as the regular low level image processing but also object recognition, movement detection, light detection, etc. 3D technology is a key enabler technology to integrate into a single device the pixel layer and associated acquisition layer, but also the smart computing features and the required amount of memory to process all the acquired data. More computing and memory within the 3D Smart Image Sensors will bring new features and reduce the overall system power consumption. Advanced 3D technology with ultra-fine pitch vertical interconnect density will pave the way towards new architectures for 3D Smart Image Sensors, allowing local vertical communication between pixels, and the associated computing and memory structures. The presentation will give an overview of recent 3D technologies solutions, such as Hybrid Bonding technology and the Monolithic 3D CoolCube™ technology, with respective 3D interconnect pitch in the order of 1 μm and l00nm. Recent 3D Image Sensors will be presented, showing the capability of 3D technology to implement fine grain pixel acquisition and processing with ultra-high speed image acquisition and tile-based processing. As further perspectives, multi-layer 3D image sensor based on events and spiking will reduce power consumption with new detection and learning processing capabilities.

This paper highlights the last technological breakthroughs achieved in the development of low temperature process modules at 500°C for 3D sequential integration. The two remaining process steps (low temperature gate stack and selective silicon raised source drain epitaxy) that were considered as potential showstoppers for this technology have shown decisive progress very recently.

International audience; Variability is a challenge for future scaling as process dimensions reduce. The emerging 3-D sequential stacking technology is more than Moore’s scaling alternative. The 3-D design flow requires the partitioning of the netlist between the tiers. This paper presents the variability analysis of circuits partitioned into different levels. A comparison among local and global variations effects on ring oscillators (ROs) and SRAM is demonstrated. The across-chip variations and correlation range are shown as a critical point for the 3-D very large-scale integrated circuits, where the local variability is dominant. The correlations between devices due to the distances or the allocation into different tiers are directly taken into account in the SPICE model due to a statically unified model applied to 3-D circuits based on Monte Carlo simulations. Design wise, the 3-D integration can further decrease the circuit variability as shown in RO output frequency and SRAM static noise margin.

session 3: Characterization technqiues and reliability assessment techniques; International audience

session T8: Transistor; International audience; For the first time, we propose a 3D-monolithic SRAM architecture with a local back-plane for top-tier transistors enabling local back-bias assist techniques without area penalty as well as the capability to route two additional row-wise signals on individual back-planes. Experimental data are extracted from a 14nm planar Fully-Depleted-Silicon-on-Insulator (FDSOI) 0.078µm 2 SRAM in order to properly model 3D top-tier cells. Simulations show this technique yields a 7% bitline capacitance reduction, a 12%/16% read/write access time improvement at VDD=0.8V and a reduction of minimum operating voltage Vmin by 60mV at 6w.r.t. planar SRAMs.

Monolithic 3D technology (M3D) is a promising alternative to takle the loss of Moore's Law scaling beyond 22 nm node. By stacking different circuit layers thanks to nano-scale 3D Monolithic Inter Tier Via (MIV), it will be possible to offer a level of circuit integration never reached before, allowing advanced node scaling again as well as mixing heterogeneous technologies. M3D integrates sequentially different layers of transistors, with an ultra-fine pitch, in the 100 nm range, which is 200x smaller than state-of-the-art Through Silicon Vias (TSV) or 50x smaller than Copper to Copper Hybrid bonding (Cu-Cu HB). This high density 3D integration will pave the way towards new architectures, such as neuro- and bio-inspired applications, ultra-high density computing cube and smarter mixed signal devices within low power constraints. This paper presents an overview of M3D technology and potential applications, and in more detail its associated design challenges, respectively on physical implementation aspects and on thermal dissipation.

3D sequential integration is a promising alternative to conventional scaling down approach: by stacking transistors level on top of each other, benefits on device density and performance are achieved. However, although the thermal processing of top transistors is currently restricted in order to avoid bottom CMOS degradation, it has been highlighted that Ni0.80Pt0.10 silicide source/drain (S&D) contact remains the most sensitive element to the thermal budget, especially on raised Si0.7Ge0.3:B S&D for pMOS transistors. In this context, a complete and systematic study on self-aligned silicide (SALICIDE) process has been proposed: alternative metallization as well as source and drain surface pre-treatments have been carried out. Indeed, a novel Ni-based silicide, the Ni0.9Co0.1 provides a better stability on unpatterned 300 mm wafers. This stability has been further improved when combined with epitaxial silicon capping layer (Si-Cap) and Si0.7Ge0.3:B S&D pre-amorphization implant (PAI) using Ge beam. For the first time, a successful Ni0.9Co0.1 SALICIDE implementation has been demonstrated on pMOS planar FDSOI transistor with both PAI and Si-Cap. Moreover, the presence of Si-Cap contributes to reduce silicide roughness and limits Ge partition that damage Si0.7Ge0.3:B S&D. (© 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)