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A circuit point of view is used for designing a high-performance negative differential resistance (NDR) element and describing a possible compact device implementation. A single-NDR element static-random-access-memory cell prototype with a compact size and high speed is described as an interesting application suitable for embedded memory.

A simple analytical model is described for surrounding gate metal-oxide semiconductor field-effect transistors (MOSFETs) with bulk traps. The model has predicted a linear threshold voltage drop that depends on the trap density because the diameter of the device decreases when the channel is fully depleted.

The charge trapping at the interface between the two dielectric layers of a high-k gate stack caused by Maxwell-Wagner instability is analyzed. The analysis shows that uniform dielectrics do not display Maxwell-Wagner instability and perfect crystals do not display dielectric relaxation, thus making the ideal high-k gate dielectric a uniform single-layer perfect crystal bonded epitaxially to the Si substrate.

The effect of a second Flash anneal at higher peak temperatures is studied. The end-of-range defects normalized out while causing minimal diffusion and deactivation of boron.

The experimental results obtained with various prototypes of impact ionization (I-MOS) transistors are described for verifying the basic concept and further understanding the device physics. These first experimental prototypes of the I-MOS showed significant hot carrier effects resulting in threshold voltage shifts and degradation of subthreshold slope with repeated measurements.

A novel transistor based on the field-effect control of impact-ionization (I-MOS) is explored through detailed device and circuit simulations. It was found that the I-MOS has the potential to replace CMOS in high performance and low power digital applications.

Lateral doping abruptness in the source/drain extension regions is an important parameter that has major impact on source/drain resistance. The potential improvement in device performance should be carefully weighed against the cost of increasing lateral abruptness.

Studies of boron, arsenic and phosphorus electrical activation after implant and annealing are presented. The activation mechanism of arsenic and phosphorus is different than boron. The relationship between ramp rates and activation and diffusion is investigated.

An additional means for tailoring current-voltage (I-V) characteristics by controlling physical effects inside the device is provided through the use of silicon germanium (SiGe) heterostructures in vertical surrounding-gate MOSFETs. Incorporation of an SiGe layer in the vertical MOSFET drain can modify hot-carrier characteristics via material dependent impact ionization coefficients.

An additional means for tailoring current-voltage (I-V) characteristics by controlling physical effects inside the device is provided through the use of silicon germanium (SiGe) heterostructures in vertical surrounding-gate MOSFETs. Incorporation of an SiGe layer in the vertical MOSFET source can delay the floating-body effect by changing the back injection efficiency and current gain of parasitic bipolar junction transistor (BJT).

Grain boundary migration effects on hillock formation in AI thin films is examined.

The structural and electrical properties of thin polycrystalline silicon films at the level of individual grains are linked together. The results demonstrate the distribution of grain structures and orientation by fundamentally determining the electrical properties of the blanket film.

A new study investigates the characteristics of arsenic dose loss at the silicon/silicon dioxide interface.

An identical class of thermal oxidation and nitridation experiments were conducted for four common dopants and self-diffusion in Si. Bounds on the fractional contributions of self-interstitial, vacancy, and concerted exchange mechanisms were obtained for arsenic, boron, phosphorus, antimony and self-diffusion in Si at temperatures of 1100 and 1000 degrees C. These bounds were obtained by simultaneously solving a system of equations making only very conservative assumptions.

Silicon-on-insulator (SOI) substrates provide true dielectric isolation (DI) for power devices. Previous SOI power device studies have been limited to thick SOI layers, but there have been recent reports of PIN diodes and LDMOS devices in ultra-thin SOI substrates. The turn-off time of an LIGBT can be reduced by reducing the thickness of the SOI layer.

A new test chip design environment, based on commercial tools, containing a test structure advisor and a coupled, library-based layout and testing environment has been developed that dramatically increases productivity. The test structure advisor analyzes cross sections of devices to recommend a comprehensive list of diagnostic and parametric test structures. These test structures can then be retrieved from the libraries of parameterized structures, customized, and placed in a design to rapidly generate customized test chips. Coupling of the layout and test environments enables the automatic generation of the vast majority of the parametric test software. This environment, which has been used to design test chips for a low-power/low-voltage CMOS process, a BiCMOS trench process, and a TFT process, results in an estimated tenfold increase in productivity. In addition, the redesign of five modules of Stanford's existing BiCMOS test chip, using parameterized test structures, showed an 8 x improvement in layout time alone.

The importance of employing a finite applied bias slew rate as opposed to instantaneous switching to better approximate experimental electronic device conditions is illustrated. This results into more accurate transient Wigner function simulations. The application of instantaneous switching is shown to have substantial effect on simulation results and lead to incorrect conclusions about device operation.

The electrical deactivation of arsenic due to low temperature anneals increases the diffusion of dopants in bipolar devices. The diffusion increases in the arsenic and in the adjacent boron layers at an annealing temperature of 750 degree celsius. The secondary ion mass spectroscopy analysis and simulation confirms the increase in diffusion during relatively low temperature backend line processing. Low temperature thermal cycles have significant effects on bipolar devices.

A three-dimensional programmable erasable nonvolatile cylindrical (PENCIL) flash EPROM cell has small size, high read current, inherent bit line isolation, optimum doping profile, low bit line capacitance, simple array structure and metal bit lines. An algorithmic approach reduces the erase threshold voltage distribution to a great extent. Gate oxide quality determines the window closure. The cells are programmable even after 30,000 cycles.

Polysilicon (poly-Si) thin film transistors (TFTs) hydrogenation by ion implantation and gas anneal shows radical improvement in performance and reduction in avalanche induced kink effect. NMOS poly-Si TFTs manufactured using a low temperature process show good mobility, threshold voltage, subthreshold swing and OFF-state leakage current at V(sub DS) of 10 volts.

Experimental studies suggest that the random distribution of channel dopant ions is the major source for surface potential fluctuations in metal oxide semiconductor devices. These fluctuations lead to a stretch-out of capacitance-voltage characteristics. A model assuming a lateral variation of threshold voltage over the region of the device with a normal distribution accurately predicts nonideal characteristics. A three-dimensional model based on the method of images helps predict the standard deviation of the threshold voltage. At higher doping levels, other sources are minor contributors to surface potential fluctuations.

A one-dimensional physical model for parasitic lateral bipolar transistor gain in a full depleted n-channel silicon on insulator (SOI) MOSFET is constructed and shown to be feasible by experiments. The transistor gain is inversely proportional to hole concentration and is influenced by SOI layer thickness, gate and drain voltages and doping concentration. Gummel plots of the bipolar reveal a 0.5 ideality factor for the hole current.

A new PIN-diode-based pixel detector, combining a VLSI readout circuit and a two-dimensional sequence of detecting elements on the same silicon medium, is developed. All signal charges are grouped into a designated low capacitance collection electrode to minimize spatial resolution and pixel pitch. A signal to single-channel-noise ratio is evaluated without signal charge loss from the collection electrode.

Aconductivity-modulated metal oxide semiconductor field effect transistor is introduced for high power operation. The device, known as a CD-double-diffusion-MOS, (DMOS) strikes a balance between the forward conduction performance and the gate switching speed. It has an ON-resistance below that of a conventional DMOS and a switching speed beyond that aof an insulated gate bipolar transistor. A derived model of the device's ON-resistance is also discussed.

Experiments were conducted on the design, fabrication and performance of the GexSi1-x/silicon inversion-base transistor (BICFET). The unipolar and bipolar properties of the device were examined. A material analysis of the device wafers exhibited good structural agreement with the target profile. BICFET was found to possess excellent device characteristics. The only limitation of the device is the current fabrication technology used in its development.

A theoretical study was conducted on the properties of the GexSi1-x/silicon inversion-base transistor (BICFET). BICFET uses the space charge of holes in an inversion channel to control vertical electron transport. BICFET outperforms heterojunction bipolar transistors at low temperatures due to the high hole mobility of modulation-doped electron transport. However, modifications have to be made on BICFET's sensitivity to the profile and location of its p+-dopant spike.

A proposed solid-state switching element can accommodate very large current densities with minimal forward voltage drop in its on-state. The Field-Assisted Turn-off thyristor can be switched off with a voltage applied to a high-impedance and insulated-gate terminal as compared to other regenerative devices which cannot be switched off using a control signal. An insulated-gated turn-on design allows full switching control by low signals.

A silicon process simulator SUPREM-IV was used to model uphill diffusion on implanted magneisum in gallium arsenic during a 900 degree centigrade anneal. The diffusion occurs through the substitution-interstitial-diffusion process. The implantation process produces the abnormal diffusion behavior using excess interstitials and vacancies obtained from Boltzmann transport equation calculations.