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In this paper, we examine whether the presence of a mechanistic structure (i.e. formalization) hinders or facilitates employee thriving at work. In doing so, we examine formalization as an antecedent of employee thriving at work. Specifically, we examine why and when formalization, as an important contextual factor, may facilitate employee thriving at work. We hypothesize that the positive relation between formalization and employees' thriving at work is mediated by their interpersonal justice perceptions. Furthermore, we hypothesize that ethical leadership moderates the indirect relationship between formalization and employee thriving at work via interpersonal justice. As such, this relationship is stronger in the presence of relatively high (rather than relatively low) levels of ethical leadership. Results from a two‐wave field study provide support for our hypotheses. We also discuss the theoretical and practical implications, limitations, and future research directions for our findings. [ABSTRACT FROM AUTHOR]

Graphene-based devices have initiated unprecedented breakthrough in nanoelectronics. Due to its intrinsic ultrathin 2-D nature, the unique structural, mechanical, electronic, optical, and magnetic properties of graphene are found to be extremely dependent on its substrate material. For the synthesis of graphene with pretailored features or fabrication of graphene-based device with tunable functionality, understanding of the graphene interfaces with other materials are of pivotal importance. Density-functional theory (DFT) computations have been proved to be a powerful tool in investigating the interface properties of graphene-crystalline solids and to subsequently correlate the experimental findings with underlying mechanisms, as well as to explore their potential applications. This paper presents a comprehensive review on utility of DFT-based analysis for graphene interfaces/heterostructures with other crystalline solid materials including metals, semiconductors, and insulators. DFT computational efforts to choose the appropriate material for substrate catalyst, probe, and electrode in graphene synthesis/graphene-based nanodevice design have been critically reviewed including the investigation of different combination of complex interfaces as well as unconventional materials. Salient features, advantages, and constraints of the approach have also been summarized. [ABSTRACT FROM AUTHOR]

Crosstalk induced overshoot/undershoot effects in multilayer graphene nano ribbon interconnects (MLGNRs) are investigated with the help of ABCD parameter matrix approach for intermediate level interconnects at both 11 nm and 8 nm technology node. The worst case crosstalk induced peak overshoot voltage for perfectly specular, doped multilayer zigzag GNR interconnects is comparable to that of copper interconnects. The performance of neutral GNR interconnects is better than that of its doped counterpart with respect to peak crosstalk overshoot. But from the perspective of overall overshoot width and overshoot area contribution, perfectly specular, doped MLGNR interconnects outperform all other alternatives. As far as the effective electric field across the gate oxide is concerned, the doped MLGNR interconnects outperform neutral ones and copper interconnects for all the cases. It is estimated that the doped perfectly specular multilayer GNR interconnects have gate oxide failure rates ( AFR ) of ~ 240 × and ~ 790 × lesser than copper interconnects for 11 nm and 8 nm technology node respectively. So, from the gate oxide reliability perspective, perfectly specular, doped multilayer zigzag GNR interconnects are great advantageous to copper interconnects for the future integrated circuit technology generations. [ABSTRACT FROM AUTHOR]

The purpose of this study was to investigate how Facebook use is leading to negative relationship outcomes such as cheating and breakup by assessing users' perceived relationship qualities. It was hypothesized that Facebook-related conflict will be negatively related with users' relationship length and will also be negatively related with their perceived relationship satisfaction, commitment, and love. Facebook-related conflict further mediates the relationship between relationship length and perceived relationship satisfaction, commitment, and love. Self-report data were gathered from participants (N = 101) in an online survey by employing standard questionnaires. A set of regression and mediation analyses confirmed all the hypotheses of the study. That is, Facebook-related conflict mediates the relationship between relationship length and perceived relationship satisfaction, commitment, and love. Moreover, the magnitude of mediation was highest for relationship satisfaction. Implications for future research and contributions are discussed. [ABSTRACT FROM AUTHOR]

Direct current (dc) microhollow cathode discharge (MHCD) is an intense source for excimer radiation in vacuum ultraviolet at a wavelength of 172 nm in a high pressure xenon (Xe) gas. The concentration of precursors for the excimer formation, i.e., excited and ionized gas atoms, increases significantly by applying high voltage pulse onto the dc MHCD over the pulse duration range from 20 to 100 ns. The intensity of the excimer emission for the voltage pulse of 20 ns duration exceeds that of the emission intensity obtained from the same MHCD operated only in the dc mode, by one order of magnitude. In addition, the emission intensity increases by one order of magnitude over the pulse duration range from 20 to 100 ns. It can be assumed that the emission intensity of the MHCD source increases as long as the duration of the high voltage pulse is shorter than the electron relaxation time. For the high voltage pulse of 100 ns duration, the emission intensity has been found to be further enhanced by a factor of three when the gas pressure is increased from 200 to 800 mbar. [ABSTRACT FROM AUTHOR]

Performance-driven routing tree construction has immense research scope in today's VLSI circuit design. In this study, the authors focuss on delay efficient routing tree construction. Our current work encompasses two aspects of research. On the one hand, the authors consider the construction of cost-effective global routing trees with the recently introduced Y-interconnects, and on the other hand, we utilise this framework for verifying the supremacy of the two-pole and Elmore delay estimate for its high fidelity. The authors also incorporated fidelity measure for two-pole delay estimate. In order to ensure accurate computation of fidelity, (i) the authors propose new statistically proven formulae for the fidelity metric, and (ii) compute the fidelity values based on delay estimates for optimal and near-optimal trees. Our experiments on several randomly generated problem instances and benchmarks confirm once again the supremacy of fidelity of two-pole and Elmore delay estimates over that of linear delay. The two-pole delay estimate is also observed to exhibit higher fidelity compared to Elmore delay in most of the cases. [ABSTRACT FROM AUTHOR]

It is our interest to design and develop a high-power pulser system employing an electrical discharge in a spark gap. The type of discharge generates short electric pulses capable of both the characteristics of a fast rise time and a high repetition rate. Such a switch pulser has wide applications in the industry. To generate the electrical discharge in the spark gap in an efficient manner is very important for the switching operation. The regime of the operation utilizes the residual plasma in the interpulse recovery of the spark gap to increase the repetition rate. Therefore, the mechanisms of the discharge in a controlled manner following the electrical breakdown of the spark gap, such as the plasma generation in the spark channel and the dielectric recovery process as well as the residual plasma in the post-spark-discharge period, are of great importance. The understanding of the type of the spark-gap discharge for the switching at a high repetition rate beyond 1 MHz has been the primary goal. The typical voltage and current ratings are below 1 kV and several amperes, respectively. In particular, this paper addresses the optimal set of several parameters, such as the spark-gap geometry, electrode gap distance, gas pressure, and gas type, in conjunction with a unique circuit scheme to drive the discharge in the controlled fashion. [ABSTRACT FROM PUBLISHER]

It is our endeavor to develop switching technology for the breakdown reliability and reproducibility at extremely high voltages above 1 MV. One of the key objectives of the endeavor is to derive precise breakdown criteria for use in high-voltage applications. We have developed empirical criteria by which the breakdown field strength of a high-pressure \SF6-filled spark gap can be computed. The validity of the computed result has been verified with several experimental data from different investigators. The computed result has shown good agreement in an extended range of pd (pressure times gap distance) and field enhancement factor of the spark gap geometry. Furthermore, a spark gap has been designed and constructed with particular intention of generating a high-pulsed-power source in Pohang Accelerator Laboratory. In parallel, field modeling has been performed to verify the appropriate shape of the highly stressed insulator and electrode design in the spark gap and to evaluate their field enhancements. A series of breakdown voltage tests has demonstrated the function of the spark gap switch as intended up to 9 bars of \SF6. Aside from this, the limitation of the switching behavior has been examined with an aim of operating the designed spark gap to its maximum capability. [ABSTRACT FROM PUBLISHER]

This study presents a simplified structure of bit parallel systolic multiplier over Galois fields (GFs) over the set GF(2m) suitable for cryptographic hardware implementation. A redundant standard basis representation with the irreducible all one polynomial is considered. The systolic multiplier consists of (m+1)2 identical cells, each consisting of one two-input AND gate, one two-input XOR gate and two one-bit latches. This architecture is well suited to very large-scale integration implementation because of its regularity modular structure and unidirectional data flow. The proposed multipliers have clock cycle latency of (m+1). This architecture has a total reduction of m2 D-flip-flops compared to earlier bit parallel systolic multiplication architecture. As the finite-field multiplier is one of the complex blocks in cryptographic hardware and need secure testability to avoid unwanted access into the on-chip security blocks, the authors also introduce an on-chip testing scheme. The authors propose a test generation technique for detecting stuck-at fault (SAF), transition delay fault (TDF), stuck-open fault (SOF) and path delay faults (PDFs) at the gate and cell level in the systolic architecture. The authors also show that realistic sequential cell fault can be detected only by 12 single input change test vectors in the complete systolic multiplier over GF(2m). The proposed technique derives test vectors from the cell expressions of systolic multipliers without any requirement of an automatic test pattern generation tool. The complete systolic architecture is C-testable for SAF, TDF, SOF and PDF with only 12 constant tests. The test vectors are independent of the multiplier size. The test set provides 100% single SAF, TDF, SOF and PDF coverage. [ABSTRACT FROM AUTHOR]

It has been recently shown that observability of design for testability techniques compromises cryptographic hardware implementation security in a straightforward manner. During test, the chip can be configured so that it is possible to observe temporal data resulting from the encryption process of a plaintext that eventually exposes the secret key. To this end, we propose a C-testable S-box implementation which is one of the most complex blocks in advanced encryption standard hardware implementation. We divide the S-box structure into a positive polarity Reed–Muller form and tested independently using a BIST circuit. The proposed structure does not use any scan chain for testability, hence avoiding the vulnerability of the chip during testing. Only 14 constant vectors are sufficient to achieve 100% fault coverage in the S-box. The C-testable feature comes with an extra hardware overhead of 15 per cent. By introducing an on-chip testing feature one can avoid potential paths for introducing unwanted access into the on-chip security blocks. [ABSTRACT FROM PUBLISHER]

It is difficult to predict or measure the breakdown strength of SF6 gas in the high pressure range. Therefore, it is hard to find reference data of the high pressure SF6 gas breakdown strength. This paper attempts to provide empirically a novel criterion for the estimation of SF6 gas breakdown strength in a spark gap switch. For this purpose, J.C. Martin's breakdown field strength of non-uniform gap in air and Kuffel et al's breakdown field strength by exploiting streamer criterion of uniform field in SF6 gas are adopted. The research is made for the empirical method of predicting the high pressure SF6 breakdown strength and compared results have been ascertained with several experimental data from different investigators in a wide range of pd (pressure times distance) and field enhancement factor (FEF). For further confirmation of the empirical approach, we have designed and developed a high pressure spark gap switch to be closely coupled to a high voltage PFN-Marx system. The designed spark gap switch operates above 1 MV. Our tests have verified the prediction of the breakdown strength of the SF6 filled spark gap switch in a pd range of 0.27-1.62 MPa . cm (2.7 to 16.2 bar.cm). [ABSTRACT FROM AUTHOR]

It is difficult to predict or measure the breakdown strength of SF6 gas in the high pressure range. Therefore, it is hard to find reference data of the high pressure SF6 gas breakdown strength. This paper attempts to provide empirically a novel criterion for the estimation of SF6 gas breakdown strength in a spark gap switch. For this purpose, J.C. Martin's breakdown field strength of non-uniform gap in air and Kuffel et al's breakdown field strength by exploiting streamer criterion of uniform field in SF6 gas are adopted. The research is made for the empirical method of predicting the high pressure SF6 breakdown strength and compared results have been ascertained with several experimental data from different investigators in a wide range of pd (pressure times distance) and field enhancement factor (FEF). For further confirmation of the empirical approach, we have designed and developed a high pressure spark gap switch to be closely coupled to a high voltage PFN-Marx system. The designed spark gap switch operates above 1 MV. Our tests have verified the prediction of the breakdown strength of the SF6 filled spark gap switch in a pd range of 0.27-1.62 MPa . cm (2.7 to 16.2 bar.cm). [ABSTRACT FROM AUTHOR]

This paper presents an algebraic testing method for detecting stuck-at faults in the polynomial-basis (PB) bit-parallel (BP) multiplier circuits over GF(2m). The proposed technique derives the test vectors from the expressions of the inner product (IP) variables without any requirement of the ATPG tool. This low- complexity testing method requires (2m + 1) test vectors for detecting single stuck-at faults in the AND part and multiple stuck-at faults in the EXOR part of the multiplier circuits. The test vectors are independent of the multiplier's structure, as proposed in (11), but are dependent on m. For the multiplier circuits, the test set is found to be smaller in size than the ATPG-generated test set. The test set provides 100 percent single stuck-at fault coverage. [ABSTRACT FROM AUTHOR]

3-Allyl-4-hydroxy-coumarins and pyrones were regioselectively cyclized with N-bromosuccinimide (NBS) on solid phase under microwave irradiation in excellent yield. NBS on montmorillonite K-10 clay under microwave irradiation for expeditious solvent-free regioselective cyclization has been used for the first time. [ABSTRACT FROM AUTHOR]

Synthesis of a number of hitherto unreported 4-aryloxymethylene-7-methyl-2,3-dihydropyrano[3,2-c]pyridine-5-ones 4a–h have been achieved in moderate yields by the thermal [3,3]sigmatropic rearrangement of 4-(4'-aryloxybut-2'-ynyloxy)-6-methyl-2-pyridone. [ABSTRACT FROM AUTHOR]

A testable design for detecting stuck-at and bridging faults in programmable logic arrays (PLAs) based on double fixed-polarity Reed–Muller (DFPRM) expression is presented. DFPRM expression has the advantage of compactness and easy testability. The EXOR part in the proposed structure is designed as a tree of depth (⌈log2s⌉+1), where s is the number of product terms and sum terms in the given DFPRM expression realised by PLAs. This solves an open problem of designing an EXOR-tree-based RMC network that admits a universal test set. For an n-variable function, a test sequence of length (2n+8) vectors is sufficient to detect all single stuck-at and bridging faults in the proposed design. The proposed EXOR-tree-based network reduces circuit delay significantly compared with cascaded EXOR-based design. The test sequence is independent of the function and the circuit-under-test, and the test set can be stored in a ROM for built-in-self-test. [ABSTRACT FROM AUTHOR]

Testable designs of GRM (generalised Reed-Muller) and ESOP (EXOR sum-of-products) circuits have been proposed for robustly detecting all single stuck-open faults in their CMOS implementation. It is shown that for an n-variable boolean function, a sequence of (4n + 13) vectors is sufficient to detect all single stuck-open faults in a GRM circuit. For an ESOP circuit, a test sequence of length (2n + 10) is sufficient. In the first case, the EXOR part is designed as a tree of depth ≤ 2(log [p + 1]), and for the latter, as a linear cascade of length ≤ (p + 1), where p is the number of product terms in the GRM or ESOP expression. For both the cases the test sequence is universal, i.e. independent of the function and the circuit under test, and can be stored in a ROM for built-in self-test. [ABSTRACT FROM AUTHOR]

In Bangladesh prevalence of kidney diseases is increasing day by day and it was observed that renal medulla is affected less in earlier period of life but in late period it becomes affected more. Moreover renal mass changes with age which affecting the medullary mass and consequently the number of medullary pyramids. So the present study was carried out to evaluate anatomical features of medulla and to count the medullary pyramids with age related changes in the number of the pyramids in Bangladeshi people. Study type: Cross sectional analytical type of study. Place and period of study: Department of Anatomy, Mymensingh Medical College, Mymensingh, Bangladesh from January 2004 to June 2005. Materials and methods: A total of 70 fresh human kidneys of both sexes and sides were collected from the morgue of Mymensingh Medical College at postmortem. The selected cases were between 5 to 60 years of age. The samples were divided into 3 different age groups (A: 05-15 years, B: 16-35 years, C: 36- 60 years) to observe the variations in number of medullary pyramid of kidney in different age groups. Results: Among three groups, highly significant (<0.001) differences were found statistically in the number of medullary pyramid. Conclusion: There were changes in the number of medullary pyramid of kidney in different age groups. [ABSTRACT FROM AUTHOR]

We present an analysis of annual and seasonal mean characteristics of the Indian Ocean circulation and water masses from 16 global ocean–sea-ice model simulations that follow the Coordinated Ocean-ice Reference Experiments (CORE) interannual protocol (CORE-II). All simulations show a similar large-scale tropical current system, but with differences in the Equatorial Undercurrent. Most CORE-II models simulate the structure of the Cross Equatorial Cell (CEC) in the Indian Ocean. We uncover a previously unidentified secondary pathway of northward cross-equatorial transport along 75 °E, thus complementing the pathway near the Somali Coast. This secondary pathway is most prominent in the models which represent topography realistically, thus suggesting a need for realistic bathymetry in climate models. When probing the water mass structure in the upper ocean, we find that the salinity profiles are closer to observations in geopotential (level) models than in isopycnal models. More generally, we find that biases are model dependent, thus suggesting a grouping into model lineage, formulation of the surface boundary, vertical coordinate and surface salinity restoring. Refinement in model horizontal resolution (one degree versus 1 4 degree) does not significantly improve simulations, though there are some marginal improvements in the salinity and barrier layer results. The results in turn suggest that a focus on improving physical parameterizations (e.g. boundary layer processes) may offer more near-term advances in Indian Ocean simulations than refined grid resolution. • Assessment of the Indian Ocean simulation from global forced sea- ice models. • SST biases are ∼ 2 times smaller in forced simulations than the coupled simulations. • Coupled model shows large inter-model spread over the eastern equatorial Indian Ocean. • Refinement in model horizontal resolution does not significantly improve simulations. • Uncover a secondary pathway of northward cross-equatorial transport along 75 °E. • Models are unable to capture the observed thick barrier layer in the north Bay of Bengal. [ABSTRACT FROM AUTHOR]

Abstract: A novel procedure for the synthesis of substituted 1,8-naphthyridinones via tandem Claisen rearrangement and ring-closing enyne metathesis is reported. [Copyright &y& Elsevier]

Oscillation-based test algorithm has been proposed and verified experimentally as an alternative to the specification--based test of analog circuits. Active filters are transformed to oscillators using nonlinear feedback, realized with a Schmitt trigger. Faults are detected based on the deviation of the oscillation frequency outside the tolerance band due to the variation of different circuit components under test. This proposed technique ensures high test precision due to the processing of the oscillation frequency with the help of a purely digital circuit. Undetectable ranges of parametric faults of circuit components have been identified by simulation with Cadence virtuoso using the 0.18 µm CMOS technology. Then, practical circuits of second order Butterworth Low Pass Filter and Sallen-Key Band Pass Filter have been tested experimentally. Experimental results ensure high fault coverage of the proposed test strategy. [ABSTRACT FROM AUTHOR]

Abstract: Thirty-one shiga toxin-producing (STEC) and 6 enteropathogenic Escherichia coli (EPEC) were isolated from 87 raw yak milk and 63 ‘churpi’ samples. Of 18 stx 1 positive isolates (48.6%), 14 carried stx 1c (77.7%). Subtyping of 28 stx2 positive isolates (75.7%) revealed the presence of stx2c (9, 32.1%), stx2d (3, 10.7%), stx2e (1, 3.57%) and stx2f (3, 10.7%) variants. Furthermore, intimin (eaeA), enterohaemolysin (ehxA), autoagglutinating adhesin (saa), iha (adherence conferring protein), efa1 (EHEC factor for adherence), bundle forming pilli (bfpA) and toxB (type III secreted protein encoded on LEE Island, similar to toxin B of Clostridium difficile) genes were detected in 14, 16, 12, 4, 3, 2 and 2 isolates, respectively. Univariate and multivariate analysis depicted that both stx1 and stx2 or their variants were more likely to occur in isolates from Arunachal Pradesh (p <0.04) rather than Sikkim. Dendogram constructed on the basis of RAPD and ERIC PCR profile distributed the STEC and EPEC isolates in separate clusters irrespective of their sources and serotypes. The STEC and EPEC isolates exhibited resistance against erythromycin, amikacin, azithromycin, amoxicillin, ampicillin+cloxacillin, cephalothin, furazolidone, gentamicin, kanamycin, streptomycin and tetracycline. This is the first ever report on occurrence and characterization of STEC and EPEC isolated from yak milk and milk products. [Copyright &y& Elsevier]

In this paper, we present a systematic method for designing single error correcting (SEC) and double error detecting finite field (Galois field) multipliers over GF(2m). The detection and correction are done on-line. We use multiple Parity Predictions to detect and correct errors. Specifically, a structural approach is first presented. The predicted parity bits are derived from the primitive polynomials for generating the fields. Further, a hybrid approach is presented where the multipliers and PP circuits are synthesised, and the decoding and correction circuits are structurally combined to form the complete error correcting designs. Although the article considers only a finite field multiplier, without loss of generality, the technique could be applied to any combinational logic circuit. Our technique, when compared with existing techniques, gives better performance. We show that our SEC multipliers over GF(2m) require about 100% extra hardware, whereas with the traditional SEC techniques, such as the triple-modular redundancy (TMR), this figure is more than 200%. Moreover, the multiple bit error detection and correction using multiple Hamming code were also introduced. [ABSTRACT FROM AUTHOR]

Motivated by the problems associated with soft errors in digital circuits and fault-related attacks in cryptographic hardware, a systematic method for designing single error correcting multiplier circuits is presented for finite fields or Galois fields over GF(2m). Multiple parity predictions to correct single errors based on the Hamming principles are used. The expressions for the parity prediction are derived from the input operands, and are based on the primitive polynomials of the fields. This technique, when compared with existing ones, gives better performance. It is shown that single error correction (SEC) multipliers over GF(2m) require slightly over 100% extra hardware, whereas with the traditional SEC techniques, this figure is more than 200%. Since single bit internal faults can cause multiple faults in the outputs, this has also been addressed here by using multiple Hamming codes with optimised hardware. [ABSTRACT FROM AUTHOR]

We investigate the effect of stacking order of bilayer black phosphorene on the device properties of p-MOSFET and n-MOSFET. Two layers of black phosphorus are stacked in three different orders and are used as channel material in both n-MOSFET and p-MOSFET devices. The effects of different stacking orders on electron and hole effective masses and output characteristics of MOSFETs, such as ON currents, ON/OFF ratio, and transconductance are analyzed. Our results show that about 1.37 times and 1.49 times increase in ON current is possible along armchair and zigzag directions, respectively, 55.11% variation in transconductance is possible along armchair direction, by changing stacking orders (AA, AB, and AC) and about 8 times increase in ON current is achievable by changing channel orientation (armchair or zigzag) in p-MOSFET. About 14.8 mV/V drain induced barrier lowering is observed for both p-MOSFET and n-MOSFET, which signifies good immunity to short channel effects. [ABSTRACT FROM AUTHOR]

A modular double gap pseudospark discharge based switch has been recently designed and developed for various pulsed power applications. The modular pseudospark geometry has two gaps that are separated by a cavity drift space region. It employs a single trigger unit in the cathode region to initiate discharge for the rapid breakdown of both the gaps. Successful experiments for the double gap pseudospark with typical coaxial arrangement of multichannel discharges were performed. The peak discharge currents at breakdown voltage of about 40 kV were 5 and 10 kA through resistive loads of 5.25 and 2.7 Ω, respectively. The design of the double gap pseudospark along with switching results is presented in this paper. [ABSTRACT FROM AUTHOR]

In this paper, a high current linear aperture radial multichannel Pseudospark switch (LARM-PSS) is reported which has been analyzed for its high current characteristics. In order to enhance hold-off voltage and support hollow cathode effect for the ignition of the discharge in this configuration, the field penetration analysis through circular and linear apertures of the electrodes has been carried out. The linear apertures in the electrodes increase the current handling capacity than that of circular aperture electrodes without significant compromise of the hold-off capacity. The developed LARM-PSS switch is capable to hold voltage up to 25 kV at gas pressure between 10 and 50 Pa for hydrogen. The switch has been operated using a 800 nF capacitor bank and conducted an effective charge up to 1.5 C with peak switch current ~20 kA at applied voltage 19 kV [ABSTRACT FROM AUTHOR]

n optimal implementation of 128-Pt FFT/IFFT for low power IEEE 802.15.3a WPAN using pseudo-parallel datapath structure is presented, where the 128-Pt FFT is devolved into 8-Pt and 16-Pt FFTs and then once again by devolving the 16-Pt FFT into 4×4 and 2×8. We analyze 128-Pt FFT/IFFT architecture for various pseudo-parallel 8-Pt and 16-Pt FFTs and an optimum datapath architecture is explored. It is suggested that there exists an optimum degree of parallelism for the given algorithm. The analysis demonstrated that with a modest increase in area one can achieve significant reduction in power. The proposed architectures complete one parallel-to-parallel (i.e., when all input data are available in parallel and all output data are generated in parallel) 128-point FFT computation in less than 312.5 ns and thereby meet the standard specification. The relative merits and demerits of these architectures have been analyzed from the algorithm as well as implementation point of view. Detailed power analysis of each of the architectures with a different number of data paths at block level is described. We found that from power perspective the architecture with eight datapaths is optimum. The core power consumption with optimum case is 60.6 MW which is only less than half of the latest reported 128-point FFT design in 0.18u technology. Furthermore, a Single Event Upset (SEU) tolerant scheme for registers is also explored. The SEU tolerant scheme will not affect the performance, however, there is an increase power consumption of about 42 percent. Apart from the low power consumption, the advantages of the proposed architectures include reduced hardware complexity, regular data flow and simple counter based control. [ABSTRACT FROM AUTHOR]

In deep-submicron very-large-scale integration (VLSI) systems, efficient circuit testability is one of the most demanding requirements. An automatic synthesis technique for designing efficiently testable logic circuits is one of the ways to tackle the problem. To this end, this study introduces the generalised theory and a new fast efficient graph-based decomposition technique for the functions over finite fields defined over the set GF(N), where N is a power of a prime number, which utilises the data structure of the multiple-output decision diagrams. In particular, the proposed technique can decompose any N valued arbitrary function over the fields conjunctively and disjunctively. The proposed technique is capable of generating testable circuits. The experimental results show that the proposed method is more economical in terms of literal count compared to the existing approaches. Furthermore, the authors have shown that the basic block can be tested with only eight test vectors. [ABSTRACT FROM AUTHOR]