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In this work, we study the charge carrier transport and electroluminescence (EL) in thin-film polycrystalline (poly-) GaN/c-Si heterojunction diodes realized using a plasma enhanced atomic layer deposition process. The fabricated poly-GaN/p-Si diode with a native oxide at the interface showed a rectifying behavior (Ion/Ioff ratio ∼ 103 at ±3 V) with current-voltage characteristics reaching an ideality factor n of ∼5.17. The areal (Ja) and peripheral (Jp) components of the current density were extracted, and their temperature dependencies were studied. The space charge limited current (SCLC) in the presence of traps is identified as the dominant carrier transport mechanism for Ja in forward bias. An effective trap density of 4.6 × 1017/cm3 at a trap energy level of 0.13 eV below the GaN conduction band minimum was estimated by analyzing Ja. Other basic electrical properties of the material such as the free carrier concentration, effective density of states in the conduction band, electron mobility, and dielectric relaxation time were also determined from the current-voltage analysis in the SCLC regime. Further, infrared EL corresponding to the Si bandgap was observed from the fabricated diodes. The observed EL intensity from the GaN/p-Si heterojunction diode is ∼3 orders of magnitude higher as compared to the conventional Si only counterpart. The enhanced infrared light emission is attributed to the improved injector efficiency of the GaN/Si diode because of the wide bandgap of the poly-GaN layer and the resulting band discontinuity at the GaN/Si interface. [ABSTRACT FROM AUTHOR]

A novel approach is described for making high-performance CMOS at low temperatures. CMOS inverters and fully functional 51-stage ring oscillators are fabricated in this process and this process is used for large-area TFT electronics as well as a functional stack layer in 3-D integration.

An existing RF voltage generation technique is used to study the degradation of deep-submicrometer MOS transistors under RF stress. The technique permits to assess the RF CMOS reliability for a variety of degradation modes via use of one basic set of instruments and devices.

Radio frequency (RF) micro-electro-mechanical systems (MEMS) capacitive switches show great promise for use in wireless communication devices such as mobile phones, but for the successful application of these switches their reliability needs to be demonstrated. One of the main factors that limits the reliability is charge injection in the dielectric layer (SIN) which can cause irreversible stiction of the moving part of the switch. We present a way to characterize charge injection. By stressing the dielectric with electric fields on the order of I MV/cm, we inject charge in the dielectric and measure the effects it has on the CV curve. Instead of conventionally measuring the change of the pull-in voltage, the presented center shift method measures the change of the voltage at which the capacitance is minimal. This way, the measurement method does not influence the charge injected by the stress voltage. Another advantage is that the measurement of the amount of injected charge is not influenced by changes in the width of the CV curve. These two advantages make it possible to test RF.MEMS capacitive switches in a more accurate way. Index Terms--Capacitive switch, charging, dielectric, radio (RF) micro-electro-mechanical systems (MEMS), reliability.

The radiofrequency (RF) charge-pumping (CP) technique is used to obtain CP curves accurately on devices that show a leakage current density far too high for use in conventional CP measurements. The analysis of the trap response to RF gate voltage signals has provided insights on the benefits and limitations of this technique.

The impact of dislocation loops on the infrared light emission from silicon light-emitting diodes (LEDs) is examined. Results suggest a strong variation in the density and physical location of implantation-originated dislocation loops observed in the resulting diodes.

We present an MOS capacitance-voltage measurement methodology that, contrary to present methods, is highly robust against gate leakage current densities up to 1000 A/[cm.sup.2]. The methodology features specially designed RF test structures and RF measurement frequencies. It allows MOS parameter extraction in the full range of accumulation, depletion, and inversion. Index Terms--Capacitance-voltage (C-V), characterization, CMOS, direct tunneling, gate leakage, RF.

This work presents the modeling of light emission from silicon based p+n junctions operating in avalanche breakdown. We revisit the photon emission process under the influence of relatively high electric fields in a reverse biased junction (>105 V/cm). The photon emission rate is described as a function of the electron temperature Te, which is computed from the spatial distribution of the electric field. The light emission spectra lie around the visible spectral range (λ ~ 300-850 nm), where the peak wavelength and the optical intensity are both doping level dependent. It is theoretically derived that a specific minimum geometrical width (~170 nm) of the active region of avalanche is required, corresponding to a breakdown voltage of ~5V, below which the rate of photon emission in the desired spectrum drops. The derived model is validated using experimental data obtained from ultra-shallow p+n junctions with low absorption through a nm-thin p+ region and surface coverage of solely 3 nm of pure boron. We observe a peak in the emission spectra near 580 nm and 650 nm for diodes with breakdown voltages 7V and 14 V, respectively, consistent with our model. [ABSTRACT FROM AUTHOR]