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Electron-beam lithography and reactive ion etching were used to process silicon-on-insulator substrates for the fabrication of single cylindrical high-aspect-ratio solid-state nanopores and high-packing-density nanopore arrays. Minimum pore diameters of 40 nm were readily achieved with a high yield. The electrolyte concentration dependence of ion transport through single nanopores was measured for pores with diameters ranging from 40 to 140 nm. Measured single-nanopore conductances in high salt concentrations were compared to a simple model using a cylindrical resistance path and bulk solution conductivity. Electrochemical impedance spectroscopy was used to study the ac response of the device. [2007-0090] Index Terms--Coulter counting, ion channel, nanopore, nanoporous array, patch damp, silicon-on-insulator (SOI).

The experiments demonstrate that the p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) fabricated on silicon-on-insulator (SOI) substrates exhibit a lower magnitude of the 1/f noise, which is studied as a function of the back gate voltage. The results show that the 1/f noise is highly affected by the channel positioning of silicon and increases with an increase in the back gate voltage that push the carriers towards the front gate oxide interface.

The depletion-all-around (DAA) operation of the silicon-on-insulator (SOI) four-gate transistor ([G.sup.4]-FET) is presented by using experimental characteristics, three-dimensional (3-D) simulations and analytical modeling. The results have shown that the DAA operation of the SOI [G.sup.4]-FET is very useful for high-performance low-noise radiation-hard analog circuits.

An engineering model of the valence-band electron (EVB) tunneling current is presented based on surface-potential formulation, which is implemented in a silicon-on-insulator (SOI) metal-oxide semiconductor field effect transistor (MOSFET) compact model and used to analyze the impact of EVB tunneling on circuit performance. The results have shown that the EVB tunneling current not only increases circuit switching speed but also mitigates the history dependence of propagation delays.

The bias scheme of the variable body-factor fully depleted (FD) silicon-on-insulator (SOI) metal-oxide semiconductor field effect transistor (MOSFET) reexamined and a new type bias scheme of variable-[gamma] is proposed. The new scheme is found to be useful for back-bias scheme and also for transistors under high-speed operation with a very thin buried-oxide (BOX).

This paper reports an electrostatic microelectromechanical systems (MEMS) gripper with an integrated capacitive force sensor. The sensitivity is more than three orders of magnitude higher than other monolithically fabricated MEMS grippers with force feedback. This force sensing resolution provides feedback in the range of the forces that dominate the micromanipulation process. A MEMS ultrasonic device is described for aligning microobjects suspended in water using ultrasonic fields. The alignment of the particles is of a sufficient accuracy that the microgripper must only return to a fixed position in order to pick up particles less than 100 [micro]m in diameter. The concept is also demonstrated with HeLa cells, thus providing a useful tool in biological research and cell assays. Index Terms--Capacitive force sensor, electrostatic microgripper, force feedback, handling biological cells, HeLa cancer cells, microelectromechanical systems (MEMS), micromanipulation, silicon-on-insulator (SOI) fabrication, ultrasonic positioning.

A low-power phase-shift keying demodulator integrated circuit (IC) has been implemented using silicon-on-insulator CMOS technology for deep space and satellite applications. The demodulator employs double differential detection to increase its robustness to the Doppler shift caused by the movement of the space vehicle and sampling technique with 1-bit analog-to-digital converter (ADC) at the front to reduce the complexity and power dissipation. In particular, digital decimation is used after sampling to achieve a low power implementation of multirate transmission. Operating at ultra-high-frequency (435 MHz), the receiver system supports a wide range of data rates (0.1-100 Kbps). From test results, the power consumption of the demodulator circuit including the 1-bit ADC is below 1 mW for data rates up to 100 Kbps. Index Terms--Differential detection, multirate, phase-shift keying (PSK), sampling, space communications, symbol timing circuit.

A 128-Mb silicon-on-insulator dynamic random access memory with floating-body cell (FBC) was developed for the first time by implementing two technologies, the optimized well structure and Cu wiring. Scalability of FBC down to 45-nm CMOS technology node investigated by device simulation showed that the signal and the maximum electric field could be maintained constant with the reduction of the device dimensions and the operation voltage.

Novel uniaxially strained SiGe-on-insulator (SGOI) pMOSFETs with Ge content of 20% is successfully fabricated by utilizing lateral strain-relaxation process on globally strained SGOI substrates. Drastic increase of drain current (80%) caused by the change of strain from biaxial to uniaxial and the mobility enhancement of about 100% against the control Si-on-insulator pMOSFETs are observed in SGOI pMOSFET.

The thickness effects of a high-tensile-stress contact etch stop layer (HS CESL) and the impact of layout geometry on the mobility enhancement of /(100) 90-nm silicon-on-insulator (SOI) n-channel MOSFETs (nMOSFETs) is studied. Experimental results reveal that a device with a 1100-angstrom HS CESL has worse characteristics and hot-carrier-induced degradations than a device with a 700-angstrom HS CESL due to larger stress-induced defects.

A quantitative evaluation of the intrinsic reliability limits of floating-gate (FG) memories in the decananometer range due to the reduction of collective phenomena and to the dominance of single-electron stochastic behaviors is presented. A model that predicts the intrinsic dispersions of the memory retention time and programming window is proposed, and the experimental results obtained on ultrasound memory devices are used to validate this model.

A novel negative differential resistance (NDR) device known as bistable gated bipolar (BGB) device, is investigated, and experimental demonstration for both n-channel and p-channel devices is carried out in a partially depleted silicon-on-insulator technology. A feasible scheme is proposed to implement this device in scaled CMOS technologies, and potential applications for logic and memory are also discussed.

Mobility and threshold-voltage (V[sub th]) in (100) and (110) in ultrathin-body (UTB) nMOFSETs and pMOFSETs are experimentally examined, and performance is compared between (110) and (100) UTB CMOSFETs based on the estimated propagation delay time. Out-of-plane effective mass (m[sub x]) is the key parameter that causes the difference in mobility and threshold-voltage behavior between (110) and (100).

The two-dimensional (2-D) channel potential and threshold voltage of the silicon-on-insulator (SOI) four-gate transistor are modeled, by assuming a parabolic potential variation between the lateral junction-gates and by solving Poisson's equation. The potential model is used to derive analytical expressions for the front threshold voltage of the four-gate transistor for all possible steady-state charge conditions at the back interface.

An analysis of the gate-source/drain capacitance behavior of a narrow-channel fully depleted (FD) silicon-on-insulator (SOI) NMOS device is reported, considering the three-dimensional (3-D) fringing capacitances. Based on three-dimensional simulation results, when the width of the FD SOI NMOS device is scaled down to 0.05 [mu]m, the inner-sidewall-oxide fringing capacitance (CFIS) is the second largest contributor to the gate-source capacitance (CGS).

A full-band particle-based simulator is used to investigate and compare the performance of silicon-on-insulator (SOI) and germanium-on-insulator (GOI) technologies, based on the cellular Monte Carlo method. The results indicate that drive currents are enhanced up to 25% by replacing Si with Ge, but the enhancement is only 13% with respect to the unity gain frequency in the case of a 50-nm MOSFET.

A simple and accurate analytical model for the threshold voltage of nanoscale single-layer fully depleted strained-silicon-on-insulator MOSFETs is developed solving the two-dimensional (2-D) Poisson equation. It is demonstrated that the proposed model correctly predicts a decrease in threshold voltage with increasing strain in the silicon thin film, and the proposed compact model can be easily implemented in a circuit simulator.

Accurate compact modeling in CMOS ultralarge scale integration (ULSI) technologies at the 65-nm node and beyond incorporates sources of intradie variation, which include lithographic effects from FET orientation, shape spacing to adjacent structures and relative location across the die. Advanced ULSI technologies provide the opportunities for high performance circuits, but present significant modeling challenges with regard to the proper positioning of intradie and interdie variations in the design flow.

Numerical two-dimensional simulations are used to show that parasitic gate-source/drain (G-S/D) fringe capacitance in nonclassical nanoscale CMOS devices are very significant, gate bias-dependent, and are markedly reduced by accurate G-S/D underlap. An analytical model for the parasitic capacitance is developed including inner- and outer- fringe components and ad BOX-fringe component for silicon-on-insulator MOSFETs, and is implemented in a process/physics-based compact model.

A completely surface-potential-based compact model for a fully depleted SOI-MOSFET, called the Hiroshima University semiconductor technology academic research center IGFET model silicon-on-insulator (HiSIM-SOI) is reported. The HiSIM-SOI is verified to reproduce measured I-V characteristics as also 1/f noise data of a 250-nm fully depleted SOI technology, while the stable convergence of HiSIM-SOI in the circuit simulation is confirmed.

The experimental data and modeling for the lateral thermal conductivity of ultrathin single-crystal silicon-on-insulator (SOI) layers at high temperatures are reported. The analytical thermal modeling and ISE-TCAD electrothermal simulations have confirmed that both the electrical and thermal performances of SOI transistor are largely affected if the reduced thermal conductivity of the silicon due to phonon boundary scattering is not properly taken into consideration.

The impact of some geometrical parameters on the ionization MOSFET (IMOS) performance such as, the gate length, the intrinsic length and the Si film thickness is investigated. The static and dynamic behaviors of an IMOS inverter are studied and the maximum frequency of the inverter is investigated by simulating an IMOS ring oscillator.

The effects of substrate-surface potential on the RF power performance of laterally diffused MOSFETs (LDMOSFETs) fabricated on high-resistivity silicon-on-insulator (HR-SOI) is studied in detail. Substrate-surface inversion and accumulation substantially degrade the RF power performance of these devices with the help of an RF shunt between source and drain through the substrate surface.

The dependence of the performance of silicon-on-insulator (SOI) Schottky-barrier (SB) MOSFETs on the SOI body thickness is studied and a performance improvement for decreasing SOI thickness is shown. A comparison is conducted of the inverse subthreshold slopes S extracted from the experiments with simulations and an analytical approximation.

An electrothermal model is presented for the lateral insulated gate bipolar transistor (LIGBT) structure based on a novel concept, silicon-on-membrane is presented. The model relies on a systematic study of both the isothermal and self-heating behaviors of the device.

The gate-source (drain)/source (drain)-gate capacitance behavior of 100-nm fully depleted silicon-on-insulator CMOS devices with HfO2 high-k gate dielectric are suggested considering vertical and fringing displacement effects is reported. A unique two-step [C.sub.S(D)G]/[C.sub.GS] versus [V.sub.G] curve could be identified for the device with the 1.5-nm HfO2 gate dielectric due to the vertical and fringing displacement effects.

A silicon-on-insulator (SOI) integration technology which includes structures and processes of OFF-gate power nMOSEFTs, conventional light doped drain (LDD) nMOSFETs, and spiral conductors for radio frequency integrated circuit (RFIC) applications are suggested. The body contact under the source and salicide techniques are developed for transistors to improve performance of the integrated devices and locally thickened oxide and ultra-thin aluminum are implemented for spiral inductors on high-resistivity SOI substrate and it was found that all these techniques are fully compatible with traditional CMOS processes and performance of the demonstrating devices is excellent.

A self-consistent Poisson-Schrodinger solver is used to measure the current and the quantum-mechanical effects in trigate n-channel silicon-on-insulator transistors. The threshold voltage is higher, the minimum energy for the electrons in the conduction energy subbands increases with the electron concentration, and this effect reduces the current drive of the device and is not predicted by classical simulators.

The RF performance of single-gate ultrathin-body (UTB) silicon-on-insulator (SOI) field-effect transistors (FETs) is analyzed. The influence of various gate stacks on the benefits of downscaling and the effect of source/drain series resistance on the RF figures-of-merit (FOMs) are investigated.

An extensive two-dimensional (2D) simulation-based design study is conducted to understand the scaling limits of ultrathin silicon-on-insulator (SOI) MOSFETs. The results have shown that channel doping does not have significant effect on the scaling limit.

Wide-band experimental and three-dimensional simulation analyses are carried out to compare the analog/RF performance of double-gate (DG), triple-gate (TG)/FinFET, Pi-Gate (PG) and single-gate (SG) SOI MOSFETs. The results have shown that multiple-gate devices have the edge over the SG devices due to the advantage of the volume inversion (VI) effect.

The fabrication of partially depleted (PD) and fully depleted (FD) strained-silicon-on-insulator (strained-SOI) MOSFETs and the performance enhancement of strained-SOI MOSFETs in the sub-100-nm region are described. The results have shown that strained-SOI n-MOSFETs can obtain the performance enhancement under sub-50-nm region.

A novel heterostructure double-gate FET (DGFET) that reduces large band-to-band tunneling (BTBT) leakage currents while retaining its high mobility, making it suitable for scaling into the sub-20-nm regime, is presented. The BTBT simulations have shown a dramatic reduction in BTBT and an excellent electrostatic control of the channel while maintaining very high drive currents and switching frequencies in these nanoscale transistors.

The fabrication and analysis of n- and p-MOSFETs in novel ultrathin-body (UTB) strained semiconductor heterostructure-on-insulator (HOI), achieved by epitaxial growth, bonding and transfer of strained layers, is described. Increased OFF-state leakage currents are seen in HOI compared to strained Si directly on insulator (SSDOI) and unstrained silicon-on-insulator (SOI) and for a 4-nm-thick buried SiGe layer, leakage is reduced relative to devices with thicker SiGe channels.

The tradeoffs between higher mobility channel and lower band-to-band tunneling (BTBT) leakage, especially the transport and leakage in ultrathin (UT) strained germanium (Ge) MOSFETs on bulk and silicon-on-insulator (SOI) are investigated. The results have shown that the UT defect-free channel can significantly alleviate the tunneling leakage problems of the strained SiGe due to quantum-mechanical bandgap widening, making the device a promising candidate for future high-performance devices.

Low-frequency noise characteristics of the silicon-on-insulator four-gate transistor [G(super 4)-field-effect transistor]are reported and the noise power spectral density as a function of biasing conditions is presented and compared for surface and volume conduction modes. It is shown that, for the same drain current, the volume of the transistor generates less noise that its surface.

An analytical tool gate capacitance model for symmetric double-gate (DG) and fully depleted silicon-on-insulator (FD/SOI) MOSFETs of arbitrary Si film is developed and demonstrated. Results show that the two-dimensional screening length for DG MOSFETs is independent of the doping intensity and much shorter than the bulk Debye length as a result of strong structural confinement.

A capacitorless one-transistor (IT)-dynamic random-access memory (DRAM) cell using gate-induced drain-leakage (GIDL) current for write operation is demonstrated. Compared with the conventional write operation with impact-ionization (II) current, the write operation with GIDL current achieves power consumption that is lower by four orders of magnitude and a write speed within several nanoseconds, indicating it as a promising technology for high-performance embedded-DRAM large-scale integration.

A compact model is developed for the effect of the parasitic internal fringe capacitance on the threshold voltage of high-kappa gate- dielectric silicon-on-insulator MOSFETs, which includes the effects of the gate-dielectric permittivity, spacer oxide permittivity, spacer width, gate length and the width of an MOS structure. The decrease in the threshold voltage with an increase in the gate-dielectric permittivity obtained using the analytical model is verified using two-dimensional device simulations.

The transport characteristics of ultrathin silicon-on-insulator MOSFETs are simulated and the influence of the quantum-mechanical mechanism on the short channel effects is evaluated on the basis of the density-gradient model. It is clearly shown that the quantum-mechanical mechanism suppresses the buried-insulator-induced barrier lowering with regard to the subthreshold swing and it is suggested that the mechanism enhances the impact of the apparent charge-sharing effect on the threshold voltage.

A detailed research of the high-frequency noise sources and figures of merit (FOMs) of fabricated deep-submicrometer n-channel fully depleted silicon-on-insulator MOSFETs is presented, Together with the calculation of intrinsic noise source, the Monte Carlo simulator is able to reproduce the measurement for the main noise FOMs in the RF and microwave frequency ranges.

The proposal of a new method for modeling the kink effect in partially depleted (PD) silicon-on-insulator (SOI) MOSFETs is discussed. When the load impedance is high and the frequency spacing is within the kink frequency domain, the kink effect degrades the intermodulation.

The characterization of the achievable high temperature coefficient of current (TCC) of standard CMOS transistors implemented in silicon-on-insulator (SOI) substrates is discussed. Achievable TCC of more than 6 percent K in subthreshold and less than -0.4 percent/K in saturation is observed.

The analysis of voltage derivative during inductive turnoff for a silicon-on-insulator (SOI) lateral insulated gate bipolar transistor (LIGBT) is discussed. Accurate device behavior is predicted with the model for different loading conditions and device parameters.

The evaluation of the on current and its ballistic limit for MOSFETs designed down to the 4-nm mode is discussed. Quasi-ballistic transport for gate length increases below approximately 50 nm and also contributes most part of the on current improvements related to scaling.

The electronic transport in bulk and double-gate (DG) silicon-on-insulator (SOI) MOSFETs with gate length down to 14 nm was examined with the use of Monte Carlo (MC) simulations including quantum correction to the potential and calibrated scattering models. The role of scattering in different parts of the device is clarified and the MC results are compared to simple models for quasi-ballistic transport presented.

The impact of an accumulation back-gate voltage on the linear kink effect (LKE) Lorentzians in thin-gate partially depleted silicon-on-insulator metal-oxide-semiconductor field-effect transistors (PD MOSFETs) is investigated. It is demonstrated that the front-back coupling effects can be explained by considering the increased body-source leakage currents.

The design features of the proposed Schottky collector structure and the reasons for its significantly improved breakdown performance are presented. The proposed structure is expected to be suitable in the design of the new generation scaled high voltage Schottky collector bipolar transistor for low power high-speed analog applications.

The process conditions, the formation, device characteristics and the geometry effects of modified Schottky barrier (MSB) junction are presented. It is concluded that MSB device is suitable for use as Fin FET and the MSB FinFET is a very promising nanodevice.