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Electron extraction mechanism of the Punch-through (PT) NPN diode is fully investigated and experimentally demonstrated. Similar to the N-type Schottky barrier, the PT -NPN region in the PT -NPN diode features a unipolar structure for electron unidirectional conduction. The hole injection of the PT -NPN diode can be tuned to a level close to that of the N-Schottky implemented PT -NPN (N-Schottky PT - NPN) diode due to the electron extraction. Experimental results show that softness factor of the PT - NPN diode is increased by 20% compared with that of the N -Schottky PT-NPN diode. In addition, the PT -NPN diode attains a stable breakdown voltage of 1268 V with a low leakage current. However, the leakage current of the N -Schottky PT - NPN diode is increased by 10 times when the barrier height is changed by 0.3 eV.

In this article, analysis and characterization of a new punchthrough (PT) n-p-n diode are performed. Numerical analysis shows that the PT voltage VPT and the p+ width ratio are the critical parameters to control the hole injection efficiency of the PT n-p-n diode. As a result, a locally reduced carrier profile can be realized due to the existence of electron extraction. Experimental results show that the leakage current of the PT n-p-n diode at 400 K can be kept at a level similar to that of a conventional Self-adjusting P Emitter Efficiency Diode (SPEED) with a well-designed VPT . In addition, a p+ width ratio of 20% is optimal for a better peak reverse recovery current ( Irrm ) and forward voltage ( VF ) tradeoff relationship. Compared with SPEED, the PT n-p-n diode achieves a reduced Irrm (−21%) and minimized reverse recovery loss Erec (−18%) at a nominal current. It can realize a significantly reduced Irrm (−42%) even at a small current and a bus voltage of 800 V. Moreover, better reverse recovery performances of the PT n-p-n diode are maintained at 400 K.

tradeoffs are investigated for SiC power MOSFETs using Al2O3/LaAlO3/SiO2 gate dielectrics. Due to the high gate capacitance, the Al2O3/LaAlO3/SiO2 gate device shows an improvement on the channel resistance (Rch) versus threshold voltage shift (AVth) tradeoff compared to the SiO2 gate coun-terpart. Besides, the short-circuit withstand time of the Al2O3/LaAlO3/SiO2 gate device is 1.55 times longer than that of the SiO2 gate device, while the two devices have the same on-resistance. Furthermore, the predicted lifetime of the Al2O3/LaAlO3/SiO2 gate device is ten years at an effective electric field (E-eff) of 4.8 MV/cm, which is comparable with the latest reported result of the SiO2 gate counterpart.

In the emerging heterogeneous power integration applications, the power devices have to be fabricated on metal/glass/organics. In this field, amorphous oxide semiconductors (AOSs) have being the dominant semiconductor material to fulfill the low-temperature fabrication requirement. In the AOSs, the theoretical tradeoff between specific oN-resistance (R-O(N, )sp) and breakdown voltage (BV) is discussed. It is found that the tradeoff is rather different from the situation in these commonly used single-crystal semiconductors. In the AOSs, under the one-dimensional condition, R-ON(, sp) is not proportional to BV2 due to the unique charge carrier mobility dependence on the carrier concentration. An analytical model has been extracted to describe such dependence, and it is found that R-O(N, sp) is proportional to BV4. Moreover, it is revealed that under a two-dimensional condition, such as reduced surface field (RESURF) condition, a "heavily doped" drift region can be used, and the mobility degradation issue could be resolved.

A fast and soft reverse recovery diode with a Punch-Through (PT) NPN structure is proposed and experimentally demonstrated. The structure features a P-type Schottky contact, a PT-NPN region for electron extraction, and a trench region with the bottom surrounded by a P-layer. Compared with conventional Self-adjusting P Emitter Efficiency Diode (SPEED), the proposed PT-NPN diode provides a much larger softness factor S (+23%), a shorter reverse recovery time Trr (-5%), and a much reduced reverse recovery charge Qrr (-20%) at nominal current. IEEE

Lateral metal–oxide–semiconductor field-effect transistors (MOSFETs) are fabricated on 4H-SiC utilizing deposited high- k gate dielectrics. The high- k gate-stack consists of thin nitrided SiO 2 and 40 nm of LaAlO 3 covered with a thin Al 2 O 3 cap. The high- k gate MOSFET achieves a 40% reduction in channel resistance (at Vgs=15 V) compared with that of the conventional SiO 2 gate MOSFET. In addition, bidirectional transfer characteristics of the high- k gate MOSFET indicate slight hysteresis and show a superior threshold voltage stability compared to that of competitors, in a range of −15 V ≤Vgs≤16 V under room and elevated temperatures. Therefore, the Al 2 O 3 /LaAlO 3 /SiO 2 gate-stack can provide both low on-resistance and good threshold voltage stability for SiC power MOSFETs.

In this letter, a suspended thick-winding inductor is demonstrated for integrated voltage regulator applications. A suspended thick-winding inductor with an area of 2.9 mm 2 and an inductance of 25 nH is designed and fabricated. The inductor has a winding thickness of 65 μm and a DC resistance of 121 mQ. A quality factor > 30 is maintained at 100-200 MHz. A peak inductor efficiency of 97.8% is analytically calculated for voltage conversion from 1.8 V to 1.1 V at 100 MHz.

In this letter, a fan-out-package-embedded power inductor technology is proposed. The inductor is embedded in a silicon-based fan-out package and surrounds the packaged die in which a voltage converter IC can be put. To demonstrate the integrated power inductor technology, a 2.4-nH air-core inductor for integrated voltage regulator applications is fabricated. The fabricated inductor shows a dc resistance of 5.0 mΩ and quality factors of 43–67 in the frequency range of 100–500 MHz. The small dc resistance and high quality factors make this integrated inductor technology promising for integrated power conversion. IEEE

In this letter, a fan-out-package-embedded power inductor technology is proposed. The inductor is embedded in a silicon-based fan-out package and surrounds the packaged die in which a voltage converter IC can be put. To demonstrate the integrated power inductor technology, a 2.4-nH air-core inductor for integrated voltage regulator applications is fabricated. The fabricated inductor shows a dc resistance of 5.0 mΩ and quality factors of 43–67 in the frequency range of 100–500 MHz. The small dc resistance and high quality factors make this integrated inductor technology promising for integrated power conversion. IEEE

In this paper, a novel silicon molded metal transfer process is developed to build on-chip suspended thick-winding inductors for high-frequency power management applications. In the proposed process, a silicon mold wafer coated with a heat-depolymerizable sacrificial layer is fabricated and used as the electroplating mold for thick-winding inductors formation; a simple transfer process is developed to release the inductors from the mold wafer and integrate the inductors with power IC chips. On-chip suspended power inductors with 65 µm thick windings are fabricated. The increased winding thickness leads to a more than 3 times reduction in DC resistance compared with inductors built by other suspended inductors fabrication techniques.

Trench field plate engineering for high efficient edge termination of 1200 V-class SiC devices is proposed and experimentally demonstrated. The structure features a deep trench filled with benzocyclobutene (BCB) dielectric, and a U-shaped field plate is incorporated in the deep trench. The deep trench extends through the epitaxial layer into the substrate to eliminate the negative effects of the microtrench on breakdown voltage. The U-shaped field plate modulates the electric field distribution to prevent premature breakdown at the interface between the P-base and trench. The SiC outside the trench is diced away to reduce the peak electric field at the edge of the field plate by spreading the electrostatic potential both horizontally and vertically. The trench field plate edge termination structure is implemented by integrating with a PiN diode. Experimental results show that the structure achieves a breakdown voltage of 1380 V, which is approximately 100% of the ideal planar junction breakdown voltage of the PiN diode. The fabricated edge termination structure has an ultra-short width of 33 mu m. Compared with conventional junction termination extension structures used in 1200 V-class SiC devices, the width of the proposed structure is approximately 75% shorter.

In this article, design and characterization of the deep-trench, U-shaped field-plate (DTUFP) edge-termination structure for 1200-V-class silicon carbide (SiC) devices are presented. A systematic numerical analysis shows that the trench depth, trench width, field-plate depth, and field-plate length are the four key structural parameters to determine the voltage blocking capability of the edge-termination structure. Experimental results demonstrate that the breakdown voltage of the proposed edge-termination structure can reach 1380 V when the edge-termination structure is well designed. Liquid crystal thermal measurement and destructive breakdown testing show that the ideal planar junction breakdown voltage has been achieved. The well-designed edge-termination structure has an ultrashort-edgewidth of 33 mu m, which is approximately 75% shorter than that of the conventional guard-ring and junction termination extension (JTE) edge-termination structures.

In this letter, a novel monolithically integrated Si-GaN cascoded FET is designed and experimentally demonstrated for high-voltage power switching applications. The device is formed by monolithically connecting a low-voltage Si MOSFET and a high-voltage normally-on GaN MIS-HEMT on the same substrate in the cascode configuration. The interconnection distance is 50 μm which is only 2.5% of that of the conventional two-chip co-package approach (~2 mm). The fabricated cascoded FET features normally-off functionalities with a threshold voltage of 3.2 V, a drive current of 1850 A/cm2 (630 mA/mm) at the gate bias of 15 V, a gate swing of 20 V, a specific on-resistance of 3.3mΩ⋅cm2 and a breakdown voltage of 696 V.

In this paper, fabrication process of the fully integrated Si-GaN cascoded field effect transistor is presented first. Device performance of the individual Si MOSFET and AlGaN/GaN MIS-HEMT, which are fabricated along with the Si-GaN cascoded FET, are then characterized. Finally, the device performance of the fully integrated cascoded FET is characterized in detail, including the transconductance compression at high VGS and high VDS, the reverse conduction, the power figure-of-merit (FOM), and the high-Temperature characteristics. It is shown that the Si-GaN monolithic cascoded FET is a promising candidate for high performance power switching applications. © 2018 IEEE.

In this letter, a novel approach for monolithic integration of Si-based and GaN-based devices on Si substrate for high-voltage power switching applications is reported. To enable the integration, AlGaN/GaN epitaxial growth is carried out in recessed windows on a Si (111) substrate by selective epitaxial growth. A cascoded diode formed by series connection of a Si diode and a normally-ON AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistor is experimentally demonstrated by using this technology. The cascoded diode features a breakdown voltage of 557 V and a differential specific ON-resistance of 2.8 mΩ· cm2 at 500 A/cm2. Its reverse leakage current is two orders of magnitude lower compared with the conventional AlGaN/GaN Schottky barrier diode. The characterization results of the fabricated cascoded diode demonstrate that the proposed Si-GaN monolithic integration technology is compatible with both Si and GaN fabrication processes.

In this paper, a new 1200 V-class edge termination structure with trench double field plates is proposed and experimentally demonstrated. The double field plates are buried inside the trench. One of the field plates is for modulating electric field distributions along the trench and shifting the breakdown point to the active region for achieving the ideal planar junction breakdown voltage, and the other one is for stopping the depletion region extension at the right side of the trench to achieve high dV/dt performance. The fabricated device has a breakdown voltage of 1422 V which is verified as the ideal planar junction breakdown voltage. Furthermore, it is with a record-short edge termination length of 78 μm which is less than one-fifth of conventional guard ring approaches. Besides, it can handle a high dV/dt value of 73 kV/μs even at a bus voltage of 1400 V. © 2017 IEEJ.

A lighting device is provided. The lighting device includes a substrate, integrated circuits (22', 24), embedded passive components (26, 27), and a lighting component (22), the device being arranged in an architecture having three layers: an integrated circuits layer (11) including the integrated circuits (22', 24), wherein the integrated circuits layer (11) is integrated on a first side of the substrate; an embedded passive components layer (12) including the embedded passive components (26, 27), wherein the embedded passive components (26, 27) are embedded in grooves formed in the substrate and wherein the embedded passive components are connected to the integrated circuits (22', 24) through vias (28) in the substrate; and a bonded layer (13), including the lighting component (22), the lighting component (22) being connected to the integrated circuit layer (11) through flip-chip bonding or monolithic integration.

A novel sloped field plate (FP)-enhanced ultra-short edge termination structure is proposed and experimentally demonstrated. The structure features a benzocyclobutene dielectric filled trench, and is fabricated along with a high-voltage p-i-n diode. In addition, a sloped FP is put inside the trench and connected to the anode electrode. The fabricated device shows a breakdown voltage of 755 V, and is confirmed as the ideal planar junction breakdown voltage of the p-i-n diode. The proposed edge termination structure has a total width of 35 mu m, which is similar to 1/5 the size of a conventional termination structure using the guard rings approach.

In this paper, an analytical model for calculating the ac resistance due to the proximity effect in thick coil integrated spiral inductors is proposed. Based on 2-D Maxwell's equations, the redistribution of magnetic field and current in the coils caused by the proximity effect is modeled, and the ac resistance of the inductor is extracted. The analytical model is compared with both numerical simulations and experimental results. The ac resistance calculated by the model is good (within 14.8% discrepancy) up to the frequency of the peak quality factor for thick coil integrated spiral inductors.

In this paper, a new 1200 V-class reverse-conducting insulated gate bipolar transistor (RC-IGBT) for hard-switching applications is proposed. The proposed structure features deep metal plugs at the emitter-side, and Schottky junctions are formed between the metal plugs and the p-body regions. This design reduces the anode injection efficiency of the built-in diode. Simulation results show that the proposed structure can achieve a significant reduction in the diode-mode reverse-recovery loss, Err, (−70% at R.T. and −57% at 150°C) without degrading the IGBT-mode performance compared with conventional RC-IGBT. Furthermore, it is also found that the proposed structure can achieve comparable diode-mode performance in terms of Err and Vf (diode-mode forward voltage) compared with those of the state-of-the-art discrete free-wheeling diodes for hard-switching applications.

The effects of Al doping on the charge-trapping characteristics of ZrO2 are investigated based on Al/Al2O3/Al-doped ZrO2/SiO2/Si structure. XRD and XPS show that the crystallization of ZrO2 and the formation of silicate interlayer at the ZrO2/SiO2 interface are effectively suppressed by Al incorporation, thus resulting in better electrical performance with larger memory window and better retention for the memory device with Al-doped ZrO2 as the charge-trapping layer (CTL) than the one with pure ZrO2. However, excessive Al doping in ZrO2 severely reduces the dielectric constant and electron traps of the CTL, thus leading to much lower program speed for the device.

In this paper, the transient turn-ON performance of the 1200 V-class fin p-body insulated gate bipolar transistor (Fin-p IGBT) is numerically analyzed and experimentally characterized. Analysis shows that the gate self-charging effect at the turn-ON transient of the device can effectively be suppressed due to its unique structural features of wide trenches and spacer gates. As a result, the Fin-p IGBT demonstrates excellent controllability on the turn-ON dVCE/dt of the IGBT, and hence the reverse-recovery dVKA/dt of the free-wheeling diode. Compared with conventional floating p-body IGBTs, the Fin-p IGBT can achieve a significant reduction (up to 82%) in the reverse-recovery dVKA/dt , which is of great merit in suppressing the electromagnetic interference noise. Moreover, the turn-ON energy loss of the Fin-p IGBT can be reduced by 53% compared with that of the conventional one at the same reverse-recovery dVKA/dt of 10 kV/μs. © 1963-2012 IEEE.

Monolithically integrated Light-Emitting Diode (LED) drivers greatly reduce the cost as well as enhance the reliability of LED system due to their reduction of bulky and expensive off-chip components and assembling cost. However, integrating all the passive and active components of an LED driver on chip is very challenging. This paper discusses current issues of designing a monolithically integrated LED driver and presents some considerations to these problems.

In this paper, a low substrate loss, monolithically integrated power inductor for compact LED drivers is designed and experimentally demonstrated. A 5.2 mu H inductor is embedded at the backside of the silicon substrate, and the low-k, insulating material SU-8 is used to reduce the substrate loss. The inductor achieves a DC resistance of 2.3 Omega and a peak Q factor of 22 at 3.4 MHz. The inductor, controller, and LED array are flip-chip bonded on a silicon slab for discrete implementation of the monolithically integrated LED driver which achieves an overall power efficiency of 73%.

The subject disclosure presents power semiconductor devices, and methods for manufacture thereof, with improved ruggedness and. In an aspect, the power semiconductor devices are power field effect transistors (FETs) having enhanced suppression of the activation of the parasitic bipolar junction transistor (BJT) and a normal threshold value. The devices comprise a doped source (14) of a first conductivity type, a doped body (15) of a second conductivity type, a source electrode (20) short-connecting the doped body and the doped source, a doped drift region (10) of the first conductivity type, a first layer (30) of a gate dielectric region (36) covering the surface of the doped drift region (10), and forming channel from the doped source (14) to the doped drift region (10), a second layer (31) of the gate dielectric region (36) over the first layer (30), a third layer (32) of the gate dielectric region (36) over the second layer (31), and a gate electrode (21) over the third layer (32).

In this brief, a backside silicon-embedded transformer (BSET) with an improved isolation structure is proposed and demonstrated. The interleaved transformer coils are embedded inside a silicon substrate from the backside and connected to the front-side through vias. The isolation between the coils is achieved by the oxide layer between the Cu coil and the Si substrate, as well as the BCB (BenzoCycloButene) layer covering the backside of the transformer. The 2-mm(2) BSET fabricated shows a best reported monolithic transformer efficiency of over 80% at a low frequency of 20 MHz. A 380 V isolation capability is achieved and shows the potential for various applications, such as USB (Universal Serial Bus) isolation. Only three masks are required for the fabrication. This technology is very suitable for on-chip isolated power transfer applications.

Charge-trapping properties of Nb-doped La2O3 (LaNbO) are investigated using an Al/Al2O3/LaNbO/SiO2/Si structure. Compared with the memory device with La2O3, the one with LaNbO shows better charge-trapping characteristics, including larger memory window (6.0 V at ±16 V sweeping voltage), higher programming speed (9.1 V at +16 V for 1 ms), and better retention property (94% charge retained after 104 s at 120 .C), due to its higher trapping efficiency resulted from increased trap density and suppressed formation of a silicate interlayer at the LaNbO/SiO2 interface by the Nb doping. Therefore, LaNbO is a promising candidate as the charge-trapping layer for nonvolatile memory applications. © 2015 IEEE.

The charge-trapping properties of Gd2O3 with different Nb doping levels are investigated using an Al/Al2O3/Gd2O3/SiO2/Si structure. Compared with the memory device with pure Gd2O3, the one with lightly Nb-doped Gd2O3 shows better charge-trapping characteristics, including higher programming speed (6.5 V at +12 V programming voltage for 10 ms) and better retention property (92% retained charge at 85 °C after 104 s), due to its higher trapping efficiency that resulted from higher trap density and suppressed formation of a silicate interlayer at the Gd2O3/SiO2 interface induced by the Nb doping. Moreover, the one with heavily Nb-doped Gd2O3 shows improvement in erasing behavior but worse retention and lower programming speed than the one with lightly Nb-doped Gd2O3. Further analysis reveals that the Nb-doping level determines the type of dominant trap in the Nb-doped Gd2O3, thus leading to different charge-loss mechanisms and charge-trapping characteristics. © 2015 AIP Publishing LLC.

In this paper, a low substrate loss, monolithically integrated power inductor for compact LED drivers is designed and experimentally demonstrated. A 5.2 mu H inductor is embedded at the backside of the silicon substrate, and the low-k, insulating material SU-8 is used to reduce the substrate loss. The inductor achieves a DC resistance of 2.3 Omega and a peak Q factor of 22 at 3.4 MHz. The inductor, controller, and LED array are flip-chip bonded on a silicon slab for discrete implementation of the monolithically integrated LED driver which achieves an overall power efficiency of 73%.

In this letter, a novel integrated power inductor with a vertical laminated NiFe magnetic core for improved inductance to resistance ratio (L/R) ratios is proposed and demonstrated. Both the windings and magnetic core are accommodated within a groove at the backside of a silicon substrate and connected to the front-side IC through vias for compactness. NiFe is used to increase the inductance, and vertical lamination is used to suppress the eddy current in the magnetic core and assist hard axis alignment. A 1-mm2 embedded inductor with 131-nH inductance and 60-mΩ dc resistance working in megahertz range is fabricated. The L/R ratio is increased by seven times compared with integrated inductors with similar area, making it suitable for portable electronics power conversion system-on-chip applications.

Aimed at reducing the form factor of LED systems, we presented an innovative concept of a highly-integrated single platform with successful demonstration by integrating a high-voltage LED, driver and inductor through flip-chip bonding.

Methods and apparatus described herein are associated with integrated magnetic induction devices. A magnetic induction device can include a groove formed in a substrate, a magnetic core included in the groove and surrounded by a conductive winding that is adjacent to portion(s) of the substrate, and respective insulation layers included between the substrate and the conductive winding and between the magnetic core and the conductive winding. An inductor can further include conductive vias formed in the substrate and connected to respective portions of the conductive winding. Further, a transformer can include a groove formed in a substrate, a closed-loop/gapped magnetic core included in the groove and surrounded by first and second conductive windings that are adjacent to respective portions of the substrate, and respective insulation layers formed between the substrate and the first and second conductive windings, and between the closed-loop/gapped magnetic core and the first and second conductive windings.

This study describes a through-silicon-underfill dispensing that the encapsulant is dispensed through through-silicon-vias (TSVs). The TSVs function as entrances for encapsulant dispensing or paths for fluid flow. Typically, the inflow for TSV dispensing may be flow with a constant speed or free droplets. A model was developed to investigate the filling time and the pressure distribution for the quasi-steady, radial and laminar flow between parallel plates. Compared with free droplets, a constant inflow has shorter filling time at the expense of increasing the fluid pressure. 3D stacking with the same-size interposers forms several planar sidewalls. Encapsulant may flow out from the edges of the sidewalls and form an edge flood failure if the edge flow of an underfill can overcome the surface force. An optimized pattern of TSVs was designed for the underfill of a 3D package to identify the trade-off between the filling efficiency and the lower risk of the edge flood. In each interposer, the TSVs are classified into two groups: the central group is dispensed by a constant inflow whereas the outer group is dispensed by free droplets; the inflow of free droplets eliminates the risk of an edge flood. A four-stack 3D package with the optimized TSV pattern was developed for validation. Edge dispensing was used to fill the gaps at the bottom levels as much as possible. Subsequently, the remaining gaps were encapsulated by TSV dispensing (with both a constant inflow and an inflow of free droplets). Inspections by scanning acoustic microscopy and cross-sectioning verified that the combined underfill could result in a void-free encapsulation and suitable fillets.

Digitally controlled switching converter suffers from bandwidth limitation because of the additional phase delay in the digital feedback control loop. To overcome the bandwidth limitation without using a high sampling rate, this study presents an adaptive third-order digital controller for regulating a voltage-mode buck converter with a modest 2x oversampling ratio. The phase lag because of the analogue-to-digital converter (ADC) conversion time delay is virtually compensated by providing an early estimation of the error voltage for the next sampling time instant, enabling a higher unity-gain bandwidth without compromising stability. An additional pair of low-frequency pole and zero in the third-order controller increases the low-frequency gain, resulting in faster settling time and smaller output voltage deviation during line transient. Both simulation and experimental results demonstrate that the proposed adaptive third-order controller reduces the settling time by 50% in response to a 1 V line transient and 30% in response to a 600 mA load transient, compared to the baseline static second-order controller. The fastest settling time is measured to be about 11.70 mu s, surpassing the transient performance of conventional digital controllers and approaching that of the state-of-the-art analogue-based controllers.

In this paper, the design of an inductive power link (IPL) for wireless power transfer (WPT) in brain-machine interface (BMI) applications is thoroughly studied. The constraints and requirements of BMI applications are analyzed. By theoretical derivations, the relationships between the IPL performances and its electrical parameters are determined. The design guidelines for the IPL physical parameters are then obtained through experimental characterizations. Experimental results show that with proper IPL design, the efficiency can be improved from the previously reported values of 29.9% and 4.3% to 33.1% and 9.2% for BMI WPT distances of 5 and 12.5 mm, respectively. © 1986-2012 IEEE.

A simple low cost monolithic 3D through-silicon-via coreless transformer is designed and fabricated for high-voltage gate driver applications. The transformer comprises the primary coil embedded in the bottom layer of a Si substrate and the secondary coil built on the front-side of the substrate. Compared with conventional transformers with both coils built on the front-side or at the backside, the proposed structure has the advantages of area-saving and cost-effectiveness. A coreless transformer with primary, secondary, and mutual inductances of 260, 280, and 112 nH, respectively, is fabricated in a small area of 2 mm(2). It achieves both high galvanic isolation (>4 kV) and satisfactory voltage gain (0.41 from 4 to 45 MHz).

There has been growing interest in single-inductor multiple-output (SIMO) dc-dc converters due to its reduced cost and smaller form factor in comparison with using multiple single-output converters. An application for such a SIMO-based switching converter is to drive multiple LED strings in a multichannel LED display. This paper proposes a quasi-hysteretic finite-state-machine-based digitally controlled single-inductor dual-output buck switching LED driver operating in discontinuous conduction mode (DCM) and extends it to drive multiple outputs. Based on the time-multiplexing control scheme in DCM, a theoretical upper limit of the total number of outputs in a SIMO buck switching LED driver for various backlight LED current values can be derived analytically. The advantages of the proposed SIMO LED driver include reducing the controller design complexity by eliminating loop compensation, driving more LED strings without limited by the maximum LED current rating, performing digital dimming with no additional switches required, and optimization of local bus voltage to compensate for variability of LED forward voltage V-F in each individual LED string with smaller power loss. Loosely binned LEDs with larger V-F variation can, therefore, be used for reduced LED costs.

A novel silicon-nitride-oxide-silicon (SNOS) gate-controlled, normally-off p-i-n switch (SGPINS) is proposed and experimentally demonstrated. The normally-off of the SGPINS is implemented by using a fully depleted n(-)-channel region that is controlled by an SNOS trench gate. The device has a threshold voltage of 7 V and an avalanche breakdown voltage of similar to 1000 V. ON-state voltage drop of the SGPINS is 1.7 V, and is similar to 0.6 V lower than that of an IGBT with the same non-punch-through structure, resulting in similar to 26% reduction in the conduction loss.

Both p- and n-channel poly-Si/Sil1-xGe/Si sandwiched conductivity modulated TFTs (CMTFTs) are demonstrated. The transistors use a poly-Si/Sil1-xGe/Si sandwiched structure as the active layer and the concept of conductivity modulation in the offset region. Results show that the transistors provide over an order of magnitude higher on-state current as well as low leakage current compared to those of conventional offset drain TFTs: The devices are most suitable for high-voltage drivers in low temperature fully-integrated large area electronic applications.

This study describes a through-silicon-underfill dispensing that the encapsulant is dispensed through through-silicon-vias (TSVs). The TSVs function as entrances for encapsulant dispensing or paths for fluid flow. Typically, the inflow for TSV dispensing may be flow with a constant speed or free droplets. A model was developed to investigate the filling time and the pressure distribution for the quasi-steady, radial and laminar flow between parallel plates. Compared with free droplets, a constant inflow has shorter filling time at the expense of increasing the fluid pressure. 3D stacking with the same-size interposers forms several planar sidewalls. Encapsulant may flow out from the edges of the sidewalls and form an edge flood failure if the edge flow of an underfill can overcome the surface force. An optimized pattern of TSVs was designed for the underfill of a 3D package to identify the trade-off between the filling efficiency and the lower risk of the edge flood. In each interposer, the TSVs are classified into two groups: the central group is dispensed by a constant inflow whereas the outer group is dispensed by free droplets; the inflow of free droplets eliminates the risk of an edge flood. A four-stack 3D package with the optimized TSV pattern was developed for validation. Edge dispensing was used to fill the gaps at the bottom levels as much as possible. Subsequently, the remaining gaps were encapsulated by TSV dispensing (with both a constant inflow and an inflow of free droplets). Inspections by scanning acoustic microscopy and cross-sectioning verified that the combined underfill could result in a void-free encapsulation and suitable fillets.

Aimed at reducing the form factor of LED systems, we presented an innovative concept of a highly-integrated single platform with successful demonstration by integrating a high-voltage LED, driver and inductor through flip-chip bonding.

In this paper, a set of backside silicon-embedded inductors (BSEIs) is fabricated and characterized for potential applications in next-generation fully integrated power electronics. The fabrication technology of the BSEI is very similar to the through-silicon-via technology and has a high potential for post-CMOS integration. Without using magnetic material, an inductance as high as 13.8 mu H is achieved with an effective inductance density of 0.6 mu H/mm(2). For the 4.5 mm x 4.5 mm BSEIs with a high substrate resistivity, an inductance between 2 and 4 mu H, a dc resistance of 0.6-1.4 Omega, and a peak quality factor ranging from 18 to 23 occurring at 2-5 MHz are experimentally demonstrated. The effects of various physical design parameters are also experimentally studied, including coil outer dimension, metal width/spacing/ pitch, coil shape, and silicon resistivity. These measurement results illustrate the design flexibility of the proposed BSEI technology to allow tradeoffs of key electrical properties for meeting different requirements of various integrated power electronics.

In this letter, a silicon-embedded receiving coil is designed and fabricated for high-efficiency wireless power transfer to implantable biomedical ICs. The 4.5 mm × 4.5 mm embedded receiving coil achieved a large inductance of 4 μ H and a high peak quality factor of 20 at 2.8 MHz. Measurement results of an inductive power link using the embedded receiving coil and a conventional printed-circuit-board transmitting coil (2 cm × 2 cm) demonstrated peak voltage gains of 0.84 and 0.24 and peak efficiency values of 30% and 4.3% for separation distances of 5 and 12 mm, respectively. This is the best reported wireless power transmission efficiency for separation distance similar to the implant chip size. © 2012 IEEE.

From power electronics to power integrated circuits (PICs), smart power technologies, devices, and beyond, Integrated Power Devices and TCAD Simulation provides a complete picture of the power management and semiconductor industry. An essential reference for power device engineering students and professionals, the book not only describes the physics inside integrated power semiconductor devices such lateral double-diffused metal oxide semiconductor field-effect transistors (LDMOSFETs), lateral insulated-gate bipolar transistors (LIGBTs), and super junction LDMOSFETs but also delivers a simple introduction to power management systems. Instead of abstract theoretical treatments and daunting equations, the text uses technology computer-aided design (TCAD) simulation examples to explain the design of integrated power semiconductor devices. It also explores next generation power devices such as gallium nitride power high electron mobility transistors (GaN power HEMTs). Including a virtual process flow for smart PIC technology as well as a hard-to-find technology development organization chart, Integrated Power Devices and TCAD Simulation gives students and junior engineers a head start in the field of power semiconductor devices while helping to fill the gap between power device engineering and power management systems.

We adopt silicon IC technologies into LED lighting and display to improve the overall efficiency and reliability of the system. In parallel, our integrated approach will also enable novel applications while decreasing system form factor and total cost of ownership with increased reliability. Our platform focuses on novel LED system designs on silicon wafers to allow for high volume manufacturing with mature Si IC technology and to leverage the cost advantages of CMOS scaling. Integration of all the components, active and passive, on a Si platform is the ultimate goal.