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In this work, IGZO device integration is reported leveraging our 300mm-fab facilities. Our objective is mainly to gain insights into the process and material elements which drive the control of the performance parameters of IGZO nFETs. To control the final doping of the IGZO channel, it is well reported in literature that a final oxygen anneal can be applied to passivate the oxygen vacancies which are formed during the device fabrication. This technique is also used in our 300mm flow. As it might be expected, in front gate IGZO nFETs, the passivation efficiency is limited by the presence of the top metal gate stack. Therefore, it seems important to limit the formation of the oxygen vacancies during the deposition of the gate dielectrics. Three oxides were studied: SiO2, Al2O3 and HfO2 on top of the IGZO channel. After oxygen annealing, only PECVD-SiO2 shows a large recovery while for Al2O3 and HfO2, it remains low. This result challenges the implementation of conventional water-based high-K materials in gate first IGZO integration. Contrary to the use of undoped IGZO in the channel for IOFF control, contacts can rely on maximizing the oxygen vacancies to increase the dopant concentration in the S/D regions. When not done locally, it could be an extra source of variability. This doping is made through oxygen scavenging from IGZO by a thin metal contact barrier. Low specific contact resistivity down to 1x107 Ohm.cm2 is demonstrated when Ti is thinner than 5nm. With thicker barrier, the formation of TiO2 and specific alloys is taking place at the IGZO/Contact barrier interface. This is both confirmed by ab initio simulations and by advanced physical characterization techniques. Regarding the channel, X-ray diffraction techniques are extensively here since this is a nondestructive in-fab technique that provides detailed information about the crystallographic structure of the IGZO material. We show a typical spectrum where clear peaks/humps are seen and attributed to: 1. amorphous IGZO, 2. CAAC-IGZO and 3. a previously not reported, to the best of our knowledge, phase called here s-IGZO. The s-phase is only formed under certain conditions of power, temperature and oxygen flow during material deposition. Thick IGZO (>12nm) back-gated nFETs with active layers submitted to final O2 anneal are used to study the different phases of IGZO and their electrical impact on device parameters. In this configuration, the carrier transport preferentially occurs in the bottom half of the IGZO channel while the top half (SiO2/IGZO interface) mostly drives the electrostatic control of BG transistors. The amorphous IGZO has much reduced spread in VTH-ON and higher ID,LIN (~mobility) than that of CAAC-IGZO. Reliability tests have also been carried out to compare the two phases and the results show the existence of two competing PBTI degradation mechanisms for CAAC-IGZO. It is important to report the degradation over time and different VG stress because a cut line at a specific value could have shown no BTI degradation of CAAC-IGZO and then attributing an unfair benefit of this phase over the a-IGZO phase. Combining these findings to some other results where the sheet resistance of IGZO under hydrogen exposure depends on the phases, we can reasonably conclude that CAAC owns different doping levels in comparison to a-IGZO. Based on the previous learning about n-type dopant location in IGZO, we show that the performance of transistors keeps increasing when the channel length is reduced and scales with the channel width. A measure of the VTH-ON variation has been performed at the 300mm wafer scale from long to ~120nm LCH and down to 200nm WCH dimensions. The figure in attachement shows the Id-Vg curves of >100 Back Gated IGZO-nFETs with no failed devices detected. The standard variation of the VTH-ON across LCH and WCH is often less than 40mV with a minimum of 20mV. In conclusion, we have demonstrated in this study scaled IGZO nFETs with excellent VTH_ON control using an industry compatible 300mm process flow. This has been achieved thanks to a careful mapping of n-type doping in the three dimensions of the IGZO channel. While semi-crystalline IGZO seems to be more robust against hydrogen than that of amorphous-IGZO, a new IGZO phase is found to help boost ION at short channel. The demonstration of back-gate IGZO nFETs with low variability and relatively high drive will benefit to the top-gate architecture development. This will provide new opportunities for the IGZO-based devices like an “on-the-fly” VTH setting for the performance control of advanced applications. Figure 1

This paper analyzes the effect of high current under illumination stress (HCIS) in self-aligned amorphous indium gallium zinc oxide transistors with Al2O3 as high- $\kappa $ gate dielectric. A negative parallel threshold voltage $({V}_{T}$ ) shift with the appearance of hysteresis $(\Delta {V}_{{hys}})$ is observed after HCIS. In contrast to the double ionized oxygen vacancy ( $\text{V}_{\text O}^{\text 2+}$ ) theory, a peroxide donor theory based on ${ab~ initio}$ calculations is proposed to explain the degradation. Several methods are carried out to support the mechanism, including $\Delta {V}_{{hys}}$ generation, stress recovery behavior and capacitance-voltage ${(C-V)}$ measurements. A linear dependence between initial ${V}_{T}$ and negative ${V}_{T}$ shift is observed that further supports the peroxide theory. This work highlights the importance of evaluating the HCIS for oxide base semiconductor devices.

We show a thin, flexible and large 500 dpi fingerprint sensor for security applications providing better usability than existing sensors with a similar performance. A new process flow, using PVDF-TrFE pyroelectric capacitors on top of an IGZO TFT backplane on a flexible polyimide (PI) foil is implemented to create an active thermal fingerprint sensor. The system measurements fit well with the simulation of the thermal operation.

In this paper, the influence of oxygen partial pressure ( ${P}_{\textsf {O2}}$ ) during physical vapor deposition on the field-effect mobility of amorphous InGaZnO (IGZO) thin-film transistor (TFT) is investigated in a wide range of ${P}_{\textsf {O2}}$ . The field-effect mobility reduced from 12 to 0.1 cm $^{\textsf {2}}/\textsf {V}~\cdot $ s when the ${P}_{\textsf {O2}}$ is increased from 0.3 to 1.5 mTorr. Temperature-dependent TFT measurements suggest that carrier transport in the TFTs deposited at the ${P}_{\textsf {O2}}$ of 0.3 mTorr can be described according to the multiple trap and release/percolation model. However, the carrier transport in the TFTs deposited at the ${P}_{\textsf {O2}}$ of 1.5 mTorr conforms to Mott’s variable-range hopping model. The elastic recoil detection analysis indicates that hydrogen concentration in the IGZO film increased with ${P}_{\textsf {O2}}$ . The X-ray photoelectron spectroscopy results indicate that In vacancy ( ${V}_{\textsf {In}}$ ) defects formed in the IGZO film deposited at high ${P}_{\textsf {O2}}$ . Scattering induced by hydrogen and pinning of Fermi level below the conduction band edge by ${V}_{\textsf {In}}$ are plausible reasons for the low field-effect mobility in TFTs deposited at high ${P}_{\textsf {O2}}$ .

We present a thin-film dual-layer bottom barrier on polyimide that is compatible with 350°C backplane processing for organic light-emitting diode displays and that can facilitate foldable active-matrix organic light-emitting diode devices with a bending radius of

High-resolution RGB organic light-emitting diode frontplane is a key enabler for direct-view transparent augmented reality displays. In this paper, we demonstrate 1250 ppi passive displays and semi-transparent active displays. Organic light-emitting diode photolithography can provide pixel density above 1000 ppi while keeping effective emission area high because of high aperture ratio. Patterns with 2 μm line pitch were successfully transferred to emission layers, indicating possible further pixel density scaling. Lifetime after patterning, key parameter enabling industrialization, is above 150 h (T90 at 1000 nit).

In this work, we have reported dual-gate amorphous indium gallium zinc oxide thin-film transistors (a-IGZO TFTs), where a top-gate self-aligned TFTs has a secondary bottom gate and the TFT integration comprises only five mask steps. The electrical characteristics of a-IGZO TFTs under different gate control are compared. With the enhanced control of the channel with two gates connected together, parameters such as on current (ION), sub-threshold slope (SS−1), output resistance, and bias-stress instabilities are improved in comparison with single-gate control self-aligned a-IGZO TFTs. We have also investigated the applicability of the dual-gate a-IGZO TFTs in logic circuitry such as 19-stage ring oscillators.

We present a qHD (960 × 540 with three sub-pixels) top-emitting active-matrix organic light-emitting diode display with a 340-ppi resolution using a self-aligned IGZO thin-film transistor backplane on polyimide foil with a humidity barrier. The back plane process flow is based on a seven-layer photolithography process with a CD = 4 μm. We implement a 2T1C pixel engine and use a commercial source driver IC made for low-temperature polycrystalline silicon. By using an IGZO thin-film transistor and leveraging the extremely low off current, we can switch off the power to the source and gate driver while maintaining the image unchanged for several minutes. We demonstrate that, depending on the image content, low-refresh operation yields reduction in power consumption of up to 50% compared with normal (continuous) operation. We show that with the further increase in resolution, the power saving through state retention will be even more significant.

Every neuron in a human brain is connected via its synapses to 10-15.000 other neurons. Those connections can over time be reconfigured allowing new connections with any other neuron. But only few of the longer connections are concurrently active. BEOL TFT should enable large scale reconfigurable interconnect that allows to connect every neuron with every neuron even across the whole neuromorphic IC but with only limited amount of them concurrently active.

In this work a metal-oxide (Indium Gallium Zinc Oxide) 6-bit successive approximation metal-insulator-metal C2C analog to digital converter (ADC) fabricated on $15 \mu \mathrm{m}$ thick flexible substrate is demonstrated. The ADC is operated at a clock speed of 2kHz and at a power supply of 15V. The power dissipation including output buffers is $212 \mu \mathrm{W}$ at 15V and the a sampling rate of 134S/s. The ADC achieves a Figure of merit (FoM) of 16.58nJ/c.s. and no missing codes using dual gate self-aligned n-type thin-film transistors on polymeric substrate.

This study sheds light on the microscopic mechanisms by which self-assembled monolayers (SAMs) determine the onset voltage in organic thin-film transistors (OTFTs). Experiments and modeling are combined to investigate the self-assembly and electrostatic interaction processes in prototypical OTFT structures (SiO2/SAM/pentacene), where alkylated and fluoroalkylated silane SAMs are compared. The results highlight the coverage-dependent impact of the SAM on the density of semiconductor states and enable the rationalization and the control of the OTFT characteristics. ispartof: ACS Applied Materials and Interfaces vol:6 issue:17 pages:15372-15378 ispartof: location:United States status: published

SnO is one of the few candidates for p-type oxide thin film transistors (TFTs) because it retains a reasonable high hole mobility in a nanocrystalline film. However, the high off-current of SnO TFT limits its usefulness. In this work, SnO TFTs were fabricated using thermal evaporation under ultra-high vacuum. In order to decrease the off-current in p-type SnO thin film transistors (TFTs), we used yttrium to reduce n-type minority charges in the channel. The on/off ratio of the TFT increases from 102 to 5104 and the mobility of the TFT in the saturated regime reduces from 1.6 to 1.4 cm2/V s when the SnO channel is doped with 1 wt. % of Y. Grazing incidence X-ray diffraction and X-ray photoelectron spectroscopy reveal that the reduction of SnO2 in the Y-doped SnO TFT channel is the main reason for the improvement in the TFT characteristics.

In this work, we report on high-performance coplanar self-aligned (SA) amorphous-Indium-Tin-Zinc-Oxide (a-ITZO) thin-film transistors (TFTs) on flexible polyimide substrate. The a-ITZO films are first optimized with respect to the oxygen ratio, thickness and final anneal conditions with common-gate TFTs structure on Si/SiO2 substrate. Optimized TFTs show mobility (μlin) between 20.0–25.0 cm2/(V.s). Material characterization revealed some degree of order compared to a truly amorphous film like a-IGZO but no grain boundaries or crystalline domains were observed. The a-ITZO films were integrated in coplanar SA TFT architecture on polyimide using hydrogen rich plasma (SiH4 based chemistry) as dopant for the source/drain (S/D) regions resulting in field-effect mobility (μFE) of 27.0 cm2/ (V.s), sub-threshold slope (SS−1) of 0.40 V/decade and ION /IOFF ratio of >108. The threshold voltage shifts of the TFTs under both positive and negative gate bias stress of 1MV/cm for 104 seconds were less than 1.5 V. We have also investigated the applicability of the SA a-ITZO TFTs in logic circuitry such as 19-stage ring-oscillators (ROs).

In this paper a charge sense amplifier (CSA) using a 5um In-Ga-Zn-O transistor technology on 15um thick flexible substrate is presented for readout of a 500dpi fingerprint sensor array targeting direct integration with active matrix organic light emitting displays (AMOLED). The CSA achieves a linear input range of 0.8V for rail to rail output at VDD=15V. The CSA comprises of a high gain and stable dual-ended output dual-stage amplifier. The n-type load is driven by a dual-stage buffer and start-up circuit to increase the performance and ensure stability. The amplifier operates down to 6V supply voltage. It achieves 31.17dB DC-gain, 140kHz gain-bandwidth, 53$°$ phase margin and dissipates 87uW at 15V. The footprint of the CSA is 0.3mm2and enables 1fps readout of 1 megapixel 500dpi sensor array. keywords: Thin film transistors,Logic gates,Resistance,amplifier,Dielectrics,igzo,Sensor arrays,Gain,metal-oxide,amoled,dual gate,csa,display,imager,in-panel ispartof: pages:194-197 ispartof: ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC) pages:194-197 ispartof: 44th European Solid State Circuits Conference (ESSCIRC) location:Dresden, Germany date:3 Sep - 6 Sep 2018 status: published

In this study, we have compared the performance of self-aligned a-IGZO thin-film transistors (TFTs) whereby the source/drain (S/D) region's conductivity enhanced in three different ways, that is, using SiNx interlayer plasma (hydrogen diffusion), using calcium (Ca as reducing metal) and using argon plasma (changing the atomic ratio). All these TFTs show comparable characteristics such as field-effect mobility (μFE) of over 10.0 cm2/(V.s), sub-threshold slope (SS-1) of 0.5 V/decade, and current ratio (ION/IOFF) over 108. However, under negative-bias-illumination-stress (NBIS), all these TFTs showed strong degradation. We attributed this NBIS stability issue to the exposed S/D regions and changes in the conductivity of S/D contact regions. The hydrogen plasma-treated TFTs showed the worst NBIS characteristics. This is linked to increased hydrogen diffusion from the S/D contact regions to the channel. In this study, we observed that the negative-bias-illumination-stress stabilities of self-aligned a-IGZO thin-film transistors are strongly dependent upon the source/drain (S/D) region's direct exposure to stress light. Among few different techniques for S/D conductivity enhancements such as metal reduction (Ca metal), Ar plamsa, and SiNx plasma (hydrogen diffusion), the SiNx plasma-treated thin-film transistors showed the worst negative-bias-illumination-stress suitabilities. This is linked to increased hydrogen diffusion from the S/D contact regions to the channel. cop. 2015 Society for Information Display.

We demonstrate the patterning of top emitting organic light emitting diodes (OLEDs) by direct-write Aerosol Jet printing in air from non-halogenated solvents. Indane was determined to be a suitable single solvent to dissolve the archetypal host poly(N-vinylcarbazole) and guest emitting dopants complexes for red, green, and blue OLEDs, and to print on both PEDOT:PSS and MoO3 transport layers. The Aerosol Jet deposition parameters were studied, including: atomization flow rate, exhaust flow rate, focusing sheath flow rate, nozzle-to-substrate distance, nozzle speed, and substrate temperature. A line width of 30 μm and thickness of 30 nm was achieved, resulting in RGB OLEDs fabricated side-by-side with a pixel density of 140 ppi.

We present a QVGA (320x240 with 3 sub-pixel) top-emitting AMOLED display with 250ppi resolution using a self-aligned (SA) IGZO TFT backplane on polyimide-foil with full barrier. The back plane process flow is based on a 7 layer photolithography process. The aperture ratio of the top-emitting OLEDs is approx. 80%. An integrated gate driver is shown that can be driven at operation speed equivalent to a 4k2k display at 100Hz

In this work we present the impact of buffer layers deposited by various techniques such as plasma enhanced chemical deposition (PECVD), physical vapor deposition (PVD) and atomic layer deposition (ALD) techniques on self-aligned (SA) top gate amorphous-Indium-Gallium-Zinc-Oxide (a-IGZO) TFT characteristics. Finally an optimized layer was integrated in TFT backplane on polyimide (PI) foil and a QQVGA AMOLED display is demonstrated.

We demonstrated self-aligned amorphous-Indium-Gallium-Zinc-Oxide (a-IGZO) thin-film transistors (TFTs) where the source–drain (S/D) regions were made conductive via chemical reduction of the a-IGZO via metallic calcium (Ca). Due to the higher chemical reactivity of Ca, the process can be operated at lower temperatures. The Ca process has the additional benefit of the reaction byproduct calcium oxide being removable through a water rinse step, thus simplifying the device integration. The Ca-reduced a-IGZO showed a sheet resistance (RSHEET) value of 0.7 kΩ/sq., with molybdenum as the S/D metal. The corresponding a-IGZO TFTs exhibited good electrical properties, such as a field-effect mobility (μFE) of 12.0 cm2/(V s), a subthreshold slope (SS−1) of 0.4 V/decade, and an on/off current ratio (ION/OFF) above 108. Cop. 2015 The Korean Information Display Society.

An integrated scan-line driver, driving half a QQVGA flexible AMOLED display using amorphous-IGZO backplane technology on foil, has been designed and measured. A pulse-width modulation technique has been implemented, enabling to drive the OLEDs with a duty cycle up to almost 100%. The digital driving method also results in a 40% static power reduction of the display. Dynamic logic and bootstrapping techniques enabled the use of clock frequencies up to 300 kHz in unipolar amorphous-IGZO technologies on foil.

In this work, we report on amorphous-Indium-Gallium-Zinc-Oxide (a-IGZO) thin-film transistor (TFT) with medium frequency physical vapor deposited (mf-PVD) etch-stop-layer (ESL). TFT with mf-PVD ESL show comparable characteristics such as fieldeffect mobility (μFE), sub-threshold slope (SS−1) and current ratio (ION/OFF) to the conventional plasma enhanced chemical vapor deposition (PECVD) ESL based TFT, however significant differences were observed in gate bias-stress stabilities. The TFTs with mf-PVD ESL showed lower threshold-voltage (VTH) shifts compared to TFTs with PECVD ESL when stressed under a gate field of +/−1 MV/cm for duration of 104 seconds in dark and light conditions. We associate the better bias-stress stability of the mf-PVD ESL based TFT to better passivating properties and the low hydrogen content of the mf-PVD layer compared to PECVD layer.

Amorphous Indium-Gallium-Zinc-Oxide (a-IGZO) Thin-Film Transistors (TFTs) integrated with Si based CMOS processes is an emerging technology in ultra-low power applications. ESD characteristics of a-IGZO TFTs with a Si substrate are studied and compared to their characteristics on traditional foil/glass substrate. The ESD performance is shown to be improved, thanks to improved thermal properties of the different buffer material. The layout dependency of ESD behaviors in Si substrate TFTs are investigated in order to meet the 1kV HBM ESD requirement. An on-chip ESD protection design with a gate-coupling TFT is proposed.

We present a qHD (960x540 with 3 sub-pixels) top-emitting AMOLED display with 340ppi resolution using a self-aligned (SA) IGZO TFT backplane on polyimide-foil with humidity barrier. The back plane process flow is based on a 7 layer photolithography process with a CD=4um. We implement a 2T1C pixel engine and use commercial source driver IC made for LTPS. By using IGZO TFT and leveraging the extremely low off-current, we can switch-off the power to the source and gate driver while maintaining the image un-changed for several minutes. We demonstrate that, depending on the image content, low-refresh operation yields reduction in power consumption of up to 50% compared to normal (continuous) operation. We show that with further increase in resolution, the power saving through state retention will be even more significant.

A process to make self-aligned top-gate amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) on polyimide foil is presented. The source/drain (S/D) region's parasitic resistance reduced during the SiN interlayer deposition step. The sheet resistivity of S/D region after exposure to SiN interlayer deposition decreased to 1.5 kΩ/□. TFTs show field-effect mobility of 12.0 cm2/(V.s), sub-threshold slope of 0.5 V/decade, and current ratio (I ON/OFF) of >107. The threshold voltage shifts of the TFTs were 0.5 V in positive (+1.0 MV/cm) bias direction and 1.5 V in negative (-1.0 MV/cm) bias direction after extended stressing time of 104 s. We achieve a stage-delay of ~19.6 ns at V-DD = 20 V measured in a 41-stage ring oscillator. A top-emitting quarter-quarter-video-graphics-array active-matrix organic light-emitting diode display with 85 ppi (pixels per inch) resolution has been realized using only five lithographic mask steps. For operation at 6 V supply voltage (V-DD), the brightness of the display exceeds 150 cd/m2. A process to make self-aligned top-gate amorphous indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) is presented. TFTs show field-effect mobility of 12.0 cm2/(V.s), sub-threshold slope of 0.5 V/decade, and current ratio (I ON/OFF) of over 107. In applications, a 41-stage ring oscillator with a stage-delay of ~19.6 ns (at V-DD = 20 V) and a top-emitting quarter-quarter-video-graphics-array (QQVGA) active-matrix organic light-emitting diode (AMOLED) display with 85 ppi (pixels per inch) resolution using five lithographic mask steps have been realized on a polyimide foil. Copyright 2015 Society for Information Display.

We report on the fabrication of organic photodetectors (OPD) based on isolated islands of P3HT:PCBM. Pattern transfer to the active material was done with photolithography based on non-fluorinated solvents and the excessive organic semiconductor was removed with oxygen plasma reactive ion etching. The photoresist system used was found to be benign to the P3HT:PCBM layer as confirmed by absorption, thickness and roughness measurements. Current–voltage characteristics and external quantum efficiency (EQE) remained unchanged after the patterning process. It was demonstrated that it is possible to photolithographically pattern isolated islands with 200 μm edge length with the same dark current density ( −5 A/cm 2 at −2 V bias voltage) and photocurrent density (>5 × 10 −3 A/cm 2 at −2 V). Furthermore, concerning the solar cell performance, the patterned, small-area devices showed power conversion efficiency of 2.1% and fill-factor of 60%. Dark current was observed to depend on the size of the remaining semiconductor island, which was demonstrated on OPDs with diameter of 50 μm. The presented results show the feasibility of fabrication of isolated devices based on organic semiconductors patterned with non-fluorinated photolithography.