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In this paper, a semiself-protection scheme is proposed and developed for gigahertz output electrostatic-discharge (ESD) protection. The output transistor acts as a trigger device to trigger the ESD protection device, and then, it is turned off when the ESD protection device turns on. Thus, the capacitance of a gigahertz high-frequency output pad can be minimized because this scheme is without any additional trigger device or any passive component. [ABSTRACT FROM AUTHOR]

A novel transient voltage suppressor (TVS) that features ultralow capacitance is proposed. This structure is able to reduce the input capacitance by 21.1%, and is designed to protect against electrostatic discharge (ESD) issues for high-speed ports. The device is also able to withstand IEC 61000-4-2 contact testing at ±14 kV and transmission line pulse (TLP) testing at 20 A. The device is fabricated using a typical planar Bipolar-CMOS-DMOS (BCD) process. By slotting the doping well to decrease the concentration of diodes, a TVS with an ultralow Cj is obtained without the need to add to the process procedures or without damaging the ESD capability. [ABSTRACT FROM PUBLISHER]

In this paper, a scheme for how to utilize VFTLP (very fast transmission line pulse) data to design an input buffer circuit for CDM (charged-device model) ESD protection is reported. The impedance of the ESD device under VFTLP stress is nearly 120 Ω at the beginning of turn-on transient, and decreases with time toward 10 Ω prior to the voltage falling below 0 V. In this work, the fact that the dynamic-characteristic impedance of the ESD device under VFTLP testing is independent of the stress current is found. Since both VFTLP zapping and the CDM are nanosecond events, the dynamic-characteristic impedance of the ESD device can be used to evaluate the CDM threshold voltage of the input buffer based on the equivalent and simplified RLC circuit. [ABSTRACT FROM AUTHOR]

The influence of the body layout on the charged device model (CDM) failure site and the robustness of the input buffer is explored. The failure analysis results confirm that the gate oxide is damaged. The failure site can be moved from the region above the channel to the overlap region between the source and the gate once the body layout is cut from a ring into a small segment, providing direct evidence demonstrating that the CDM current flows through the gate oxide via the body and the source of the transistor, since both connect to the Vss bus line. Otherwise, changing the body layout of the input buffer transistor does not vary the failure location. [ABSTRACT FROM AUTHOR]

A simple scheme is proposed to increase the hold voltage and not change the original trigger voltage of a silicon‐controlled rectifier (SCR) to enhance its latch‐up immunity without changing the device dimensions. It is found that using the lightly doped P‐diffusion instead of the highly doped P+ diffusion as the P emitter of the anode can increase the hold voltage of an SCR. [ABSTRACT FROM AUTHOR]