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The effects of the Si/W ratio on chemical vapor deposition (CVD)-WSi(sub x) metal gate MOSFET performance were reported. The findings suggest that both mobility and reliability of metal gate nMOSFETs are improved by higher Si/W ratio of CVD-WSi(sub x) films.

The impact of new flash lamp annealing (FLA) technology, which both minimizes diffusion to yield a shallow junction and realizes low sheet resistivity, is investigated based on MOSFET fabrication and computer simulations. Productivity can be improved since FLA makes it possible to employ higher acceleration energy ion implantation and higher throughput. The MOSFET performance can be improved and its deviation suppressed by using FLA. In analyzing MOSFETs with gate length (L) of 20 nm by computer simulations, it was clarified that in contrast to spike annealing, the shallow junction realized by applying FLA to pMOSFET fabrication enabled the suppression of |[I.sub.off]| with a low channel surface dopant concentration. This provided a higher mobility value and a higher drive current. FLA is promising for improving the performance and productivity of sub-30-nm gate-length MOSFETs. Index Terms--Annealing, MOSFET, performance, shallow junction.

Flash lamp annealing (FLA) technology is proposed as a new method of activating implanted impurities. By optimizing FLA and implantation conditions, junction depth (Xj) at the concentration of 1 x [10.sup.18] c[m.sup.-3] and the sheet resistance of 13 nm and 700 [ohm]/s. for As and 14 nm and 770 [ohm]/sq for B[F.sub.2] with junction leakage lower than 1 x [10.sup.-16] A//[micro][m.sup.2] at 1.5 V were successfully obtained without wafer slip and warpage problems. Index Terms--Activation, crack, flash !amp annealing (FLA), junction leakage, low resistance, MOSFETs, preamorphization, slip, stress, ultrashallow junction.

A new type of ion implanter developed for an agile fab can eliminate the processes concerned with photoresist lithography from the ion implantation process. This new ion implantation technology can reduce the raw process time, footprint, and the cost of ownership to less than one-half that of conventional ion implantation technology. The authors are making further developments on this ion implanter and evaluating technical issues related to ion implantation. This technique is suitable for manufacturing submicro node IC devices. Based on the results of evaluating the prototype machine, we will produce the next [beta]-machine. Index Terms--Implant, lithography, stencil, stencil mask Lithographic Ion Implanter (SLIM).

SiH-free silicon nitride (SiN) films formed by tetrachlorosilane (TCS) and ammonia are applied effectively to suppress the SiN-induced boron penetration. Boron-doped polysilicon gated capacitors with several kinds of thick silicon nitride (SiN) films are used in the SiN-induced boron penetration.

Ion implantation process should be important to development or manufacturing of semiconductor devices, because ion implantation conditions directly influence some characteristics of semiconductor devices. Recently, we have developed a new implantation technology, stencil mask ion implantation technology (SMIT). In the SMIT system, a stencil mask acts like a resist mask, and ions passing through the hole of the mask are implanted into selected regions of Si substrate chip by chip. Use of SMIT has several advantages, notably lower manufacturing cost and shorter process time than in the case of conventional process, because no photolithography process (including deposition and stripping of resist) is required. We have already demonstrated an application of SMIT to transistor fabrication, using various implanted dose conditions for the same wafer. Threshold voltage values can be controlled as effectively by implanted doses as they can by conventional implantation, and the dose dependence of the threshold voltage could be obtained from one wafer to which various implantation conditions are applied. Using SMIT, implantation condition can be changed chip by chip without additional processes. This flexibility of implantation conditions is another advantage of SMIT. In this paper, we propose stencil mask ion implantation technology and show some fundamental results obtained by applying SMIT. Index Terms--Agile fab, Damascene metal gate, ion implantation, MOSFET, SMIT, stencil mask.

A dynamic threshold-voltage damascene metal gate MOSFET technology for very low voltage operation (under 0.7 V) is proposed. In this technology, the metal gate is formed by the damascene gate process and directly connected to the well region.

Metal gate work function deviation (crystal orientation deviation) causes threshold voltage deviation in damascene metal gate transistors. If TiN work function (crystal orientation) is controlled by means of a chemical vapor deposition (CVD) technique, threshold voltage deviation of surface channel damascene metal gate transistors is significantly improved and is less than that for conventional polysilicon gate transistors.

A low-resistivity poly-metal gate structure W/WSiN/poly-Si shows thermal stability even after annealing and also achieves a sheet resistivity as low as 1.5 ohm. Annealing gives rise to a uniform WSiN layer between the W and poly-Si in addition to the removal of the WN(sub x) layer. Rutherford backscattering spectrometry shows no silicidation, and an equivalent circuit simulation reveals the negligible effect of the contact resistivity of W and poly-Si on the gate RC delay time. The W/WSiN/poly-Si gate structure may prove extremely useful in sub-quarter-micron MOSFET's.

Deep sub-micrometer devices, such as logic CMOS ULSI, are constructed using a new technology known as mono-silicidation technology. The device made using this technology has shown better transistor characteristics and propagation delay time than those of titanium salicide. This is because, polysilicon and single-silicon layers have lower contact resistance and sheet resistance. The details of use of nickel-monosilicide technology in making deep sub-micron CMOS are given.

The numerical investigation of the interfacial energy of interconnect metal/barrier-metal interfaces in ultralarge-scale integrations is performed by the assumption of a simple additive interaction potential inside a rigid lattice approximation. The investigation indicates that the Al occurs in an (III) preferred orientation on the Ti plane, but the Cu did not exhibit any preference for orientation. The Al(III) also exhibits a strong epitaxial growth.

A novel method of filling contact holes which occur during fabrication of deep-submicrometer devices is presented. It involves the formation of a polysilicon plug with a titanium nitride stopper via selective nickel silicidation of polysilicon. The resulting contact plug exhibits low contact resistance values equal to those ofan unplugged contact hole. It may also be used to fill two holes of varying depths simultaneously.