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We have fabricated and tested the performance of sub-50nm gate nMOSFETs to assess their suitability for mixed signal applications in the super high frequency (SHF) band, i.e. 3-30GHz. For a 30nm×40 μm×2 device, we found f(T) =465GHz at V(ds)=2V, V(g)=0.67V, which is the highest cut-off frequency reported for a MOSFET produced on bulk silicon substrate so far. However, our measurements of f(max) and noise figure indicate that parasitics impose limitations on SHF operation. We also present a high-frequency ac model appropriate to sub-50nm gate length nanotransistors, which incorporates the effects of the parasitics. The model accurately accounts for measurements of the S and Y parameters in the frequency range from 1 to 50GHz.

An ultra high-density hybrid integration for micro-electromechanical system (MEMS) mirror chips with several thousand inputs/outputs has been developed. The integration scheme involving flip-chip assembly provides electrical signal to individual mirrors, which is compatible with postprocessing steps of selectively removing the silicon handle and releasing the MEMS mirrors. For the first time, to our knowledge, solder deposition and flip-chip bonding of 3-mum bumps on 5-mum centers of a large array has been demonstrated.

Fabrication of devices and circuits on silicon wafers creates patterns in optical properties, particularly the thermal emissivity and absorptivity, that lead to temperature nonuniformity during rapid thermal processing (RTP) by infrared heating methods. The work reported in this paper compares the effect of emissivity test patterns on wafers heated by two RTP methods: (1) a steadystate furnace or (2) arrays of incandescent lamps. Method I was found to yield reduced temperature variability, attributable to smaller temperature differences between the wafer and heat source. The temperature was determined by monitoring test processes involving either the device side or the reverse side of the wafer. These include electrical activiation of implanted dopants after rapid thermal annealing (RTA) or growth of oxide films by rapid thermal oxidation (RTO). Temperature variation data are compared with a model of radiant heating of patterned wafers in RTP systems.

A new approach is presented for fabricating monolithic crystalline silicon tilting-mirror microoptoelectromechanical systems (MOEMS) devices. The activation electrodes, etched from a thick silicon layer deposited over insulating oxide onto the top surface of a silicon-on-insulator (SOI) wafer, are displaced from the mirrors and interact with these tilting elements via electrostatic fringing fields. In contrast to the more usual parallel-plate activation, the rotation angle saturates at high voltages. This paper discusses concept, design, and processing, and also compares modeling and measured performance of a specific 9/spl deg/ tilt range device array.

A study was undertaken to determine the efficacy of various underlayers for the nucleation and growth of atomic layer deposited HfO2 films. These were compared to films grown on hydrogen terminated Si. The use of a chemical oxide underlayer results in almost no barrier to film nucleation, enables linear and predictable growth at constant film density, and the most two-dimensionally continuous HfO2 films. The ease of nucleation is due to the large concentration of OH groups in the hydrous, chemical oxide. HfO2 grows on chemical oxide at a coverage rate of about 14% of a monolayer per cycle, and films are about 90% of the theoretical density of crystalline HfO2. Growth on hydrogen terminated Si is characterized by a large barrier to nucleation and growth, resulting in three-dimensional, rough, and nonlinear growth. Thermal oxide/oxynitride underlayers result in a small nucleation barrier, and nonlinear growth at low HfO2 coverages. The use of chemical oxide underlayers clearly results in the best HfO2 layers. Further, the potential to minimize the chemical oxide thickness provides an important research opportunity for high-κ gate dielectric scaling below 1.0 nm effective oxide thickness.

We describe the reliability projection methods currently used and show that 1.6 nm oxides are sufficiently reliable even if soft breakdown is considered the point of failure. We also explore the possibility of using oxides after soft breakdown.

The exponential growth of the silicon industry can be attributed to that fact that silicon has a native oxide that is silicon dioxide. With SiO 2 soon approaching its fundamental limit, we must find an alternate to SiO 2 or a new switch to replace MOSFETs. In this paper we focus on the leading alternate gate dielectrics. We first discuss the selection criteria for alternate gate dielectrics and why it is important to have an amorphous gate dielectric. SiO 2 and aluminum oxide remain amorphous at very high temperatures. For dielectrics with K >15 and gate power 2 , it may be necessary to stabilize the amorphous phase of metal oxides by adding Al or Si to the oxide, thus forming multi-component dielectrics such as aluminates. We then benchmark aluminates with aluminum oxide and silicon dioxide.

In spite of its many attributes such as nativity to silicon, low interfacial defect density, high melting point, large energy gap, high resistivity, and good dielectric strength, SiO 2 suffers from one disadvantage, low dielectric constant (K=3.9). Thus, ultrathin SiO 2 gate dielectric layers are required to generate the high capacitance and drive current required of sub-50 nm transistors. The silicon industry roadmap dictates 4 nm SiO 2 gate dielectrics for 0.25 μm technology today, and calls for 2 thickness for 0.05 μm technology in 2012. SiO 2 layers in this thickness range may suffer from boron penetration, reduced drive current, reliability degradation, and high gate leakage current. We will argue that none of these problems are limitations for thicknesses greater than about 1.3 nm. Below that thickness, the fundamental problems of high tunneling current and reduced current drive will prevent further scaling, unless alternate gate dielectrics are introduced.

In this paper we report experiments and simulations on thin oxide (1.5–3 nm) MOS devices, showing that native traps can play a dominant role in the tunneling characteristics of such oxides. The number of traps, and thus their role on the tunneling current, can be minimized by careful and simple processing: in this case traps affect the tunneling current in relatively thick oxides while their role vanishes at oxide thicknesses of 2 nm and below.

A nanopore is an analytical tool with single molecule sensitivity. For detection, a nanopore relies on the electrical signal that develops when a molecule translocates through it. However, the detection sensitivity can be adversely affected by noise and the frequency response. Here, we report measurements of the frequency and noise performance of nanopores

Thin SiO2 layers were exposed to an HBr/O2 plasma for a variety of short periods, reproducing the over-etching process after polycrystalline Si gate electrodes have been etched and the gate oxide layer is exposed. Samples were transferred under vacuum to an x-ray photoelectron spectrometer for analysis. After relatively thick (>60 A) films were exposed to a 10% O2/HBr plasma at an average ion energy of ∼150 eV, the near-surface region becomes brominated, and the thickness of the film decreases, indicating an etching rate of ∼1–2 A/s. When the starting film thickness is between 10 and 20 A, however, exposure to the plasma results in an increases in the thickness of the film, and is enhanced with the increasing addition of oxygen to the feed gas. At mean ion energies of 40 or 150 eV, the transition from etching to deposition occurs at oxygen additions of ∼1% or ∼8%, respectively. The increase in SiO2 thickness is ascribed mainly to oxidation of the Si at the oxide-substrate interface, and not to deposition ...

We have fabricated and tested sub-50nm gate length nMOSFETs with fT up to 290GHz to assess their suitability for mixed signal applications in the super high frequency (SHF) band, i.e. 3-30GHz. We have also developed an accurate, high frequency (1 -50GHz) model suitable for integration with digital CMOS

In this letter, we report on the reaction between Si and N2 in the temperature range of 760–1050 °C, in a rapid thermal processing chamber. Gas phase impurities such as H2O, O2, and H2, which can outgas from the cold walls of the chamber, mediate the Si/N2 reaction, resulting in the formation of SiOxNy. The oxynitridation can be explained by equilibrium chemical thermodynamics, in contrast to the case of oxynitridation using N2O or NO, where the nitrogen is incorporated under nonequilibrium conditions. Using nuclear reaction analysis, we have measured nitrogen contents as high as 2.5×1015 N/cm2 (the equivalent of more than 3 monolayers) in these new dielectrics. They can be reoxidized to form ultrathin (2 to 3 nm) dielectrics.

We combine a PLC and free-space optics for a compact Fourier-plane pulse shaper with low polarization dependencies. A micromirror array with piston motion provides phase modulation. The shaped electric field is extracted from a recorded spectrogram of the synthesized waveform.

This paper discusses a significant improvement of the SOI process that can be implemented in various manners and that remedies many problems of earlier fabrication schemes. In particular the new MOEMS structures are monolithic, do not exhibit rotational snapdown, have electrical shielding between channels, and have activation voltages less than or comparable to parallel plate devices. The approach is discussed in terms of an application requiring a linear array of closely-spaced cantilever mirrors.

We demonstrate for the first time that chemical oxide underlayers /spl sim/5 /spl Aring/ thick provide improved growth and flatband voltage control of ALD HfO/sub 2/ films compared to thermal oxides. Optimized annealing conditions are shown to greatly reduce both fixed charge and interfacial oxide growth in the high-/spl kappa/ stacks. Extremely small flatband voltage shifts of

We demonstrate that reliability projections can be improved significantly if oxide thickness uniformity is improved. Our results include a Weibull slope of 1.38 for an extremely uniform 1.6 nm oxide, and also a steeper voltage scaling factor than has been used in the past. Transistors with 50 nm gate-length and /spl sim/1.5 nm oxides exhibit soft breakdown, suggesting that it may be possible to relax current reliability specifications.

We have fabricated and demonstrated a new device called the Vertical Replacement-Gate (VRG) MOSFET. This is the first MOSFET ever built that combines (1) a gate length controlled precisely through a deposited film thickness, independently of lithography and etch, and (2) a high-quality gate oxide grown on a single-crystal Si channel. In addition to this unique combination, the VRG-MOSFET includes a self-aligned S/D formed by solid source diffusion (SSD) and small parasitic overlap, junction, and S/D capacitances. The drive current per /spl mu/m of coded width is significantly higher than that of advanced planar MOSFETs because each rectangular device pillar (with a thickness of minimum lithographic dimension) contains two MOSFETs driving in parallel. All of this is achieved using current manufacturing methods, materials, and tools, and competitive devices with 50-nm gate lengths (L/sub G/) have been demonstrated without advanced lithography.

We have achieved extremely high drive current performance and ballistic (T>0.8) transport using ultra-thin (

High-κ dielectrics based the oxide of Al were prepared by atomic layer deposition (ALD) on 200-mm p-type Si wafers. Films were deposited directly on clean Si or on 0.5-nm underlayers of rapid thermal oxide or oxynitrides grown in O2 and/or NO ambients. The purpose of the underlayer films is to provide a barrier for atomic diffusion from the crystal Si to the high-κ dielectric film. Deposited Al-oxide films varied in thickness from 2 to 6 nm. Post deposition anneals were used to stabilize the ALD oxides. Equivalent SiO2-oxide thickness varied from 1.0 to 3.5 nm. In situ P-doped amorphous-Si 160 nm films were deposited over the oxides to prepare heavily doped n-type gate electrodes in MOS structures. Samples were rapid thermal annealed in N2 ambient at 800°C for 30 s, or spike annealed at 950, 1000, and 1050°C (nominally zero time at peak temperature). Flat band voltages, VFB were determined from C-V measurements on dot patterns. The 800°C anneals were used as a baseline, at which the poly-Si electrodes are crystallized and acquire electrical activation while subjecting the high-κ dielectrics to a low thermal budget. Positive shifts in VFB were observed, relative to a pure SiO2 control, ranging from 0.2 to 0.8 V. Spike annealing reduces the VFB shift for ALD films deposited over underlayer films. The VFB shift and the changes with annealing temperature show systematic dependence on the nitridation of the underlayer.

We study breakdown in high-quality 2-7 nm gate dielectrics, and find that soft breakdown becomes more likely for thinner oxides and for oxides stressed at lower voltages. For 2 nm oxides, an increase in gate noise is the only precise indication of soft breakdown. For many applications, devices should remain functional with the level of gate noise we have observed, after soft breakdown.

We have investigated a new class of high K gate dielectric materials, Si-doped aluminates. These dielectrics, with TiN gates, can withstand high temperature CMOS processing and therefore do not require replacement gate technology. In this paper we focus on Si-doped zirconium aluminate (Zr-Al-Si-O), with K/spl sim/20. With the TiN gate stack subjected to the standard CMOS thermal budget, we have scaled this dielectric to t/sub eq//spl sim/1.2 nm with leakage current 15) may be viable alternate gate dielectrics.

We present the first p-channel Vertical Replacement-Gate (VRG) MOSFETs. Like the VRG-nMOSFETs demonstrated last year, these devices show promise as a successor to planar MOSFETs for highly-scaled ULSI. Our pMOSFETs retain the key features of the nMOSFETs and add channel doping by ion implantation and raised source/drain extensions (SDEs). We have significantly improved the core VRG process to provide high-performance devices with gate lengths of 100 nm and below. Since both sides of the device pillar drive in parallel, the drive current per /spl mu/m of coded width can far exceed that of planar MOSFETs. Our 100 nm VRG-pMOSFETs with t/sub ox/=25 /spl Aring/ drive 615 /spl mu/A//spl mu/m at 1.5 V with I/sub OFF/=8 nA//spl mu/m-80% more drive than specified in the 1999 ITRS Roadmap at the same I/sub OFF/. We demonstrate 50 nm VRG-pMOSFETs with t/sub ox/=25 /spl Aring/ that approach the 1.0 V roadmap target of I/sub ON/=350 /spl mu/A//spl mu/m at I/sub OFF/=20 nA//spl mu/m without the need for a hyperthin (

We present the SALVO CMOS process, first device data and simulation study with the following features: (1) self-aligned local channel implants for SCE reduction; (2) sub-50 nm fabrication using only current production tools; (3) replacement gate with dual-polysilicon for low V/sub T/; (4) low aspect-ratio gates with CD insensitive to lithography and etch profile variability. The first demonstration of SALVO process shows it is a viable candidate for future ULSI CMOS production, in view of its versatility, controllability and compatibility.

We have integrated HfO/sub 2/ and Al/sub 2/O/sub 3/ gate dielectrics grown by atomic layer chemical vapor deposition (ALD) with poly-Si gate electrodes in the vertical replacement-gate (VRG) MOSFET geometry. These transistors are among the first reported with ALD HfO/sub 2/ gate dielectrics, and have HfO/sub 2/ target equivalent oxide thicknesses (tEOT's) down to 13 /spl Aring/. The poly-crystalline HfO/sub 2/ films in these VRG nMOSFETs exhibit extremely low gate leakage (GL) current densities of J/sub G/ /spl sim/ 10/sup -7/ A/cm/sup 2/ at V/sub G/-V/sub T,Long/ = 0.6 V for 15 /spl Aring/ tEOT devices. This indicates that amorphous gate dielectrics may not be necessary to meet GL requirements. HfO/sub 2/ devices with 50 nm gate length L/sub G/ exhibit drive currents [normalized by the coded width W/sub C/] of 490 /spl mu/A//spl mu/m for 1 V operation (overdrive V/sub GS/-V/sub T/ = 0.6 V) with good short-channel performance. These results demonstrate that ALD is compatible with the demanding VRG geometry, thereby illustrating that it should be well-suited to essentially any novel device structure built with Si-compatible materials.

Ultrathin ( 1200°C) and therefore too high a thermal budget. The use of NH3 as a nitridation agent, especially to nitridize the Si/SiO2 interface [8-11], resulted in excessive H incorporation and the potential for degradation of dielectric reliability. More recently, oxynitrides have been grown in either N2O [12,13] or NO [14,15]. These dielectrics contain a small but significant amount of nitrogen [16], almost invariably concentrated near the Si/SiO2 interface [17].

By using a combination of smooth epi substrates (0.7 Å rms roughness), in-situ UV/Cl2 processing, and rapid thermal oxidation, highly reliable ultrathin gate oxides were produced with ≤ 1.0 Å rms interface roughness.

Spatial light modulators (SLMs) designed to replace photomasks for optical lithography have been designed, fabricated, and tested. These microelectromechanical devices are fabricated with alternating polycrystalline Si and sacrificial SiO2 layers that are patterned by a 193nm wavelength scanner to dimensions as small as 150nm. Aerial image simulations were used to define the mechanical requirements of the devices. Piston motion of electrically actuated devices was measured with an optical profilometer. The measurements were fit to a simple equation to within 1nm precision, which is adequate for defining 50nm features lithographically. Transient response measurements show that one version of the SLM responds to actuation as quickly as 20μs, fast enough for current 193nm wavelength excimer laser sources.

We report on progress toward scaling both N-metal–oxide–semiconductor (MOS) and P-metal–oxide–semiconductor MOS transistors to a gate length of 30 nm. We describe lithography and pattern transfer results that are suitable to meet this goal. Scanning capacitance microscopy is used to determine the effective channel lengths and source drain junction depths on cross-sectioned devices to optimize the fabrication process. We present interim electrical results obtained for high performance, down to Lg=57 nm, N-MOS and P-MOS transistors made using this process. We have also used a device simulation program to predict subthreshold current for N-MOS transistors with gate lengths from 40 to 26 nm. The simulation provides insights into the effects of critical dimension control and edge roughness on leakage current, and has implications for extending large scale integration of MOS technology beyond 50 nm.

Results are described for a gate level technology module developed to produce metal–oxide–semiconductor transistors with physical gate lengths of 70 nm and below. Lithography is performed by direct write e-beam lithography (EBL) using a thermal field-emission EBL system in SAL 601 resist. Critical dimension (CD) control, as measured by several methods, is found to depend not only on dose control but also on writing parameters such as pixel spacing. The pattern transfer using a silicon dioxide hard mask is shown to exhibit a trade-off between anisotropy and selectivity. Transmission electron microscopy cross sections reveal that two atomic layers are removed even when the gate oxide stopping layer is completely intact. We report results for gate lengths down to 60 nm with edge roughness on the order of 5 nm, within the acceptable limits for threshold requirements, while stopping the etch process on oxides as thin as 1.2 nm.

The narrowest feature of an integrated circuit is the silicon dioxide gate dielectric (3–5 nm). The viability of future CMOS technology is contingent upon thinning the oxide further to improve drive performance, while maintaining reliability. Practical limitations due to direct tunneling through the gate oxide may preclude the use of silicon dioxide as the gate dielectric for thicknesses less than 1.3 nm, however.

This paper reports experimental data and simulations of low-voltage tunneling in ultrathin oxide MOS devices. When the substrate is very heavily doped, a thermionic barrier is present that opposes the direct tunneling of gate electrons when the applied gate voltage is between 0 V and the flatband voltage. In such conditions, we show that the measured gate current cannot be explained by direct tunneling, but features an additional, dominant component. The temperature dependence of this extra component indicates that it is due to gate electrons tunneling into the anode interface states. By comparing measurements and simulations, it is possible to exploit this extra current to estimate the interface state density within the silicon band gap. In addition, it is shown that this tunneling current component is very sensitive to electrical stress and allows a clear detection of oxide wear out even for stress at very low field. Therefore, it can be adopted as monitor of oxide degradation in ultrathin oxides where the traditional stress induced leakage current due to bulk-oxide traps is not detectable.