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The switching behavior of semiconductor devices responds to charge/discharge phenomenon of terminal capacitance in the device. The differential capacitance in a semiconductor device varies with the applied voltage in accordance with the depleted region thickness. This study develops a C--V characterization system for high-voltage power transistors (e.g., MOSFET, insulated gate bipolar transistor, and JFET), which realizes the selective measurement of a specified capacitance from among several capacitances integrated in one device. Three capacitances between terminals are evaluated to specify device characteristics--the capacitance for gate--source, gate--drain, and drain--source. The input, output, and reverse transfer capacitance are also evaluated to assess the switching behavior of the power transistor in the circuit. Thus, this paper discusses the five specifications of a C--V characterization system and its measurement results. Moreover, the developed C--V characterization system enables measurement of the transistor capacitances from its blocking condition to the conducting condition with a varying gate bias voltage. The measured C--V characteristics show intricate changes in the low-bias-voltage region, which reflect the device structure. The monotonic capacitance change in the high-voltage region is attributable to the expansion of the depletion region in the drift region. These results help to understand the dynamic behavior of high-power devices during switching operation. Index Terms--C--V characteristics, high-voltage power device, terminal capacitance, voltage dependency.

The gate critical dimension (CD) variation of ultra-large-scale integrated circuit (ULSI) devices should be reduced to improve the production yield. An examination of the formulation of a gate-CD model for the transistor area, including the static random access memory (SRAM), was conducted taking the topographical and layout effects into account. It was found that the formulation of a gate CD for transistor areas with a root-mean-square error (RMSE) of less than 1 nm was efficient. The coefficients of the shallow-trench-isolation (STI) step height and polycrystalline-silicon (poly-Si) thickness were found to be inversely proportional to the distance between the gate electrodes. It was found that this dependence is related to the reactive-ion-etching (RIE) lag in the etching process. Index Terms--Gate electrode, MOS devices, plasma etching, process control, shallow trench isolation, SRAM.

The effects of random variations during the manufacturing process on devices can be simulated as a variation of transistor parameters. Device degradation, due to temperature or voltage stress, causes a shift of device parameters, for example threshold voltage [V.sub.th], which can also be modeled as a degradation of transistor parameters. Therefore, in order to design circuits, which are robust and reliable, analysis and optimization of their sensitivity to variations in model parameters is important. Furthermore, constraints on the operating regions and voltage differences of transistors are used in order to keep operating points stable over a large temperature range. In this work, using two circuits for automotive applications and current process development kits (PDK), we show how design centering software can be used to consider both sensitivity reduction towards model parameter variation and constraints to control safe operating areas (SOA). Beyond that a comparison of the constraint matrix method with two established methods of SOA checking is done. Index Terms--Circuit reliability, circuit optimization, hot carriers, analog circuits.

We propose an 8 by 8 dynamic true-single-phase-clock (TSPC) circuit based on low-temperature polycrystalline silicon (LTPS) technology to perform high speed dynamic memory cell. The proposed method allows the memory access rate to reach 25 MHz, in contrast to the traditional LTPS memory, with static circuit design, that operates at a low frequency of only about 6 MHZ. The 8 by 8 dynamic TSPC LTPS memory cell can be applied in high speed circuits. The experimental results show that the proposed 8 by 8 dynamic TSPC LTPS memory cell, operating at 25 MHz, can achieve high speed effectively. We believe it will be the most suitable technology to realize high speed memory for system on a panel (SOP) together with IC chip technology. Index Terms--Clocked storage elements (CSE), low-temperature poly-silicon (LTPS), system on panel (SOP), true-single-phase-clock (TSPC).

In this paper, low-temperature poly-silicon (LTPS) thin-film transistors (TFT) are used for LTPS memory on glass substrates. System on panel (SOP), combined with memory, controller, and driver circuits on a glass substrate, will be the most suitable applications for TFT panels in the near future. Recently, the low-temperature poly-silicon thin-film transistors prepared on glass substrates have been studied extensively. Compared to amorphous silicon TFT (a-Si TFT), the LTPS TFT has electron mobility that is several orders of magnitude higher. Therefore, it is possible to integrate the LTPS TFT with peripheral circuits on the same glass substrate for advanced flat panel display applications. We use LTPS technology to achieve a high-speed memory cell that adopts a true single phase clocking (TSPC) circuit. Finally, the experimental results show that the high-speed TSPC LTPS-TFT memory operates at 24 MHz and accomplishes the SOP design target. Index Terms--Amorphous silicon (a-Si), low-temperature poly-silicon (LTPS), system on panel (SOP), thin-film transistors (TFT).

In this paper, the effects of forward body bias (FBB) on high-frequency noise performance in deep-submicrometer CMOS transistors are presented. It was observed that noise parameters [NF.sub.min] and [R.sub.n] in both N and PMOS increased significantly under FBB. FBB may appear as a great concern in the low noise circuit design. This is in contrast with the improvement of other device parameters induced by FBB, such as reduction of threshold voltage ([V.sub.TH]), and increase in speed. The underlying physical mechanisms for the noise increase in N and PMOS were found to be different. In NMOS, high-frequency noise behavior can be well explained by a combinational effect between substrate resistance noise and nonequilibrium channel noise. However, increase of noise in PMOS was found to be mainly due to the substrate resistance noise. The contribution of nonequilibrium channel noise is trivial. Index Terms--Body bias, channel noise, high-frequency noise, MOSFETs, noise modeling, nonequilibrinm channel noise, RF noise, semiconductor device noise, substrate resistance noise.

Backscatter lidar detection systems have been designed and integrated at NASA Langley Research Center using IR heterojunction phototransistors. The design focused on maximizing the system signal-to-noise ratio rather than noise minimization. The detection systems have been validated using the Raman-shifted eye-safe aerosol lidar (REAL) at the National Center for Atmospheric Research. Incorporating such devices introduces some systematic effects in the form of blurring to the backscattered signals. Characterization of the detection system transfer function aided in recovering such effects by deconvolution. The transfer function was obtained by measuring and fitting the system impulse response using single-pole approximation. An iterative deconvolution algorithm was implemented in order to recover the system resolution, while maintaining high signal-to-noise ratio. Results indicated a full recovery of the lidar signal, with resolution matching avalanche photodiodes. Application of such a technique to atmospheric boundary and cloud layers data restores the range resolution, up to 60 m, and overcomes the blurring effects. OCIS codes: 280.3640, 010.0280, 290.1090, 250.0040, 100.1830.

A novel linear tunable transconductor based on a combination of linearization techniques is presented. The input signal is transferred to the V-I conversion element by means of a high-speed feedback loop. Then, the linear V-I conversion is accomplished using quasi-floating-gate MOS transistors biased in the triode region. Finally, the absence of current mirrors in the signal path provides low sensitivity to transistor mismatch and reduces the harmonic distortion. The operational transconductance amplifier (OTA) was fabricated in a 0.5-[micro]m CMOS technology with a single 3.3-V supply voltage. Experimental results show a total harmonic distortion of -78 dB at 1 MHz with 1-[V.sub.PP] input signal. High linearity of the OTA is obtained over a two octave tuning range with only 1.25-mW power consumption. Index Terms--Analog CMOS circuits, flipped voltage follower (FVF), linear circuits, low-power and low-voltage CMOS circuits, operational transconductance amplifier (OTA), quasi-floating-gate transistors.

An implementation of a compact and programmable 10-bits floating-gate digital-to-analog converter (FGDAC) is described. In this implementation, nonvolatile floating-gate voltage references (epots) are employed together with unity-size capacitors to obtain the binary-weighted scale factors. The FGDAC, fabricated in a 0.5-[micro]m CMOS process, occupies 0.208 [mm.sup.2] of die area. The stored epot voltages drift [10.sup.-3]% over the period of ten years at 25[degrees]C and exhibit temperature coefficients of less than 37 ppm/[degrees]C. With the proposed design, INL and DNL values less than [+ or -]0.5LSB (LSB = 3 mV) and SFDR around 63 dB are obtained. Index Terms--Binary weighted, digital-to-analog converter (DAC), epot, floating gate (FG), programmable, transistor, trimming.

This paper presents an efficient reverse converter for transforming the redundant binary (RB) representation into two's complement form. The hierarchical expansion of the carry equation for the reverse conversion algorithm creates a regular multilevel structure, from which a high-speed hybrid carry-lookahead/ carry-select (CLA/CSL) architecture is proposed to fully exploit the redundancy of RB encoding for VLSI efficient implementation. The optimally designed CSL sections interleaved evenly in the mixed-radix CLA network to boost the performance of the re. verse converter well above those designed based on a homogeneous type of carry propagation adder. The logical effort characterization captures the effect of circuit's fan-in, fan-out and transistor sizing on performance, and the evaluation shows that our proposed architecture leads to the fastest design. A 64-bit transistor-level circuit implementation of our proposed reverse converter and that of its most competitive contender were simulated to validate the logical effort delay model. The pre- and post-layout HSPICE simulation results reveal that our new converter expends at least two times less energy (power-delay product) than the competitor circuit and is capable of completing a 64-bit conversion in 829 ps and dissipates merely 5.84 mW at a data rate of 1 GHz and a supply voltage of 1.8 V in TSMC 0.18-[micro]m CMOS technology. Index Terms--Carry-lookahead adder (CLA), carry-select adder (CSL), redundant binary (RB) multiplier, reverse converter, ripple-carry adder.

A configuration of a linearized operational transconductance amplifier (OTA) for low-voltage and high-frequency applications is proposed. By using double pseudodifferential pairs and the source-degeneration structure under nano-scale CMOS technology, the nonlinearity caused by short channel effect from a small feature size can be minimized. A robust common-mode control system is designed for input and output common-mode stability and thus reduces distortion caused b y common-mode voltage variation. Tuning ability can be achieved by using MOS transistors in the linear region. The linearity of the OTA is about -60-dB third-order inter-modulation (IM3) distortion for up to 0.9 [V.sub.pp] at 40 MHz. This OTA was fabricated by the TSMC 180-nm deep n-well CMOS process. It occupies a small area of 15.1 x [10.sup.-3] [mm.sup.2] and the power consumption is 9.5 mW under a 1.5-V supply voltage. Index Terms--Operational transconductance amplifier (OTA), pseudodifferential structure, short channel effect, source degeneration.

We have proposed a novel poly-Si/a-Si/HfSiON transistor to enhance reliabilities without performance degradation for a 65-nm-node low standby power (LSTP) application. By insertion of a thin amorphous-Si layer between the Poly-Si gate electrode and HfSiON, both phosphorus penetration from gate electrode and a reaction at gate electrode/HfSiON interface are successfully suppressed, so that positive bias temperature instability, one of the biggest issues for high-k gate dielectric, is drastically improved by two orders of magnitude. By carefully optimizing the gate stack structure of HfSiON, the HfSiON device can satisfy both lower gate leakage and gate-induced drain leakage at the same time. As a result, an excellent [I.sub.on]--[I.sub.standby] (=[I.sub.g] + [I.sub.off]) characteristic can be achieved, compared to the conventional SiON device. The a-Si insertion technique can realize the combination between the high-k gate dielectric and Poly-Si for future LSTP applications. Index Terms--Amorphons-Si (a-Si), gate leakage, gate-induced drain leakage (GIDL), HfSiON, high-k, phosphorus, positive bias temperature instability (PBTI), reliability.

Historically, design margin and defects have been viewed as different topics, one a part of design and the other a part of a test. Shrinking process geometries are making the two part of a continuum. This paper discusses the leakage and delay behavior associated with classic resistive defects and compares it with transistor variation due to lithography. Index Terms--Characterization, defect modeling, design margin, standard cells, variation.

This paper presents two fully integrated CMOS transmit/receive (T/R) switches with improved body-floating operations. The first design exploits an improved transistor layout with asymmetric drain-source region, which reduces the drain-source feed-through for body-floated RF switches. In the second design, a switched body-floating technique is proposed, which reconfigures the body-floating condition of a switch transistor in the ON and OFF states. Both designs are fabricated in a standard 0.13-[micro]m triple-well CMOS process. With regard to 2-dB insertion loss, the switch with asymmetric drain-source achieves 28-GHz bandwidth, which is among the highest reported frequencies for CMOS T/R switches. The bandwidth of the switched body-floating design is 16.6 GHz. There is approximately 5 dB better isolation obtained in the switched body-floating design. With the resistive double-well body-floating technique, 26.5- and 25.5-dBm input 1-dB compression point ([P.sub.1dB]) are obtained, respectively. Both designs consume only 150 [micro]m x 100 [micro]m die area. The demonstrated T/R switches are suitable for high-frequency and wideband transceivers. Index Terms--Asymmetric drain-source, CMOS integrated circuits, MOSFET switches, RF switches, switched body floating, transmit/receive (T/R) switches, triple well.

The transient radiation response of single- and multiple-gate fully depleted silicon-on-insulator (FD SOI) transistors is investigated with heavy ion and pulsed laser experiments. Very fast transients are shown on single-gate devices while non-planar [OMEGA]-gate transistors exhibit longer transient pulses. The current process of multi-gate devices, which includes long resistive access to source and drain electrodes, is shown to be responsible for these longer pulses, they are not an intrinsic characteristic of multi-gate devices. The charge collection mechanisms are discussed with I-D device simulations as a function of device architecture and Mixed-mode simulations are used to present trends on the sensitivity to single event upset and single event transient of elementary cells based on a 50 nm FD SOI technology. Index Terms--Charge collection mechanisms, heavy ion, multiple gate transistors, pulsed laser, single event effects, single event transient, single event upset, SOI.

Simultaneous least-squares adjustment of calculated neutron spectra in the central cavity of SPR-III and in the Pb-[B.sub.4]C bucket at ACRR is described, and the resulting 1-MeV-equivalent fluences are compared with damage measurements in 2N2222A transistors. Index Terms--Dosimetry, fission reactor measurements, least squares methods, neutron radiation effects, neutron spectroscopy, semiconductor device radiation effects.

This paper evaluates the radiation responses of 2.5 V I/O transistors and regular-threshold MOSFETs from a 90 nm commercial bulk CMOS technology. The data obtained from [sup.60]Co ionizing radiation experiments indicate enhanced TID susceptibility in I/O devices and circuits, which is attributed to the p-type body doping. A quantitative model is used to analyze the effects of doping and oxide trapped charge buildup along the sidewall of the shallow trench isolation oxide. These effects are captured in the general electrostatic equation for surface potential, which can be correlated to off-state leakage current. Device simulations are used in concert with experimental measurements and the analytical model to provide physical insight into the radiation response of each device type. Index Terms--I/O transistors, off-state leakage, oxide trapped charge, p-type body doping, regular-threshold, total ionizing dose.

Analysis of 90 nm CMOS SET response quantifies the interaction between charge collection and charge redistribution in a matched-current-drive inverter chain. It is shown that the SET pulse width difference between an n-hit and p-hit is due to parasitic bipolar amplification on the PMOS device. This difference is exploited to optimize transistor sizing and n-well contact layout for SET RHBD in combinational logic. Index Terms--Charge collection, charge confinement, lateral parasitic bipolar, n-well collapse, n-well contact area, n-well contact location, radiation hardened by design, transistor sizing.

The hot-carrier degradation behavior of both lateral and vertical integrated DMOS is investigated in detail by the analysis of the electrical data, charge pumping measurements and two-dimensional device simulations. Findings show that due to the specific nature of the vertical DMOS (VDMOS) device, the hot hole injection is absent in the device and the channel N(sub it) formation is substantially lower in the VDMOS.

A comparison of the structural and electronic properties of continuous grain (CG) silicon fabricated by low temperature catalyst-assisted solid-phase crystallization with that of low-temperature polycrystalline silicon (LTPS) was conducted. The results proved that CG had a large domain size (15 micrometers) whereas the size of the conventional LTPS was less than 1 micrometer.

A novel tetraethylorthosilicate (TEOS)/oxynitride stack gate dielectric for low-temperature poly-Si thin film transistors, composed of a plasma-enhanced chemical vapor disposition (PECVD) thick TEOS oxide/ultrathin oxynitride grown by PECVD N2O plasma, is proposed. The proposed novel stack oxide has better interface quality, lower bulk-trap density, and higher long-term reliability than PECVD TEOS dielectrics.

A statistical model for extracting geometrical variations in nominally identical devices fabricated in close proximity to each other is provided. Related geometrical variations, namely corner influences, where the source and drain encounter the isolation edges are examined and incorporated in the model.

Two soluble phthalocyanine derivatives, 2, 9, 16-tri(tert-butyl)-23-(10-hydroxydecyloxy) phthalocyanine (1) and 2, 9, 16-tri(tert-butyl)-23-(10-hydroxydecyloxy) copper phthalocyanine (2) were used as semiconductor layers in organic thin-film transistors (OTFTs) based on their Langmuir - Blodgett (LB) films. The highest occupied molecular orbital and the lowest unoccupied molecular orbital were determined, and the energy band diagram of their OTFT can be deduced by the cyclic voltammetric measurements.

A simple method to determine the interface and bulk density of states in polycrystalline silicon thin-film transistors is presented. Both interface and bulk traps were found to consist of deep states with constant density near the mid-gaps and band-tails with energy increasing exponentially with the energy.

The (VMT) has two channels with differing velocities. A noise model for the VMT is developed that suggests that high electron mobility transistor-like (HEMT-like) noise is achievable with good carrier confinement.

A magnetic tunnel transistor (MTT) with a full epitaxial [Co.sub.66][Fe.sub4]/Au/[Co.sub.66][Fe.sub.34] spin valve base, grown on GaAs, is presented. The layer structure of the system is analyzed by TEM, XPS, and STM. For a bias voltage of 1.1 V, the MTT shows a magneto current ratio of 85% and a transfer ratio of 1.5 * [10.sup.-6.] We ascribe these low values to the, although epitaxial, rough structure of the sample. Index Terms--Epitaxial, magnetic tunnel transistor, spin valve.

The effect of post-thermal annealing after indium-halo implantation on the reliability of sub-0.1 (mu)m nMOSFETs is investigated. Findings show that the control of annealing time is more efficient than that of annealing temperature with respect to improving the hot carrier-induced device degradation and that the best results of device performance are obtained with post-annealing treatment performed at medium temperatures for a longer time.

Very good quantitative agreement was found between the experimental and simulated switching transients of a Si avalanche transistor at extreme currents. Marked current localization was found, which was of a non destructive character with nanosecond current pulses due to a very significant reduction in the residual voltage across the transistor at high current densities and specific location of the region of intensive heat generation.

The resonant plasma waves oscillations in several gate-length InGaAs high electron mobility transistors (HEMTs) are measured. A numerical approach is developed that is based on hydrodynamic equations coupled to a pseudo-two-dimensional Poisson solver and a comprehensive spectroscopy of plasma waves in HEMTs is described.

Carrier mobilities in ambipolar field-effect transistors (FETs) are analyzed by using a rubrene single crystal assembled with Au/Ca electrodes and Si[O.sub.2] gate insulators modified by polymethylmethacrylate (PMMA), parylene-C, and hexamethyldisilazane (HMDS). The shift of light emitting with applied gate voltage is seen in a device with PMMA modified insulator and Au-Ca asymmetric metals.

The analysis of the data following the McWhorter model for the low frequency noise in amorphous Si thin film transistors (TFTs) with Si[N.sub.x] gate dielectric has shown relatively low density of traps. The value is close to the lower limit for amorphous and polycrystalline Si TFTs and the trap density has increased with the increase of the gate voltage.

The preparation, vacuum deposition, structure, and properties of Metal-organic thin-film transistor formed by bis(o-diiminobenzosemiquinonate) nickel(II) complex is described. The study is the first report of a complex with radical o-semiquinonate ligands being used as the conducting layer of thin-film transistors device.

The nonuniform polarization charging effects due to the ion flow on the ion-dust elastic collision process is investigated in the presence of ion drift. The results revealed that the nonuniform charging effects significantly enhance the differential scattering cross section for backward-scattering directions.

Ultrathin oxide-gated point-contact junctions are fabricated to explore single-electron charging effects in strongly gate-dot-coupled polycrystallinesilicon transistors. Current-voltage (I-V) measurements show periodic current oscillations near room temperature.

Researchers have incorporated electronic circuitry into the tissues of a rose. Magnus Berggren at Linkoping University in Norrkoping, Sweden, and his colleagues submerged the cut end of a rose stem [...]