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The aim of this paper is to present the 3D-sequential integration and its main prospective application sectors. The presentation will also give a synoptic view of all the key enabling process steps required to build high performance Si CMOS integrated by 3D-sequential with thermal budget preserving the integrity of active devices and interconnects and will sketch a status and prospect on current low temperature device performance.

This paper highlights the last technological breakthroughs achieved in the development of low temperature process modules at 500°C for 3D sequential integration. The two remaining process steps (low temperature gate stack and selective silicon raised source drain epitaxy) that were considered as potential showstoppers for this technology have shown decisive progress very recently.

We report the efforts and challenges dedicated towards building a scalable quantum computer based on Si spin qubits. We review the advantages of relying on devices fabricated in a thin film technology as their properties can be in situ tuned by the back gate voltage, which prefigures tuning capabilities in scalable qubits architectures.

The 3D sequential integration, of active devices requires to limit the thermal budget of top tier processing to low temperature (LT) (i.e. $\mathrm{T}_{\text{TOP}}=500^{\circ}\mathrm{C})$ in order to ensure the stability of the bottom devices. Here we present breakthrough in six areas that were previously considered as potential showstoppers for 3D sequential integration from either a manufacturability, reliability, performance or cost point of view. Our experimental data demonstrate the ability to obtain 1) low-resistance poly-Si gate for the top FETs, 2) Full LT RSD epitaxy including surface preparation, 3) Stability of intermediate BEOL between tiers (iBEOL) with standard ULK/Cu technology, 4) Stable bonding above ULK, 5) Efficient contamination containment for wafers with Cu/ULK iBEOL enabling their re-introduction in FEOL for top FET processing 6) Smart Cut™ process above a CMOS wafer.

Silicon-based quantum bits with electron spins in quantum dots or nuclear spins on dopants are serious contenders in the race for quantum computation. Added to process integration maturity, the lack of nuclear spins in the most abundant $^{28}$silicon isotope host crystal for qubits is a major asset for this silicon quantum technology. We have grown $^{28}$silicon epitaxial layers (epilayers) with an isotopic purity greater than 99.992 % on 300mm natural abundance silicon crystals. The quality of the mono-crystalline isotopically purified epilayer conforms to the same drastic quality requirements as the natural epilayers used in our pre-industrial CMOS facility. The isotopically purified substrates are now ready for the fabrication of silicon qubits using a state-of-the-art 300 mm Si CMOS-foundries equipment and processes, Comment: 7 pages, 7 figures

session 32: Process and Manufacturing Technology (32.2); International audience; For the first time, a low temperature (LT) FinFET process is demonstrated, using Solid Phase Epitaxy Regrowth (SPER), gate last integration and Self Aligned Contact (SAC). The LT devices exhibit performances close to those of the High Temperature Process Of Reference (HT POR). Several techniques of SPER doping are investigated and an innovative Double SPER (DSPER) process using two amorphization/recrystallization steps, is demonstrated. This DSPER process has the advantage of doping the bulk of the S/D junctions. This work opens the door to the fabrication of high-performance LT FinFETs for 3D sequential integration.

session: Monolithic 3D 3; International audience; This work investigates the possibility to reduce the Solid Phase Epitaxy Regrowth (SPER) temperature for dopant activation needed in 3D sequential integration. The electrical results obtained on 28nm FDSOI devices show that 500°C SPER can yield similar performance to that of 600°C SPER and 1050°C spike anneal. This paper highlights the advantages of using a -oriented channel and tilted implantation to successfully reduce the SPER thermal budget. It also confirms that the channel can be used as a seed for the recrystallization. The analysis takes into account the SPER rate dependence on temperature, crystalline orientation, dopant type and dopant concentration.

In this paper, the recent advances in low temperature process in view of 3D VLSI integration are reviewed. Thanks to the optimization of each low temperature process modules (dopant activation, gate stack, epitaxy, spacer deposition) and silicide stability improvement, the top layer thermal budget fabrication has been decreased in order to satisfy the requirements for 3D VLSI integration.

International audience; 3D sequential integration requires top FETs processed with a low thermal budget (500-600°C). In this work, high performance low temperature FDSOI devices are obtained thanks to the adapted extension first architecture and the introduction of mobility boosters (pMOS: SiGe 27% channel / SiGe:B 35% RSD and nMOS: SiC:P RSD). This first demonstration of n and p extension first FDSOI devices shows that low temperature activated device can match the performance of a device with state-of-the-art high temperature process (above 1000°C).

This work highlights recent advances in 3D VLSI integration. A review of low temperature process modules development such as junctions, spacers and salicidation is presented. Finally, for the first time, a full CMOS over CMOS 3D VLSI integration on 300mm wafers is demonstrated with a top level compatible with state of the art high performance FDSOI (Fully-Depleted Silicon On Insulator) process requirements such as High-k/metal gate or raised source and drain.

After a short reminder of the principle of monolithic 3D integration, this paper firstly reviews the main technological challenges associated to this integration and proposes solutions to assess them. Wafer bonding is used to have perfect crystalline quality of the top layer at the wafer scale. Thermally stabilized silicide is developed to use standard salicidation scheme in the bottom layer. Finally a fully depleted SOI low temperature process is demonstrated for top layer processing (overall temperature kept below 650^oC). In a second part the electrical results obtained within this integration scheme are summarized: mixed Ge over Si invertor is demonstrated and electrostatic coupling between top and bottom layer is used to shift the threshold voltage of the top layer. Finally circuit opportunities such as stabilized SRAM or gain in density are investigated.

The effects of implant dose and annealing conditions on the diffusion, activation, and out-diffusion of the typical n-type dopants in germanium (phosphorus, arsenic, antimony) were studied. First, short annealing times were used to limit the diffusion of dopants and to match the conditions needed for the realization of shallow junctions. Sb is not well suited to achieve high activation levels because honeycomb voids can already form at doses of 3 × 1014 cm−2. Of the other two, P is a better candidate than As because it was possible to maximize the activation level to up to about 4.5 × 1019 cm−3 without noticeable diffusion. This absolute value has only a limited accuracy, though, since the mobility models available in literature lead to values which differ by more than one orde r of magnitude. Longer annealing times were then used to study the redistribution of the dopants. For P, a model based on migration predominantly via complexes with doubly negatively charged vacancies and dopant loss was implemented which allowed the simultaneous simulation of our experimental profiles with one set of parameters. The extracted diffusion coefficient with an activation energy of 2.2 eV is comparable to the results obtained in previous studies. No noticeable P clustering was observed in these experiments. The model was then adapted to simulate the redistribution of As and Sb. For Sb, clustering is apparent in the diffusion profiles and has to be taken into account in the simulations.

Dichlorosilane (SiH2Cl2) is essential for the Selective Epitaxial Growth of Si and SiGe in the windows of patterned wafers. However, it is plagued by relatively slow growth rates at low temperatures. Meanwhile, hydrogenated silicon precursors (such as silane (SiH4), disilane (Si2H6) or trisilane (Si3H8)), yield significantly higher Si and SiGe Growth Rates (GR) at low temperatures. Such precursors are intrinsically non selective versus dielectric masking materials, but this difficulty can be overcome with advanced (Cyclic) Deposition / Etch processes. Liquid Si precursors such as trisilane have however several drawbacks: (i) they are expensive to produce with electronic-grade quality; (ii) being liquid, they require dedicated bubblers to be delivered into the growth chamber. Taking full advantage of their decomposition at very low temperatures is also not always possible, as the resulting films might be of lesser crystalline and electronic quality (gas phase nucleation and/or an adatom surface mobility which is too low). By contrast, disilane is gaseous and gives higher GR than silane (the Si-Si bond strength, 33 kcal mol.-1, is indeed weaker that the Si-H bond strength, 47 kcal. mol.-1). With the proper process parameters, it is possible to have reasonable growth rates down to 450°C only for SiGe(:B). It is thus a good choice of silicon precursor for the low temperature growth of Si and SiGe layers. This is illustrated in the following, where we have benchmarked SiH4 and Si2H6 against SiH2Cl2 for the low temperature growth of Si and SiGe in 300mm industrial Reduced Pressure – Chemical Vapour Deposition (RP-CVD) chambers from major Suppliers A and B. Si growth rates are, for T < 575°C, approximately ten times higher with Si2H6 than with SiH4, which are in turn roughly ten times higher than with SiH2Cl2 (see Figure 1). Activation energies, 49-52 kcal. mol.-1 (SiH4), 51-56 kcal. mol.-1 (Si2H6) or 60-61 kcal. mol.-1 (SiH2Cl2), are in-between the Si-H and Si-Cl bond strengths. For given GeH4 and Si precursor mass-flow ratios, lower Ge contents and significantly higher SiGe growth rates are obtained at 550°C, 20 Torr with Si2H6 than with SiH4 and especially SiH2Cl2 (see Figure 2). The dependency of the Ge content x on the F(GeH4) / F(Si precursor), linear for a SiH4 - based chemistry (x / (1-x) = 2.27–2.50 * F(GeH4) / F(SiH4)), is parabolic for Si2H6 and SiH2Cl2 based chemistries (x 2 / (1-x) = 0.51–0.58 * F(GeH4) / 2*F(Si2H6) and x 2 / (1-x) = 2.22-2.37 * F(GeH4) / F(SiH2Cl2), respectively). The associated SiGe GR increase linearly with the GeH4 mass-flow irrespective of the Si precursor used. With SiH4 and SiH2Cl2, growth rates (Ge concentrations) are typically lower (slightly lower) in Supplier A than in Supplier B chamber. The situation is the opposite with Si2H6. Growth rates (and Ge contents) are then higher in the former reactor than in the latter. This is assigned to (i) a ~ 5°C offset between the two and (ii) effective precursor flows which are different (likely due to chamber geometry differences). Growth rate activation energies and relationships linking Ge concentration to precursor mass-flow ratios are nevertheless similar, as shown in Figure 3 for the SiH2Cl2 + GeH4 chemistry and various temperatures. Process transfer between the two should be rather easy, We have otherwise assessed the interest of having an in-situ surface preparation chamber connected to the N2-purged transfer chamber of our cluster tool on interfacial contamination and epitaxial quality. There are indeed two ways of removing native oxide on a Si wafer: (i) thanks to an ex-situ “HF-last” wet cleaning followed by a short queue time loading in the N2-purged load-locks or (ii) thanks to an in-situ exposure of the wafer surface to a remote NH3/NF3 plasma which transforms native oxide into a salt which is sublimated at low temperature. As the oxide-free surface is exposed for minutes up to tens of minutes to the air in the former case, while it stays under N2 in the latter case, we would expect the second to be better. We have therefore compared both processes for Si surface preparation prior to epitaxy. Surfaces are with the in-situ process always under high purity N2. This results in a threshold H2 bake temperature (above which there is no O interfacial contamination anymore) which is shifted downwards by ~ 25°C (from 775°C down to 750°C). Below that temperature, O sheet concentrations are with the in-situ process typically one third those associated with “HF-Last” wet cleanings and epitaxial surfaces are smoother, as shown in Figure 4. Figure 1

We demonstrate for the first time 70 nm gate length TiN/HfO 2 pMOSFETs on 200 mm GeOI wafers, with excellent performance: I ON = 260 μA/μm and I OFF = 500 nA/μm @ V d = −1.0 V (without germanide). These performance are obtained using adapted counterdoping and pocket implants. We report the best CV / I vs. I OFF trade-off for Ge or GeOI devices: CV / I = 4.4 ps, I OFF = 500 nA/μm @ V d = −1 V. Moreover, based on fine electrical characterizations ( μ , D it , R access , etc.) at T = 77–300 K, in-depth analysis of both ON and OFF states were carried out. Besides, calibrated TCAD simulations were performed to predict the performance enhancements which can be theoretically reached after further device optimization. By using germanide and reducing both interface state density and diode leakage we expect I ON = 450 μA/μm, I OFF = 100 nA/μm @ V d = −1 V for L g = 70 nm.

Wafers made of germanium epitaxied on silicon were implanted at various doses and energies and were then annealed at temperatures ranging from 515 to 600 °C and process times ranging from 10 to 60 s. The corresponding SIMS profiles were used as targets for the optimization of the parameters of a diffusion model. Although diffusion in germanium is often believed to be mediated by vacancies, physical considerations on the damaging of the substrate led us to consider an interstitially mediated diffusion mechanism. The amorphization caused by the implantation was taken into account to set the initial distribution of point defects. Our predictions of the diffused phosphorus profiles were obtained using a pair-model with various charge states including solubility limit and outdiffusion. This modelling allowed us to accurately fit with the same set of parameters more than 15 experimental profiles, even the box-shaped ones that occur at higher thermal budget.

P. Batude, M. Vinet, L. Clavelier, A. Pouydebasque, C. Tabone, A. Roman, L. Baud, V. Carron, F. Nemouchi, L. Sanchez, and S. Deleonibus. CEA-LETI, Minatec, 17 rue des Martyrs, 38054 Grenoble Cedex 9, France. perrine.batude@cea.fr 3D integration is regularly mentioned for its potential in decreasing interconnection delay, and for the density gain brought by stacking several transistors layers. An additional benefit of 3D integration lies in an independent optimization of n-FET and p-FET allowed by stacking entire p-FET onto n-FET layers. In this integration scheme, connecting the layers at the transistor scale is absolutely mandatory. 3D monolithic integration, with its high alignment performance fulfils this requirement whereas parallel integration falls short in this aspect (best alignment performance at 1 sigma ~0.5μm). To achieve 3D monolithic integration, some issues such as realization of high quality top film, high stability bottom FET, low TB (Thermal Budget) top FET still have to be solved. In this paper, a 3D monolithic process flow relying on molecular Wafer Bonding (WB) (fig.1) is proposed and breakthroughs in the critical steps are presented. It allows full enhancement of n and p-FET performance through material choice, strain options, surface and channel orientation and metal workfunction tuning. Note that WB, contrary to other techniques for upper thin film realisation based on recristallisation, offers the possibility to co-integrate different surface and channel orientations. Furthermore this mature process step leads to a high quality crystalline top film with low TB. For the top crystalline layer realization, a Ge or Si on insulator substrate is bonded at room temperature on the fully processed bottom transistor layer after planarization of its topology (fig.1(b)). A low temperature anneal (200°C) is performed to strengthen the bonding interface before mechanical substrate removal. The bonding is found of excellent quality with bonding energy of 900 mJm (mazzara method) and clean acoustic and infrared characterisation as shown in figure 2 (a,b) . Note that the Inter Layer Dielectric (ILD) thickness (fig.2(c)) is thinned down to 100 nm and allows dense 3D contacts. Indeed this additional depth, specific to 3D technology must be minimized to enable the contact scalability as its etching and filling become critical. To spare the bottom FET from high temperature anneal for top transistor dopant activation, which would have detrimental impact on its performance, SPE (Solid Phase Epitaxial) on thin SOI films (

We hereby present a non-destructive method for extracting the activation level on boron-doped germanium-on-insulator (GeOI) wafers, with a discussion on the impact of the hole mobility model. This method combines Monte Carlo boron profile simulations with optical Ge layer thickness TGe and electrical sheet resistance Rsh measurements. As B atoms are known not to diffuse in Ge for the usual activation temperatures (

This study was conducted to assess the tolerability and efficacy of a ternary bimonthly irinotecan (CPT-11) - oxaliplatin (OHP) - infusional 5-fluorouracil (5-FU)/folinic acid (FA) combination in advanced colorectal cancer patients who had received prior CPT-11 and/or OHP-based chemotherapy regimen. Colorectal cancer patients were given bimonthly CPT-11 as a 90-min infusion, followed by OHP (85 mg/m(2)), FA (200 mg/m(2)) 2-h infusions and 5-FU (48-h infusion). CPT-11 and 5-FU doses were escalated as reported below. 26 patients were recruited. Fourteen patients had received a prior CPT-11-, 6 patients a prior OHP-based chemotherapy regimen and 6 patients both regimens. Three dose levels were investigated: CPT-11 100, 120 and 140 mg/m(2) and 5-FU 1500, 1800 and 2100 mg/m(2) in 6, 12 and 8 patients, respectively. All patients were evaluable for toxicity, 24 for antitumor activity. At all dose levels toxicity was acceptable. Grade 4 toxicity occurred in two patients only (neutropenia in one case and stomatitis in another one, 3.8%). Grade 3 toxicities included nausea and vomiting (34.6%), asthenia (26.9%), neurosensory toxicity (15.4%), neutropenia (3.8%) and diarrhea (3.8%). Hematological toxicity was infrequent and generally mild. At the third dose level, a higher, although not significantly different incidence of hematological and neurosensory toxicity (both occurring in 62.5% of cases, all grades) was observed compared to the other two, while nausea and vomiting were significantly less frequent (37.5% vs 100%). Overall, we observed 2 complete responses, 9 partial responses (OR 45.8%), 8 stable disease (33.3%), and 5 disease progression (20.8%). Median overall survival was 18 months and median time-to-progression 5.5 months. This combination showed moderate toxicity and promising antitumor activity in CPT-11 and/or OHP pretreated colorectal cancer patients. The second dose level using CPT-11 at 120 mg/m(2) and 5-FU at 1800 mg/m(2) is recommended for further phase II studies in this patient population.

Background As yet, no population-based prospective studies have been conducted to investigate the incidence and clinical outcome of glioblastoma (GBM) or the diffusion and impact of the current standard therapeutic approach in newly diagnosed patients younger than aged 70 years. Methods Data on all new cases of primary brain tumors observed from January 1, 2009, to December 31, 2010, in adults residing within the Emilia-Romagna region were recorded in a prospective registry in the Project of Emilia Romagna on Neuro-Oncology (PERNO). Based on the data from this registry, a prospective evaluation was made of the treatment efficacy and outcome in GBM patients. Results Two hundred sixty-seven GBM patients (median age, 64 y; range, 29–84 y) were enrolled. The median overall survival (OS) was 10.7 months (95% CI, 9.2–12.4). The 139 patients ≤aged 70 years who were given standard temozolomide treatment concomitant with and adjuvant to radiotherapy had a median OS of 16.4 months (95% CI, 14.0–18.5). With multivariate analysis, OS correlated significantly with KPS (HR = 0.458; 95% CI, 0.248–0.847; P = .0127), MGMT methylation status (HR = 0.612; 95% CI, 0.388–0.966; P = .0350), and treatment received in a high versus low-volume center (HR = 0.56; 95% CI, 0.328–0.986; P = .0446). Conclusions The median OS following standard temozolomide treatment concurrent with and adjuvant to radiotherapy given to (72.8% of) patients aged ≤70 years is consistent with findings reported from randomized phase III trials. The volume and expertise of the treatment center should be further investigated as a prognostic factor.

Il metodo ad Onte Guidate sta riscuotendo sempre maggiore interesse nel campo della sicurezza degli impianti industriali. Esso consente, infatti, di svolgere con semplicità e rapidità, un controllo di screening delle tubazioni ai fini della valutazione del loro stato di conservazione ed efficienza. Proprio perché controllo di screening, il metodo ad Onde Guidate presuppone ulteriori controlli di dettaglio, da effettuare su zone e componenti delle tubazioni che abbiano evidenziato indicazioni di una certa rilevanza. L’utilizzo esteso a vari tipi d’installazione e l’agevole ripetersi dell’indagine su tubazioni in esercizio, rende questo controllo particolarmente indicato per una diagnosi d’insieme (a carattere globale) sullo stato d’integrità anche di tubazioni coibentate o interrate, difficilmente ispezionabili con altri metodi, senza interventi di preparazione particolarmente onerosi. La linea guida qui proposta è stata redatta con l’intento di fornire uno strumento per fornire: • per quanto possibile, il senso concreto delle potenzialità diagnostiche della metodica, ma sottolinearne anche le limitazioni applicative; • gli elementi essenziali di caratterizzazione della metodica sotto il profilo della fisica di base, dell’adeguatezza dell’approccio diagnostico per le diverse tipologie applicative, della descrizione delle principali condizioni operative del controllo e interpretative dei dati rilevati; • le basi per un approccio strutturato della metodica, complementare al primo importante contributo della specifica norma sperimentale di prodotto elaborata a livello nazionale.

We present in this letter the most aggressive dimensions reported to date in Ge-channel transistors: pMOSFETs with 30-nm gate length on ultrathin germanium-on-insulator substrates (TGe = 25 nm). By improving both the Ge-enrichment technique and the transistor fabrication process, we demonstrate devices with controlled threshold voltage (Vth) and excellent short-channel effects. Moreover, the low defectivity and the very low thickness of the Ge film lead to a record drain OFF-state leakage for Ge-channel devices (< 1 nA/?m at VDS = -1 V) and thus, to the best ON-state to OFF-state current ratio (ION/IOFF ~5 × 105), even at Lg = 55 nm.

The main challenge of Low Temperature (LT) Solid Phase Epitaxy (SPE) is the dopant deactivation during post activation anneal. For the first time, we demonstrate that, for LT-SPE activated Boron (B) on thin SOI substrates, B deactivation can be well controlled during post anneal at 400 °C–600 °C. This is achieved by locating the preamorphization induced end of range defects close to the Buried OXide (BOX), thus benefiting from the defect cutting off and sinking effect of the BOX. This offers the opportunity to use LT-SPE activation for dopant activation of the bottom and top FETs in LT 3D sequential integration. In addition, this allows ultra shallow junction to effectively beneficiate from an activation which is higher with LT SPE than with conventional high temperature (HT) spike anneal (1050°C). LT SPE B-doped ultra shallow junction (∼10nm) with a sheet resistance of 900 Ω/┚ was achieved, fulfilling the ITRS requirement for device scaling, down to 22nm node (1100 Ω/┚).

3D monolithic integration, thanks to its high vertical density of interconnections, is the only available option for applications requiring connections at the transistor scale. However to achieve 3D monolithic integration, some issues such as realization of high quality top film, high stability bottom FET, low thermal budget top FET still have to be solved. In this work, a 3D monolithic process flow relying on molecular wafer bonding is proposed and results in all critical steps are given. Significant breakthroughs have been obtained using a full wafer molecular bonding with thin interlayer dielectric and an original salicidation process stabilized up to 650°C enabling to reach high performance for the top and bottom transistor. With such technology, we demonstrate functional top and bottom transistors as well as 3D structures such as invertors and SRAMs.

We report for the first time the fabrication and the electrical operation of a Ge and Si based CMOS planar scheme with GeOI pFETs and SOI nFETs, taking advantage of the best mobility configuration for holes (Ge) and electrons (Si). The hybrid Ge/Si wafers have been obtained by the local Ge enrichment technique on SOI wafers. A sub 600 C CMOS transistor process featuring High-K/Metal Gate and silico-germanidation was used to obtain functional high mobility CMOS transistors (down to L = 160 nm). Excellent low-field mobility values for electrons in Si nFETs and holes in Ge pFETs were achieved (275 and 142 cm 2 /V/s resp.).

High temperature ion implantation was investigated as a possible solution to reduce the thermal budget in doping processes. Pre‐doped Si and Ge 200 mm wafers were used as substrates for implantation of 33As and 5B. Different heating methods were used. This includes the use of thermal transfer from a hot plate on the backside of the wafer or the thermal energy deposited by a high current density beam. An appropriate model was used to evaluate the wafer temperature when a direct measurement was not possible. We studied the efficiency of different configurations to maximise the thermal transfer to the wafer. The maximum temperature reached on the implanted substrate was calculated at 550 °C. Four‐point resistivity measurements and spectroscopic ellipsometry were used to understand the influence of the in situ heating on the implanted materials properties. Interestingly, self‐annealing resulting in activation and consequent re‐crystallization is observed at a much lower temperature than what is usually requir...

Technologic innovations enable management of medical equipment and power supply systems, with improvements that can affect the technical aspects, economics, and quality of medical service. Herein are outlined some technical guidelines, proposed by Istituto Superiore per la Prevenzione e la Sicurezza del Lavoro, for increasing the effectiveness of the power supply system and the safety of patients and surgeons in the operating room, with particular focus on transplantation. The dependence of diagnoses and therapies on operation of the electrical equipment can potentially cause great risk to patients. Moreover, it is possible that faulty electrical equipment could produce current that may flow through the patient. Because patients are particularly vulnerable when their natural protection is considerably decreased, as during transplantation or other surgery, power supply systems must operate with a high degree of reliability and quality to prevent risk, and must be designed to reduce hazards from direct and indirect contact. Reliability of the power supply system is closely related to the quality of the project, choice of materials, and management of the system (eg, quality and frequency of servicing). Among the proposed guidelines, other than normal referencing, are (1) adoption of a monitoring system to improve the quality of the electrical parameters in the operating room, (2) institution of emergency procedures for management of electrical faults, (3) a procedure for management of fires in the operating room, (4) and maintenance interventions and inspections of medical devices to maintain minimal requirements of safety and performance.

We present the shortest and narrowest high-κ/metal gate n- and pFETs on compressively strained enriched SiGe On Insulator (c-SGOI) reported to date (L G =20nm; W=30nm; T SiGe =15nm). The range of active area widths in this work allows observing the transition from biaxial to uniaxial stress due to lateral elastic strain relaxation, and its benefit down to 20nm gate length on hole mobility and pFET performance (up to ×2.85 I Dlin enhancement vs. SOI, I ON =520µA/µm / I OFF =130nA/µm at L G =20nm and V DS =−1V). Moreover, an improved electrostatic integrity compared to SOI pFETs is demonstrated in c-SGOI (DIBL=120mV/V vs. 160mV/V, respectively at L G =30nm). Combined to the intrinsic |V th,p | lowering properties of c-SiGe, these characteristics qualify trigate c-SGOI as a very promising candidate for high performance pMOSFETs.

The objective of the European project HELIOS is to combine a photonic layer with a CMOS circuit by different innovative means, using microelectronics processes. Bonding of AWG + Ge Photodiodes on CMOS wafer is achieved.

For the first time 3D sequential CMOS integration turns up to be an actual competitor for sub 22nm technology nodes. Thanks to the original use of molecular bonding, high quality top Si active layers are obtained. Thermally robust bottom salicide goes through the whole top FET processing without any significant sheet resistance degradation. The low temperature integration of raised source and drain for top layers is demonstrated. A decrease by 4A of the Equivalent Oxide Thickness is measured when a low thermal budget process is implemented. The electrostatic coupling between stacked FETs is demonstrated thanks to an ultra thin inter layer dielectric thickness of 60nm. It leads to a threshold voltage dynamic shift of 130mV enabling SRAM stabilization.

In this work, we studied Excimer Laser Annealing at 308 nm with 180 ns pulse duration on Phosphorus and Boron implanted in Germanium, with or without Pre-Amorphization Implant (PAI) and co-implant. Using an industrial tool, experimental results show that we can achieve electrical activation levels up to 1.2×1020 cm−3 for P implant in Ge, which is the highest level regarding the appropriate mobility model. With the B implanted samples, we obtained an electrical activation level higher than 1×1020 cm−3 which is the better results obtained whithout PAI [1]. Melt thresholds were determined to be 0.65 J/cm² in amorphized Germanium (a-Ge) and 0.95 J/cm² in crystalline Germanium (c-Ge). With P, the best activation was obtained after a complete melt of the amorphous layer and the amorphous / crystalline (a/c) interface, necessary to obtain a perfectly recrystallized layer. In the case of B, we found a better activation in the submelt regime compared the melt one, and no contribution on the electrical activation with PAI was observed.

In this work, the influence of a pre-amorphization implant (PAI) combined with a single-step spike anneal on the junction formation in Germanium is inverstigated, both for n-type dopant with Phosphorus (P) as well as for p-type dopant Boron (B). The experiments were performed on a 1.5µm Germanium (Ge) epi-layer onto 200mm Silicon (Si) substrate. After implantation both with or without PAI, the dopant activation was achieved using a single step, conductive, spike anneal (ranging 550oC–900oC) in a ASM Levitor® system. Junction depth (Xj) and electrical activation levels (N act ) were characterized using secondary-ion-mass spectroscopy (SIMS) and sheet resistance Rs measurements. The results show that the combination of the high ramp rates with single step spike anneal on the one hand and PAI on the other hand, improved junctions characteristics compared to standard implant and RTP (Rapid Thermal Processing) conditions. The SIMS results show a reduction of junction depth for pre-amorphized junction after activation annealing up to 20% with P and 42% with B at 5×1018 cm−3 dopant concentration. In addition, electrical activation levels up to 4,95×1020 cm−3 were achieved for the p-type implants.

The extraction of the trap density on Ge/gate-stack (top) and Ge/BOX (bottom) interfaces of germanium-on-insulator pMOSFETs is shown using the Lim & Fossum model historically developed for fully depleted SOI devices. The doping and the thickness of the Ge film do not change significantly the top interface trap density. The bottom one is slightly raised by doping the Ge film. This method can be used as a simple and efficient meaning of the interface trap density levels monitoring during process optimization of GeOI devices.

Germanium MOSFET is considered as a promising alternative to silicon due to its intrinsically higher carrier mobility, especially for holes. Using appropriate channel and pocket implants, this paper presents for the first time well-behaved short channel devices characteristics featuring a negative Vth and no parasitic conduction at the BOx interface. After a brief presentation of the device fabrication, sub-threshold characteristics are discussed. The linear drain off-current can be reduced by a factor of 200 with channel+pocket implants. The effect of the drain voltage Vj is reflected in a strong band to band tunneling (BTBT) in the off-state leakage that can be reduced by junction optimization.

Germanium has regained attention in the semiconductor industry for MOSFET application because of the higher mobility of carriers – two times higher mobility for electrons and four times for holes – as compared to silicon. In the opposite of the Silicon, the major issue with Germanium is to limit the n-dopant diffusion. Usual n-dopants (Phosphorus and Arsenic for example) are not electrically activated at an acceptable level without a large diffusion of the doping profile and a substantial dose loss. In this work, we have studied the influence of low energy and dose implant (15KeV to 40KeV @ 8E13 to 1E15at.cm−2) and low temperature anneal (515°C to 600°C) on diffusion, exodiffusion and activation of the phosphorus dopant into Germanium. The annealing steps were made in RTP furnace, the chemical profile and electrically active profiles were extracted by using Secondary-Ion-Mass Spectroscopy (SIMS) and sheet resistance measurement (Rs). To investigate the implantation-induced defects in depth, cross-sectional micrographs were made by using Transmission Electron Microscopy (TEM). Experimental results show that we achieved an efficient activation level by tuning both dose implant and anneal temperature, limiting the exodiffusion with pratically no diffusion of the dopant. We also show that very abrupt profile can be achieved with appropriate implant and thermal annealing conditions. To limit the leakage current in devices, we suppose we have to limit the defects generated during the implantation. Specially for dopant activation temperature anneal below 550°C, we have shown and observed by cross-sectional micrograph that the defects are totally removed by addition of a pre step of annealing at 400°C.

We demonstrate for the first time 70 nm gate length TiN/HfO2 pMOSFETs on 200 mm GeOI wafers, with excellent performances: ION=330 muA/mum & IOFF=1 muA/mum @ Vd=-1.2 V (without germanide). These performances are obtained using adapted counterdoping and pocket implants. We report the best CV/I vs. IOFF trade-off for Ge or GeOI: CV/I=4.4 ps, IOFF=500 nA/mum @ Vd=-1 V. Moreover, based on fine electrical characterizations (mu, Dit, Raccess) at T=77-300 K, in-depth analysis of both ON & OFF states were carried out. Besides, calibrated TCAD simulations were performed to predict the performance enhancements which can be theoretically reached after further device optimization. By using germanide and reducing both interface state density and diode leakage we expect ION=450 muA/mum, IOFF=100 nA/mum @ Vd=-1 V for Lg=70 nm.

Germanium MOSFETs with high-k gate dielectrics have received recent attention (Clavelier et al., 2005 and Wu et al., 2005) for the future ultra large scale integration (ULSI), because of their superior transport properties (Clavelier et al., 2005). Thin-body Ge-on-insulator (GeOI) structures can provide advantages like low parasitic capacitances, immunity for short-channel effects, and low junction leakage currents. For device fabrication, it is mandatory to determine optimized doping conditions. Therefore, data on ion implantation, amorphizations and dopant activation in GeOI are needed. In this paper, we use optical non destructive measurements to study amorphization due to BF2 implantation in GeOI ("GOF method"). The obtained results have been confirmed by the electrical characterization. Moreover, we have extracted from the measured sheet resistances the Bore activation for the considered anneal

2058 Background: Following the EORTC/NCIC trial investigating temozolomide concurrent and adjuvant to radiotherapy, this regimen is considered standard treatment for newly diagnosed glioblastoma (G...

2003 Background: To assess the efficacy of treatment of medulloblastoma (MB) in adults (> 18 years). Methods: Ninety-five MB patients (pts) were enrolled a prospective phase II trial conducted betw...

2027 Background: MGMT promoter methylation status is known to be a potent prognostic factor in newly diagnosed glioblastoma (GBM) patients (pts). However, it is not yet clear whether and, if so, how MGMT methylation status may change; nor is it known whether the prognostic role of this epigenetic feature is retained during the disease course. Methods: A retrospective analysis was made using a database of 614 GBM pts treated prospectively from January 2000 to August 2008. We evaluated only patients who met the following inclusion criteria: age ≥18; PS 0–2; two distinct surgical procedures; histological diagnosis of GBM both at first and at second surgery for recurrence; postoperative treatment consisting of: a) radiotherapy (RT) followed by temozolomide (TMZ) until 2005, and b) TMZ concurrent with and adjuvant to RT after 2005; a time interval ≥3 month between first and second surgery. The study aim was to evaluate changes of MGMT status during the course of GBM. The log-rank test was employed to evaluate the significance of the prognostic variables. The percentages of MGMT methylated cases at first and second surgery were compared using the McNemar test. Results: MGMT status, evaluated at first and second surgery in all 44 pts (M:F 32:12, median age: 49 years, range: 27–67), was assessable in 38 (86.4%) cases: MGMT promoter was methylated in 13 (34.2%) pts at first surgery. MGMT methylation status, unchanged in 63.2% of second surgery samples, changed more frequently in methylated than in unmethylated pts (61.5% vs 24%, p = 0.03). The median survival was 24.3 months (95% CI: 20.8–27.7), being 35.2 months (95% CI: 10.1–60.2) and 21.9 months (95% CI: 17.3–26.5) for pts with methylated and unmethylated MGMT assessed at first surgery, respectively (p = 0.04). However, MGMT status at second surgery was no longer prognostic for survival (p = 0.1). Conclusions: Significant changes in MGMT methylation status during the course of GBM occur more frequently in MGMT methylated than unmethylated cases. Moreover, while MGMT methylation status is prognostic at first surgery, it appears to be of no prognostic utility at the time of second surgery. No significant financial relationships to disclose.

2027 Background: Temozolomide (TMZ), concomitant with and adjuvant to radiotherapy (RT), has become the standard treatment for newly diagnosed glioblastoma (GBM). The aim of the present analysis wa...

3751 Background:CPT11 or OHP in combination with infusional FU/FA induce objective responses (OR) in MCRC pts treated with the opposite combination. However, second-line response rates are still lo...