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The authors report upon highly reproducible, unipolar resistive-switching random access memory with narrow voltage distributions using Au/ZnO nanorods/Au structures. The ZnO nanorods resistive switching layer was prepared by a simple spin-coating process on a sol-gel seed layer, and from its size confinement effect, this device showed narrow set/reset voltage distributions and low voltage operations compared with Au/ZnO thin film/Au structures. With this electrical uniformity, the device exhibited good reliabilities such as long retention (> 70000 sec) and high endurance (> 5000 cycles).

The program/erase (P/E) cyclic endurances including bias temperature instability (BTI) behaviors of Metal-Al₂O₃-Nitride-Oxide-Semiconductor (MANOS) memories are investigated in comparison with those of Semiconductor-Oxide-Nitride-Oxide-Semiconductor (SONOS) memories. In terms of BTI behaviors, the SONOS power-law exponent n is ~0.3 independent of the P/E cycle and the temperature in the case of programmed cell, and 0.36~0.66 sensitive to the temperature in case of erased cell. Physical mechanisms are observed with thermally activated h * diffusion-induced Si/SiO₂ interface trap (N IT ) curing and Poole-Frenkel emission of holes trapped in border trap in the bottom oxide (N OT ). In terms of the BTI behavior in MANOS memory cells, the power-law exponent is n=0.4~0.9 in the programmed cell and n=0.65~1.2 in the erased cell, which means that the power law is strong function of the number of P/E cycles, not of the temperature. Related mechanism is can be explained by the competition between the cycle-induced degradation of P/E efficiency and the temperaturecontrolled h * diffusion followed by N IT passivation.

The electrical properties of Cr-SrTiO"3 films deposited on p-Si(100) substrates are investigated for application to a new type of charge-trap flash memory, named ReCTF (ReRAM+CTF). The Cr-SrTiO"3 film used as a switch in a ReCTF device has a complete cubic perovskite structure with a (200) crystallographic orientation. By means of current-voltage (I-V) and capacitance-voltage (C-V) analyses, we found that it exhibited electric-field-induced threshold switching characteristics and there were no trapping effects. In this study, we investigated how the retention characteristics of the ReCTF device can be improved without any special processes by applying an optimized Cr-SrTiO"3 film.

In this paper, in order to suppress unwanted current paths originating from adjacent cells in a passive crossbar array based on resistive random access memory (RRAM) without extrinsic switching devices, 1-diode type RRAM which consists of a 0.2% chromium-doped strontium titanate (Cr-) film deposited on a silicon substrate, was proposed for high packing density, and intrinsic rectifying characteristics from the current versus voltage characteristics were successfully demonstrated.

We report the effect of hydrogen annealing on the gate-leakage-current and switching characteristics of metal-alumina-nitride-oxide-silicon (MANOS) capacitors by analyzing their negative-/positive-bias instability (NBI/PBI). One sample, namely, A, is annealed with rapid thermal annealing (RTA), and the other sample, namely, B, is first annealed with RTA and then further annealed in a furnace, using a N2-H2 (98% nitrogen and 2% hydrogen) gas mixture. In the NBI/PBI experiments, the flatband voltage shift ΔVFB is observed to be smaller, i.e., the gate-leakage-current density is reduced for sample B at gate voltages less than ±3 V, a domain where trap-assisted tunneling is dominant. However, ΔVFB increases rapidly for the same sample at gate voltages larger than ±6 V, a domain where the modified Fowler-Nordheim tunneling (MFNT) is dominant, which indicates faster program-and-erase characteristics. These results show that additional hydrogen annealing can improve both device reliability and switching characteristics of the MANOS-type memory by reducing interface traps between the silicon substrate and silicon oxide layers, as well as turn-on voltages for MFNT.

The paper presents the passivation effect of post-annealing gases on the negative bias temperature instability of metal/silicon-oxide/silicon-nitride/silicon-oxide/silicon (MONOS) capacitors. MONOS samples annealed at 850 °C for 30 s by a rapid thermal annealing (RTA) are treated by additional annealing in a furnace, using annealing gases N 2 and N 2 –H 2 (2% hydrogen and 98% nitrogen gas mixture) at 450 °C for 30 min. MONOS samples annealed in an N 2 –H 2 environment are found to have lowest oxide trap charge density shift, Δ N ot = 8.56 × 10 11 cm −2 , and the lowest interface-trap density increase, Δ N it = 4.49 × 10 11 cm −2 among the three samples as-deposited, annealed in N 2 and N 2 –H 2 environments. It has also been confirmed that the same MONOS samples have the lowest interface-trap density, D it = 0.834 × 10 11 eV −1 cm −2 , using small pulse deep level transient spectroscopy. These results indicate that the density of interface traps between the silicon substrate and the tunneling oxide layer are significantly reduced by the additional furnace annealing in the N 2 –H 2 environment after the RTA.

ZnO-based charge-trap Flash technology using a resistive switching mechanism is demonstrated for next-generation nonvolatile memory. This device consists of metal/ZnO/nitride/oxide/silicon in order to make use of the electrical transport in the ZnO resistive switching layer. Compared to the previous devices with perovskite oxide materials used as a conduction path, the proposed device shows faster switching speeds (10 ns/100 μs), lower operation voltages ( ±7 V) for the program/erase ( P/E) states, and higher endurance (106 P/E cycles), along with comparable retention properties.

This letter covers the fabrication of a transparent resistive random access memory (T-ReRAM) device using ITO/AlN/ITO capacitors and its observed resistive switching characteristics. This AIN-based T-ReRAM shows a transmittance above 80% (including the substrate) in the visible region and an excellent switching behavior under ±3 V/10 ns with a high-to-low resistance ratio greater than 102. In the reliability test, the device showed an endurance of >; 108 cycles and a retention time of >; 105 s at 85°C. We believe that the AIN-based T-ReRAM presented in this letter could be a milestone for future see-through electronic devices.

In this paper, vertically trapped charge location is investigated to understand the carrier-transport dynamics in chromium-doped strontium titanate (Cr-SrTiO3 (STO))-based charge trapping memory devices using a transient analysis method. The vertical location of trapped charges is found to move from the Cr-SrTiO3/Si3N4 interface to the bulk region of Si3N4 with an increasing of the electric field, and, particularly, available trap sites are limited at the Cr-SrTiO3/Si3N4 interface by hole injection from the Si substrate into the Si3N4 layer at a high electric field (EOX > 7 MV/cm). In addition, some of these charges passing across the SiO2 (OX) layer generate many Si-SiO2 interface traps (Dit: 1.58 × 1012 cm−2 eV−1) that may degrade the device. However, the trapping efficiency can be improved by using sufficiently thick ( > 10 nm) bottom layers and by preventing direct hole tunneling and thereby, reducing the interface trap density.

The authors report a silicon-based one-diode–type resistive-switching memory (RRAM) device with self-rectifying properties and high electrical properties. The RRAM cell consisted of Al/Cr–SrTiO3/Si and revealed intrinsic diode properties, so that unwanted sneaky currents could be removed from an RRAM crossbar array without extra switching devices. The insulator–metal transition property of the proposed device was explained using the space-charge–limited conduction mechanism. The memory device showed good characteristics including high ON/OFF ratio (~106), low reset current (~10-11 A), high speed at low voltage (200 ns, 2 V), and reasonable endurance (>104 cycles) and retention characteristics (>104 s).

We investigated the deep-level traps formed in Cr-SrTiO3/Si3N4/SiO2 structures deposited on n-type Si by deep-level transient spectroscopy (DLTS). Three electron traps, with averaged activation energies of 0.24, 0.28, and 0.53 eV, were observed below the conduction band minimum of Si. Different behaviors in the dependence of DLTS on both filling bias and pulse confirm that the traps originate as the Si3N4 bulk trap, the Si3N4/SiO2 interfacial trap, and the Si/SiO2 interfacial trap. We also demonstrate that a specific point defect is the source of memory behavior in Cr-SrTiO3-based fusion-type charge trap flash (CTF) memory devices.

In this paper, we propose a charge-trap flash memory device using a ferroelectric material, Sr0.7Bi2.3Nb2O9 (SBN), with spontaneous polarization as a blocking layer. This device consists of metal/SBN/nitride/oxide/silicon and has an advantage in the carrier injection into the nitride from the silicon due to polarization charges formed in the ferroelectric material. Compared to conventional metal/oxide/nitride/oxide/silicon memory devices, the proposed devices showed a larger memory window (7 V), faster program/erase (P/E) speeds (100/500 μs), and higher endurance (105 P/E cycles) with comparable retention properties.

An effective resistive-switching effect has been observed in silicon nitride (Si3N4) dielectrics in Ag/Si3N4/Al memory cells. The ratio of the low resistance to high resistance state was larger than 107 at ±1.2 V for a 10 nm thick Si3N4 layer. This switching behavior is attributed to a change in the conductivity of the Si3N4 dielectrics, depending on whether nitride-related traps are filled with electrons under positive biases or unfilled under negative biases. This assertion is experimentally confirmed from the relationship between the amount of charges trapped in the Si3N4 layer and the corresponding changes in its resistance with respect to bias voltages. In addition, the formation or dissolution of the conductive path is confirmed by conductive atomic force microscopy current images.

We examined the origin of the charge traps in bothSiO2/Si3N4/SiO2 (ONO) and Al2O3/Si3N4/SiO2 (ANO) structures and their effect on the memory characteristics by capacitance-voltage (C-V) measurements and deep level transient spectroscopy (DLTS). A larger memory window was observed by C-V for ANO, due to its higher trap density. The DLTS showed that nitride traps are dominant in ANO, while more Si/SiO2 interface-related traps are observed in ONO. The ANO capacitor outperforms the ONO one in terms of both the program efficiency and retention, which is attributed to the reduced number of interface traps in ANO.

The origin of the electron memory trap in an oxide-nitride-oxide structure deposited on n-type Si is investigated by both capacitance-voltage and deep level transient spectroscopy (DLTS). Two electron traps are observed near 0.27 and 0.54eV, below the conduction band minimum of Si and are identified as the nitride bulk trap and the Si–SiO2 interfacial trap, respectively. The trap depth, viz., vertical distribution of the electron trap, in both nitride bulk and Si–SiO2 interface, are also estimated from the bias voltage dependent DLTS.