Search

Aims Emerging evidence has related inflammation-based biomarkers to numerous carcinomas, including bladder carcinoma (BC). However, the role of inflammatory biomarkers in the prognosis of BC remains inconclusive. This study aimed to compare preoperative plasma fibrinogen (PF) and other inflammatory biomarkers such as the platelet–lymphocyte ratio (PLR), neutrophil–lymphocyte ratio (NLR), lymphocyte–monocyte ratio (LMR), C-reactive protein (CRP) level, and serum albumin level to predict the prognosis of patients with BC. Methods This article focused on a retrospective analysis of 175 patients with newly diagnosed BC who were admitted to our hospital from March 2005 to March 2016. Of these BC patients, 136 had undergone radical cystectomy (RC). Results According to multivariate analysis, high PF level was an independent predictor of overall survival (OS) in 136 BC patients receiving RC (HR = 3.759; P = 0.011), but not for all 175 BC patients. Combining the NLR and PF values showed higher predictive accuracy for OS than NLR or PF alone (P < 0.05). Additionally, for 136 BC patients who had undergone RC, a close relationship was found between high PF levels (≥3.39 g/L) and lymph node metastasis (P = 0.011) and clinical T stage (P = 0.015). Furthermore, PF was a superior prognostic factor compared with the LMR, PLR, CRP, and albumin values in 136 BC patients who had undergone RC (P < 0.001). Conclusions The preoperative PF level may be a prognostic biomarker; and when combined with the NLR, it can improve the predictive ability of the survival of BC patients, particularly of BC patients who underwent RC.

This paper presents a split-based feedforward calibration technique for timing mismatch of Time-Interleaved Analog-to-Digital Converter (TI-ADC). The timing mismatch is estimated by using the difference between corresponding sample points of paired split-sub-ADCs, and compensated by a non-derivative interpolation method. Compared with traditional feedback methods with LMS iterative, the proposed feedforward calibration method can achieve much higher calibration speed and the complexity of digital post-processing is greatly relaxed without using of any dummy channel or filters. In addition, it has good calibration effects in both single-tone and multi-tone input conditions. Applied in a 1 GS/s 12-bit TIADC, the simulation result shows a convergence time of 1 × 104Ts under Nyquist frequency input with 2%Ts initial timing mismatch, and the peak signal to noise and distortion ratio of TI-ADC is improved from 37.54 dB to 67.60 dB with a normalized frequency of single-tone input signal fin/fS = 0.474. For a multi-tone input signal which contains 10 evenly distributed frequency points in the Nyquist frequency range, after calibration, the signal to noise and distortion improves 28.33 dB.

BackgroundForkhead box protein M1 (FOXM1) and β-catenin were confirmed to associate with numerous cancers, which attracted more attention in recent years. Our research investigated the expression of FOXM1 and β-catenin and their effects on prognosis of patients with muscle-invasive bladder cancer (MIBC). MethodsIn this study, FOXM1 and β-catenin expression was detected by immunohistochemistry in a study cohort including 121 MIBC patients. Results The results showed significant correlations of FOXM1 and β-catenin expression with tumor stage, tumor grade, and lymph node metastases in MIBC patients. Univariate analysis showed that patients with high FOXM1 (HR = 2.986; P = 0.011) and low β-catenin (HR = 2.623; P = 0.001) expression levels, advanced tumor stage (HR = 2.325; P = 0.002), advanced tumor grade (HR = 2.790; P < 0.001), tumor size (HR = 2.080; P = 0.020), lymph node metastases (HR = 3.392; P < 0.001), or recurrence status (HR = 2.016; P = 0.011) had a significantly higher risk of worse overall survival (OS). In the multivariate analysis, tumor stage (HR = 2.095; P = 0.009), tumor grade (HR = 1.962; P = 0.019), FOXM1 expression (HR = 2.196; P = 0.017) and lymph node metastases (HR = 2.136; P = 0.015) predicted worse OS. ConclusionTherefore, FOXM1 and β-catenin expression was relevant to MIBC incidence, tumor stage, tumor grade, metastasis, and survival and might be a reliable index to judge the prognosis of patients with MIBC.

Convolution Neural Networks (CNNs) involve massive data to be calculated and stored. To meet the challenges above, parallel hardware accelerators consisting of hundreds of Processing Elements (PEs) arranged as a many-core systemon-chip, connected by a Network-on-Chip (NoC) are proposed, which achieve high throughput exploiting parallel PE array. However, most of existing accelerators focus on only one aspect, such as compute structure of PE and data movement overhead above NoC, which causes the throughout, area and latency of the accelerator not fully optimized. In this paper, we propose an efficient general purpose CNN accelerator including both compute based on Non-Recovery Compression (NRC) method and data movement by novel Multi-Paths Packet Connection Circuit (MP-PCC). NRC can save computation time due to zero multiplier through shift decoding in PE and improve power efficiency by saving a large number of data transmission. MPPCC, evolved from Packet Connection Circuit, supports single and multicast transmission modes at the same time, and changes the multicast (X, Y) routing algorithm to multicast Y algorithm to improve the transmission efficiency. The proposed architecture which was implemented on Xilinx FPGA achieves 17.7x faster computation speed and 2.2x fewer memory accesses compared with the state-of-the-art method.

An all-digital background calibration technique for timing mismatch of Time-Interleaved ADCs (TIADCs) is presented. The timing mismatch is estimated by performing the correlation calculation of the outputs of sub-channels in the background, and corrected by an improved fractional delay filter based on Farrow structure. The estimation and correction scheme consists of a feedback loop, which can track and correct the timing mismatch in real time. The proposed technique requires only one filter compared with the bank of adaptive filters which requires (M-1) filters in a M-channel TIADC. In case of a 8 bits four-channel TIADC system, the validity and effectiveness of the calibration algorithm are proved by simulation in MATLAB. The proposed architecture is further implemented and validated on the Altera FPGA board. The synthesized design consumes a few percentages of the hardware resources of the FPGA chip, and the synthesized results show that the calibration technique is effective to mitigate the effect of timing mismatch and enhances the dynamic performance of TIADC system. The all-digital background calibration technique for timing mismatch is estimated by performing the correlation calculation of the outputs of sub-channels in the background, and corrected by an improved fractional delay filter based on Farrow structure.The estimation and correction scheme consists of a feedback loop, which can track and correct the timing mismatch in real time.The proposed timing mismatch estimation and correction scheme can effectively enhance the signal to noise ration of TIADC system with the merits of less hardware resources.

Deep neural network (DNN) has become a pivotal machine learning and object recognition technology in the big data era. The softmax layer is one of the key component layers for completing multi-classification tasks. However, the softmax layer contains complex exponential and division operations, resulting in low accuracy and long critical paths in hardware accelerator design. In order to solve the above issues, we present a softmax hardware architecture with proper accuracy, good trade-off and strong expansibility. We summarize the classification rules of neural network and balance the calculation accuracy between resource consumption. On this basis, we proposed an exponential calculation unit based on the group lookup table, and improve a natural logarithmic calculation unit based on the Maclaurin series and the data preprocessing scheme matching them. The experimental results show that the softmax hardware architecture proposed in this paper can achieve the calculation accuracy of 3 decimal fraction and the classification accuracy of $99.01%$. Theoretically, it can accomplish the classification task of infinite categories.

Adsorption characteristics of methane on coals before and after supercritical CO2 extraction are closely related to CO2 injection in coal seams for enhanced coalbed methane (ECBM) recovery and CO2 sequestration. Using self-developed extraction facility of supercritical fluids and micro-calorimetric measurement system, this work studied the adsorption behavior of methane on six types of coals which were pretreated with supercritical CO2 at 45 °C and 10 MPa for two weeks. The effects of supercritical extraction, coal rank and pressure on adsorption amount of methane, integral heat of adsorption and pore structure of coal samples have been analyzed. To interpret the experimental data, dynamical models are developed to describe the variations of gas pressure and heat released in the process of adsorption, and corresponding isotherm models are proposed to characterize the adsorption amount and adsorption heat for pretreated and untreated coal samples. The correlation between the integral adsorption heat and adsorption amount was discussed for different coal samples. It is found that compared with untreated coals, the adsorption amount and integral adsorption heat for pretreated coals are reduced, and the decrements are largely dependent on the coal rank. The integral adsorption heat relates linearly with the adsorption amount, and the ratio coefficients for medium rank coals decrease after supercritical CO2 extraction, whereas an increasing trend is found for low-rank and high-rank coals. In addition, it is revealed that the volume of micropores is reduced by supercritical CO2 extraction for low-rank and medium-rank coals, while no significant change is found for high-rank coals.

A digital calibration technique for timing mismatch in a four-channel time-interleaved ADCs is presented. The calibration principle is as follows. Firstly, we use delay units to have the clock of the first channel aligned with the channel that needs to be calibrated and do subtraction. Secondly, we use a digital sampling module and an error determination module to detect the timing mismatch between them. Lastly, a method of variable delay line is used to compensate the mismatch. The mismatch detection and compensation form a feedback loop that can achieve a real-time tracking and correcting. Simulation results showed that this technique can be applied to any channel TIADC and has the timing mismatch calibrated quickly and correctly by the virtue of a smaller hardware.

This paper describes a correlation-based background calibration method to calibrate the linear and non-linear gain errors of pipelined ADCs. The calibration algorithm introduces a sequence PN to the input of the sub-ADC to have the output code modulated, estimates the errors by correlating the injected sequence with the output code, and calibrates the errors based on a LMS algorithm. Simulation results show that, with an equivalent gain error 2% and a 3-order nonlinear gain error 2%, after calibration, the measured DNL and INL were improved to −0.46/0.88 LSB and −0.81/0.92 LSB, respectively, and the SFDR/SNDR are improved to 93.8dB and78.6 dB, respectively.

This paper proposes a low sub-gigahertz frequency generator with fine frequency resolution. An injection-locked ring oscillator (ILRO) is firstly adopted to obtain multiphase output at integer multiple times crystal oscillator (XO) frequency. Following that, a multiplexer (MUX) selects the output phase according to the output of a delta-sigma modulator ([Formula: see text]M) to achieve high frequency, low in-band noise fractional output. A hybrid type finite impulse response (FIR) filter, which is composed of some MUXs, flip-flops (FFs), digitally-controlled delay units (DCDUs), and a linear multiphase combiner (MPC), is employed in cascading to suppress the quantization noise (Q-noise) at high-frequency offset. An auto-calibration scheme for calibrating the DCDU’s delay has been proposed as well. Simulated in 65[Formula: see text]nm CMOS, the proposed fractional-N frequency generator exhibits a phase noise performance that is well below [Formula: see text]118[Formula: see text]dBc/Hz from 100[Formula: see text]kHz to 100[Formula: see text]MHz offset. The simulation also shows that the power consumption and die area is 10.6[Formula: see text]mW and 0.3[Formula: see text]mm2, respectively, with the FIR filter consuming 4.3[Formula: see text]mW and 0.041[Formula: see text]mm2.

A novel Time-Interleaved Analog-to-Digital Converter (TIADC) digital background calibration for the mismatches of offsets, gain errors, and timing skews based on split-ADC is proposed. Firstly, the split-ADC channels in present TIADC architecture are designed to convert input signal at two different channel sampling rates so that redundant channel to facilitate pair permutation is avoided. Secondly, a high-order compensation scheme for correction of timing skew error is employed for effective calibration to preserve high-resolution when input frequency is high. Numerical simulation performed by MATLAB for a 14-bit TIADC based on 7 split-ADC channels shows that Signal-to-Noise and Distortion Ratio (SNDR) and Spurious Free Dynamic Range (SFD) of the TIADC achieve 86.2 dBc and 106 dBc respectively after calibration with normalized input frequency near Nyquist frequency.

This paper presents a novel over-current protection circuit applied in constant current driver for LED. The circuit uses SENSEFET current sensing technique to sample inductor current, which has a high accuracy. It is different with the traditional over-current protection circuit, which uses voltage comparator. Current comparator, applied in this circuit, has simple structure and quick response. This over-current protection circuit has been successfully applied to a step-down constant current LED driver chip, and has been implemented with TSMC 0.25µm 40V BCD process. Simulation results show that the sampled current accuracy is 98.68%, meeting the accuracy requirements.

A novel adaptive off-time (AOT) technique, which is applicable to the circuit design of an AC-DC constant-current LED driver using hysteresis-current control method, is proposed in this paper. The AOT is achieved by a novel off-time control method, which is based on the combination of peak-current-loop and error sample feedback-loop, to solve the problem that peak current is not consistent with average current due to the constant off-time (COT) technique in the typical low side current sense topology. Output current magnitude is controlled by sense resistor. The simulation result shows that the average current error is no more than 1.1%. The average current achieves less than 1.5% variation in the output voltage range from 20V to 100V, which means good load regulation characteristic can be achieved. The design was implemented with TSMC' 0.25μm 40V BCD process.

Objective: The objective of this study was to screen and identify differentially expressed genes in invasive bladder transitional cell carcinoma (BTCC). Methods: Voided urine samples were collected from consecutive patients with BTCC and patients under surveillance for bladder cancer recurrence; voided urine samples from patients with nonmalignant diseases served as control. We identified the differentially expressed genes by comparing urine samples of bladder carcinoma to that of the control group with suppressive subtractive hybridization (SSH) and cDNA microarray. The differentially expressed genes were verified by quantitative real-time polymerase chain reaction (QPCR). Results: From the 762 white colonies, a total of 449 positive clones were obtained in which 112 were found to be upregulated in BTCC. Sequencing and homology analysis were performed for these 112 clonies. The detection rates of some known genes (including IGF- 1, human telomerase reverse transcriptase [hTERT], bladder cancer specific nuclear matrix protein 4 [BLCA-4] and homeobox A13 [HOXA13]) for BTCC at the Ta, T1 and >T1 stages were 48%, 90% and 100%, respectively, with a specificity of 85%. The test specificity was 80% for the 30 control patients with urinary tract infections. The combination of BLCA-4 and HOXA13 could distinguish between low- and high-grade tumours, with specificity and sensitivity of 80%. Conclusion: We successfully constructed a reliable SSH library of BTCC and found that combination detection insulin-like growth factor 1 (IGF-1), hTERT, BLCA-4 and HOXA13 genes could help to evaluate BTCC at different stages.

This paper presents a low-power rail-to-rail amplifier with a paralleled folded-cascold structure input stage and a feedforward class AB output stage. the switch in the bias circuit is switching off to boost the driving capability when the input single is low, or else, the amplifier works on the switching on state to save power. simulations using SMIC 0.35um process moled and cadence specre at 3.3V supply voltage, the amplifier performs almost 70dB dc gain, the CMRR reaches 140dB and the lowest static power consumption is just 0.6mW.this amplifier is used in the PGA of hige precision sigma-delta ADC as a buffer to meet the input sigle range of 2.5 V when the gain of the PGA is 1 or 2.

This paper presents a background calibration technique for gain error in Time-interleaved (TI) analog-to-digital converters (ADCs). The presented calibration technique is based on statistical characteristics of the input signal and error information can be obtained by analyzing the statistical properties of the input signal. Compared with conventional calibration algorithm, the presented calibration in this paper has low hardware resource consumption and no restriction on the input signal frequency, and can be extended to arbitrary number of channels. Simulation of the 8-bit 5-channel TIADCs with MATLAB shows that with gain error in the range of ±5% Vref, SNR of the output signal of the TIADCs is only 29.8dBc and reach 47.9dBc after calibration. The TIADCs performance is enhanced significantly by using this calibration algorithm.

This paper presents a background calibration algorithm based on the interpolation filter and the Least Mean Square (LMS) algorithm, taking the 5-channel Time-Interleaved Analog to Digital Converter(TIADC) as the model. And the algorithm is verified by the Simulink modeling and hardware. Comparing the spectra of the signals before and after calibration in the Simulink model, the ENOB rises from 3.62446 to 7.67697 and the SNR rises from 23.5815dB to 43.1738dB when the frequency of the input signal f in =29.8MHz While f in =59.8MHz, the ENOB rises from 3.62009 to 7.48092 and the SNR rises from 23.5552dB to 43.1929dB. Therefore, the correctness and the effectiveness of the algorithm have been verified.

A high-performance bootstrap switch for low-voltage switched-capacitor (SC) circuits is presented. The switch enables the precise sampling of input signals on a low voltage supply with high speed, low nonlinear distortion. Experimental results in TSMC 130nm CMOS process show that a peak signal-to-noise-and-distortion ratio (SNDR) of 102.8 dB, spurious-free dynamic range (SFDR) of 104.6 dB and total harmonic distortion (THD) of 105 dB can be acquired at 125 MSample/s.