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In this paper, a novel approach is introduced for the development of a power-efficient voltage differencing buffered amplifier (VDBA) by incorporating an adaptive biasing circuit. The proposed design is specifically tailored to exhibit low power consumption. The VDBA proposed in this study includes a conventional transconductance unit (TU) with an adaptive biasing and a positive feedback circuit. Incorporating adaptive bias cells and cross-coupled positive feedback circuit, the VDBA structure allows for boosted tunable gain based on the input differential voltage. The proposed VDBA shows improved transconductance gain, transient characteristics, linearity for a wide range of inputs, and reduced standby power dissipation. A mathematical formulation has been presented to define the characteristics of the proposed VDBA. To validate the proposed VDBA structure, SPICE simulations were conducted using 180 nm CMOS technology. The input linear range of the proposed VDBA is ± 250 mV. The 3 dB bandwidth of the proposed structure is 200 MHz. The THD has been found low. The Monte Carlo simulations have also been carried out and found the proposed structure is less sensitive to the different parameter variations. The slew rate of the proposed VDBA is found 26.2 V/µS. As an application example, a voltage mode universal MISO biquad filter is also proposed using the proposed structure VDBA. [ABSTRACT FROM AUTHOR]

This paper presents the design of an efficient operational transconductance amplifier (OTA) to be explicitly used for electroencephalogram (EEG) signal acquisition in neural amplifiers (NAs). The central objective of this study revolves around addressing the fundamental compromise between noise and power in the design of NAs. The overarching goal is to effectively mitigate this trade-off by introducing novel approaches. The proposed design's novelty lies in utilizing an adaptive biasing technique instead of the traditional current mirror biasing technique. Furthermore, the conventional input differential pair of the OTA is modified to employ a self cascode flipped voltage follower (SCFVF), which eventually reduces power consumption of the NA to 0.822 μ W. Additionally, notable improvements in noise performance are achieved and found to be 624.9 nV/ (H z) at 1 Hz. The gain and bandwidth range of the input low-noise amplifier is 54.2 dB and 2.8 Hz–207 Hz, respectively, which effectively amplifies low-amplitude noisy incoming signals, addressing the specific requirements of EEG signal acquisition. [ABSTRACT FROM AUTHOR]

Summary: This paper presents an on‐chip bias‐generating architecture for automotive applications with a wide input range of 3.8–36 V in a 0.18‐ μm high‐voltage bipolar‐CMOS‐DMOS (BCD) process. The proposed architecture effectively manages high‐voltage stress issues with few high‐voltage devices optimizing the silicon area. The proposed bias‐generator comprising crude‐reference and crude‐regulator generates a preliminary low bias voltage for the bandgap‐reference circuit. An adaptive‐biased, with‐capacitor, low‐dropout regulator generates a well‐regulated core supply with low quiescent current and better stability over the wide input range. The adaptive biasing expands the unity gain frequency with increasing load enabling a fast‐transient response. The proposed LDO provides a 5‐V output voltage and a load current of 10 μA to 20 mA from 5.5‐ to 36‐V supply with a 500‐mV dropout voltage consuming a very low quiescent current of 5 μA. With 0‐ to 20‐mA load step and an output capacitor of 1 μF, an undershoot of 40 mV and an overshoot of 55 mV are achieved. [ABSTRACT FROM AUTHOR]

An efficient implementation of low-voltage low power two stage fully differential transconductance amplifier using CMOS technology is proposed. In this work, the dynamic threshold voltage MOSFET (DTMOS) and unique adaptive biasing technique are used to obtain the enhanced slew-rate with minimized power supply overhead. This dynamic threshold MOS based fully differential OTA operates at ±0.5 V dual supply voltage. It provides average slew-rate as168 V/μS with 0.104 mW static power consumption. The dc gain of the circuit is calculated as 73.86 dB with a 72° phase margin. The figure of merit of proposed OTA is 16.15 [(V/µs).pF/µW] for the load capacitor of 10 pF, which shows significant improvement compared to prior work. To validate the robustness of the proposed design universal voltage mode filter is designed and simulated as its application. Mentor Graphics Eldospice with 0.18 μm TSMC level 53 CMOS technology has been used to verify the performance of the proposed circuit and its application. [ABSTRACT FROM AUTHOR]

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In this paper , DTMOS based recycling folded cascode with controlled positive feedback operational transconductance amplifier is introduced. The proposed Positive Feedback Recycling Folded Cascode Operational Transconductance Amplifier (PFRFC OTA) employs positive feedback which enhances and controls the dc gain of PFRFC OTA by adjusting current in feedback. The proposed PFRFC OTA also utilizes the high swing cascode current mirror (HSCCM) as active load which provides high output impedance at low power supply requirements. Moreover, the adaptive biasing is provided by using cross-coupled flipped voltage followers to the differential pair which results in remarkable improvement in gain, unity gain bandwidth and slew rate. The flipped voltage followers are also utilized to reuse the input current to drive the transistors which are connected in feedback with HSCCM. The proposed PFRFC OTA employs PMOS DTMOS transistors at the input stage which utilizes the body effect to enhance the performance of the proposed amplifier. The proposed PFRFC OTA with the second stage is also implemented to further improve the frequency response of the proposed circuit. Mentor Graphics Eldo tool with CMOS technology of 0.18 μm is used for the simulation of the proposed circuits at supply voltage of ±0.5 V. The simulation result of the proposed PFRFC OTA provides gain of 90 dB and a power consumption of 42 μW. The proposed two stage PFRFC OTA provides gain of 114.56 dB. To validate the efficiency of the proposed two stage PFRFC OTA, a tunable biquad filter is also implemented. • The proposed PFRFC OTA employs the High Swing Cascode Current Mirror (HSCCM) with controlled positive feedback at active load which enhances and controls the dc gain of proposed circuit by adjusting current in feedback loop. • The Flipped Voltage Followers (FVFs) are utilized to reuse the input current to drive the feedback transistors at load. FVFs based adaptive biasing technique and Dynamic Threshold MOS (DTMOS) transistors at the input stage further enhance the transconductance and slew of the proposed circuit. • Mentor Graphics Eldo tool is used to simulate the proposed circuit with 180 nm technology. The proposed PFRFC OTA (stage I and stage II) is implemented at ±0.5 V supply voltage along with load capacitance and compensation capacitance of 20 pF and 5 pF respectively. • Process Supply Voltage Temperature (PVT) variations and Monte Carlo analysis have been done to verify the robustness of proposed circuit. • By comparing the proposed circuit with previous works it is noticed that the proposed PFRFC OTA (stage I and stage II) provides the high gain, unity gain bandwidth and phase margin at low supply voltage of ±0.5 V. [ABSTRACT FROM AUTHOR]

Low-dropout regulators (LDOs) are widely adopted in power management integrated circuits (PMICs) and serve as a bridge between the switching regulators and individual on-chip modules to provide a smooth, regulated output voltage. Compared to digital LDOs (DLDOs), analog LDOs (ALDOs) lead in the advantage of low output ripple and large power supply rejection (PSR). However, the preference of achieving high performance in terms of load transient, high PSR, good load and line regulation, while maintaining a low quiescent current and low dropout voltage for high efficiency, remains the key challenge in ALDO design. For operation with a low quiescent current, the bandwidth is reduced due to low transconductance, resulting in the limited gate driving capabilities in terms of charging and discharging the large gate capacitance of the pass or output transistor. In addition, the preference for system-on-chip design in the absence of large off-chip capacitors arises stability issues. In this paper, recent reported state-of-the-art architectures for ALDOs are revisited and reviewed. The performance of these ALDOs is compared and their applications are investigated.

In this paper, a gain enhanced transconductance amplifier having high bandwidth and improved phase margin has been proposed. Miller compensation technique, using a series connected capacitor and resistor branch has been utilized to improve the phase margin of adaptively-biased cross-coupled high gain transconductance amplifier (proposed OTA-I). Further, gate compensation resistor is utilized to achieve bandwidth extension (proposed OTA-II). This proposed structure offers improvement in phase margin and bandwidth without increasing the power consumption or supply voltage requirement, while maintaining DC gain and linear range of the gain enhanced transconductance amplifier. The simulation results have been carried out in EldoSpice using TSMC based level 53, 0.18 µm CMOS technology with ± 0.6V supply voltage. These results show that for peaking free response in proposed OTA-II, phase margin of 59.40° and bandwidth of 33.31MHz can be achieved compared to values of 51.92° and 16.10MHz in conventional OTA. Monte Carlo and temperature analysis demonstrate robustness of the proposed circuit against process and temperature variations. [ABSTRACT FROM AUTHOR]

A proposed ultra-high slew rate current recycling folded cascode operational transconductance amplifier (OTA) working in the subthreshold region is presented. By employing adaptive biasing and the proposed positive-feedback nonlinear current mirror techniques, it not only forces the charge or discharge path to enter the strong inversion region during slewing, but also provides an ultra-high output current, leading to a significant boost in the slew rate. The simulation results of the two OTAs designed in SMIC 0.18 μ m CMOS process demonstrate that the slew rate of our proposed OTA is enhanced 387 times than that of the conventional counterpart with the same power. [ABSTRACT FROM AUTHOR]

This paper proposes a 300 mA low-dropout (LDO) regulator using an $I_{Q}$ of only $0.94~\mu \text{A}$ , which has the advantage of minimizing power consumption in the standby mode of a battery-based system. The LDO uses a source follower buffer with dynamic biasing to maintain loop stability and load transient response performance. Under light-load conditions, the buffer enters a fully-off state because there is a sub-nA bias current. Therefore, the LDO uses a dual output operational transconductance amplifier (DO-OTA) for operation under light-load conditions. The second output of the DO-OTA for light-load operation in the LDO forms an additional feedback path instead of the fully-off buffer. The second output of the DO-OTA is designed to consume a current lower than the bias current of the buffer while operating. Furthermore, the buffer in the LDO is designed for operation above 5 mA $I_{L}$ . While the buffer is operating, the dynamic biasing current of the buffer is used as the second output of the DO-OTA. The second output of the DO-OTA has lower output impedance characteristics than its main output, so the LDO can secure loop stability under light-load conditions by lowering the DC gain. As a result, the LDO exhibits load transient response performance up to 300 mA by using a minimal $I_{Q}$ under the no-load condition. The LDO is based on a 180 nm bipolar-CMOS-DMOS (BCDMOS) process and covers an area of approximately $256 \times 143 \mu \text {m}^{2}$ . The measured $I_{Q}$ is $0.94~\mu \text{A}$ under the no-load condition with a maximum load current of 300 mA.

This paper presents a second-order complex baseband operational transconductance amplifier-capacitor (OTA-C) filter design for wireless receivers. It employs a novel adaptive biasing circuit for large-signal linearization that extends the filter’s usable signal swing range. An analysis of this linearization technique provides insights into its underlying concepts to assist the design process. The method is demonstrated with the first experimental evaluation of a second-order complex baseband filter prototype having a center frequency of 2 MHz and a bandwidth of 850 KHz. Fabricated in a standard 130nm CMOS technology, the filter prototype measurement results show a gain of 35.1 dB and an image rejection ratio of 39.7 dB while operation from a supply voltage of 0.95 V and consuming 0.13 mA. This design advances the low-power bandpass filter state-of-the-art by having an in-band and out-of-band SFDR of 62 dB and 64 dB respectively due to the use of the large-signal linearization approach.

Kinase domains are highly conserved within proteins in both sequence and structure. Many factors, including phosphorylation, amino acid substitutions or mutations, and small molecule inhibitor binding, influence conformations of the kinase domain and enzymatic activity. ULK1 and ULK2 are serine/threonine kinases that serve important roles in autophagy, an intracellular recycling process capable of degrading proteins and organelles via fusion with lysosomes. ULK1/2 are emerging as therapeutic targets in human cancer, particularly KRAS-driven malignancies. Here, we performed molecular dynamics (MD) simulations to hypothesize bound poses for the ULK1/2 small molecule inhibitor, ULK-101. We observed stable bound states for ULK-101 to the adenosine triphosphate (ATP)-binding site of ULK2, coordinated by hydrogen bonding with the hinge backbone and the catalytic lysine sidechain. Notably, ULK-101 occupies a hydrophobic pocket associated with the N-terminus of the αC-helix. Large movements in the phosphate-binding loop (P-loop) are also associated with ULK-101 inhibitor binding and exit from ULK2. Together, our data support a model to explain ULK-101 potency toward ULK1/2.

A low voltage low power two-stage CMOS amplifier with high open-loop gain, high gain bandwidth product (GBW) and enhanced slew rate is presented in this work. The proposed circuit makes use of folded cascode gm-boosting cells in conjunction with a low voltage gain enhanced cascode mirror using quasi-floating gate (QFGMOS) transistors. QFGMOS transistors are also used in input pair and adaptive biasing, which facilitate large dynamic output current in the presented circuit. Consequently, the slew rate is enhanced without much increase in static power dissipation. The unity gain frequency (UGF) and dc gain of the circuit are 29.4 MHz and 132 dB, respectively. The amplifier is operated at 0.6 V dual supply with 89 μ W power consumption and has a nearly symmetrical average slew rate of 51.5 V/ μ s. All simulations including Monte Carlo and corner analysis are carried out using 180-nm CMOS technology for validating the design with help of spice tools. [ABSTRACT FROM AUTHOR]

This brief presents an ultra-low power low-dropout (LDO) regulator with an experimental total quiescent current consumption of only 3.08 nA. The circuit is designed to operate with a load current in the range 0 - 11 mA. A novel adaptive biasing scheme based on a super source follower (SSF) structure is proposed, which measures the absolute voltage difference between the two inputs of the LDO’s error amplifier and modifies the biasing current accordingly. Thus, the transient response of the regulator is improved by counteracting the effect of using such a low bias current. The proposed LDO has been fabricated in a standard CMOS 180 nm process and the experimental characterization showed an outstanding performance in terms of maximum load current over quiescent current consumption ratio. [ABSTRACT FROM AUTHOR]

Flat panel displays require buffers for column driving circuits. These buffers have unity gain and usually drive large capacitive loads. To maintain the rail-to-rail swing operation, most of the buffer circuits employ complementary differential pair input stage. Whenever the input voltage is close to supply voltages, one of the driving paths enters the cut-off state. In this paper, a novel adaptive biasing technique for biasing differential input pair transistors is proposed in order to maintain high driving capacity for the whole input range. In the proposed scheme, whenever an NMOS input stage enters the cut-off stage, the biasing current is boosted for the PMOS input stage and vice versa. As a result, without increasing the biasing current, driving capability of the circuit is boosted in the ranges which are close to the supply voltages. With the proposed biasing scheme, the circuit consumes 45% less biasing current with 16% better settling time as compared to the non-adaptive biased circuit. The proposed biasing circuit and liquid-crystal displays (LCD) buffer is designed using 0.35 µm AMS technology and the SPICE results are reported. The circuit provides high slew-rate and good settling time characteristics which is comparable to the state-of-art LCD driving circuits. [ABSTRACT FROM AUTHOR]

This paper presents an ultra-low-power and high-gain low-dropout (LDO) regulator. It is based on the flipped voltage follower cell with an adaptive biasing technique that is suitable for implantable biomedical applications. The error amplifier for the proposed regulator consists of two cross-coupled common-gate cells and a pseudo-folded-cascode structure to increase the regulator's loop gain. In addition, three different compensation techniques including Miller, cascode, and Q-reduction are simultaneously utilized at the LDO regulator to achieve high stability despite having the minimum load current and ultra-low power consumption. The proposed LDO regulator has been simulated in TSMC 90-nm CMOS technology with minimum power consumption of 2.8 µW at no load. Post-layout simulation results show that the proposed LDO regulator is stable over load currents from 30 µA to 40 mA with a maximum on-chip CL of 100 pF. Moreover, the voltage regulator settles in less than 850 ns at 0.75 V output voltage that is achieved in response to a load transient step of 40 mA with a rise time of 200 ns. Besides, the obtained line and load regulations are significantly improved to 1 mV/V and 36 µV/mA, respectively. [ABSTRACT FROM AUTHOR]

Summary: A sense field effect transistor (FET)–based inductor‐current sensor for buck converters is introduced in this paper. The proposed current sensor adopts and realizes piecewise‐linear adaptive bias to maintain consistent bandwidth and phase margin in the sensor's control loop throughout a wide range of load currents. Moreover, the specially designed turn‐on/off process of switches is introduced together with the sole gain–boosted amplifier to avoid the sharp transitions in the sensed peak and valley currents during the deadtime zone of synchronous buck converters. Simulation results of the proposed sensor show an 11.6‐dB rise in direct current (DC) gain at light load (approximately 200 mA) and 21° improvement in phase margin at heavy load (approximately 2 A), compared with the traditional structure with fixed‐bias current. Furthermore, the variation in the unity gain bandwidth of the proposed structure across the whole load range is 12.8 times lower than that of the traditional designs. [ABSTRACT FROM AUTHOR]

An area efficient output capacitor-free low dropout [LDO] voltage regulator with an improved figure of merit is presented in this paper. The proposed LDO regulator consists of a novel, dynamically biased error amplifier that reduces overshoot and undershoot voltage spikes arising from abrupt load changes. Source bulk modulation is employed to enhance the current driving capability of the pass transistor. An adaptive biasing scheme is also used along with dynamic biasing to improve the current efficiency of the system. The on-chip capacitor required for proper working of the LDO regulator is only 35 pF. The proposed LDO regulator is designed and simulated in 180 nm standard CMOS technology. The LDO regulator exhibits a line regulation of 1.67 mV/V and a load regulation of 100 µV/mA. When load changes from 0 mA to 100 mA in 1 µs, an undershoot of 148 mV and an overshoot of 172 mV are observed. The measured power supply rejection ratio is 25 dB at 100 kHz. The working of the proposed LDO regulator has been tested under all process corners and Monte-Carlo statistical analysis reveals that it is robust against process variations and local mismatch. [ABSTRACT FROM AUTHOR]

A 1.9-GHz linear CMOS power amplifier is presented. An adaptive bias circuit (ABC) that utilizes an AC ground to detect the power level of the input signal is proposed to enhance the linearity and efficiency of the power amplifier. The ABC utilizes the second harmonic component as the input to mitigate the distortion of the fundamental signal. The input power level of the ABC was detected at the AC ground located at the VDD node of the power amplifier. The output of the ABC was fed into the inputs of the power stage. The input signal distortion was mitigated by detecting the input power level at the AC ground. The power amplifier was designed using a 180 nm RFCMOS process to evaluate the feasibility of the application of the proposed ABC in the power amplifier. The measured output power and power-added efficiency were improved by 1.7 dB and 2.9%, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a low quiescent current, fast settling time, and adaptively biased capacitor less lowdropout (LDO) regulator. The topology involves a segmented pass transistor with bulk modulation and adaptively biased current control stages to improve the transient performance. The bulk modulation of the pass transistor assists in fast settling of the output voltage. The frequency compensation makes the LDO voltage regulator stable adaptively over load current transitions. In addition, the biasing stage is designed such that it adapts to the load transitions while consuming the quiescent current abstemiously. This arrangement further improves settling time to be within 1 μs while restricting undershoot/overshoot to 171 mV/82 mV for a load current transition between 0 and 100 mA with load capacitor of 40 pF. The LDO regulator is designed using 0.18 μm UMC CMOS process by consuming 1.5 μA quiescent current at no loads. [ABSTRACT FROM AUTHOR]

This paper presents a class-AB amplifier with enhanced transconductance and slew rate using adaptive biasing technique and new drivers. The adaptive biasing configuration provides a tail current linked to the input signal in order to increase the slew rate during slewing phase. In addition, the new structure benefits from new drivers to enhance the transconductance which are supported by adaptive biasing configuration. These enhancement techniques lead to the input and output class-AB operations for fast settling applications. The proposed structure is simulated in 65-nm complementary metal-oxide semiconductortechnology which shows a 16.2-dB enhancement in the DC gain and a 72% reduction in the settling time compared to the conventional structure. [ABSTRACT FROM AUTHOR]

Supply regulation using low quiescent current linear regulators helps in extending the battery life of power aware applications with very long standby time. A 1.24 $\mu \text{A}$ quiescent current NMOS low dropout (LDO) that uses a hybrid bias current generator (HBCG) which boosts the bias current dynamically and adaptively to improve the transient response is presented in this paper. A bias-current scalable error amplifier with an on-demand pull-up/pull-down buffer drives the NMOS pass device. The error amplifier is powered with an integrated dynamic frequency charge pump to ensure low dropout voltage. A low-power relaxation oscillator (LPRO) generates the charge pump clocks. A novel switched-capacitor pole tracking (SCPT) compensation scheme is proposed to ensure stability up to maximum load current of 150 mA with a low-ESR 1 $\mu \text{F}$ output capacitor. Designed in a 0.25 $\mu \text{m}$ CMOS process, the LDO has an output voltage range of 1–3 V, a dropout voltage of 240 mV, and a core area of 0.11 mm2. [ABSTRACT FROM AUTHOR]

A fully-integrated switched-capacitor (SC) DC-DC converter that steps down 2.0 V to 0.9 V with a peak efficiency of 80% is implemented in a 0.18 μ m CMOS process. An ultra-low-power voltage-controlled oscillator that generates a wide range of switching frequencies is proposed to extend battery runtime. An efficiency >70% for load currents in the range of 12 μ A to 17.8 mA is achieved by implementing a novel adaptively-biased pulse frequency modulation (ABPFM) technique in the controller. A symmetric charge-discharge topology with two-phase time interleaving is used as a power stage to reduce the output voltage ripple to

This paper presents a low-voltage high driving capability rail-to-rail Class-AB CMOS bulk-driven (BD) operational transconductance amplifier (OTA) for analog voltage buffer with minimal current consumption. The proposed OTA design consists of adaptively biased Class-AB differential input stage to improve the effective transconductance and adaptive load relying on nonlinear current mirrors, configured in partial positive feedback mode to enhance the overall gain. In addition, because of adaptive bias and load configuration, the load-driving capability of OTA increases for a large change in differential input. The circuit is designed using UMC 65-nm CMOS process node and is operated at supply voltage of 0.5 V with a standby current consumption of 4.25 $$\upmu $$ A. Simulation results show that the buffer based on the proposed BD-OTA achieves an average slew rate of 93.2 mV/ $$\upmu $$ s for a capacitive load of 100 pF, which is nearly 29 times that of conventional OTA with 13 $$\%$$ increment in quiescent power dissipation. [ABSTRACT FROM AUTHOR]

A novel fully on-chip low dropout (LDO) linear regulator with a supply voltage of 1.6V, dropout voltage of 200mV and a quiescent current of 64.4A is presented in this paper. The slew rate limitations of conventional low dropout regulator (LDR) employing folded cascode structure are overcome by fixed bias LDR (FB LDR) with the usage of recycled transistors of conventional LDR. The FB LDR with its limited input common mode range limits the transient response. The adaptive bias LDR (AB LDR) overcomes these limitations of FB LDR and further enhances the transient performance. However, fast rise and fall time demands of advanced digital technology demand the regulator to respond to corresponding fast load changes. These challenges are addressed by an additional fast reacting path. An undershoot of 89.95mV for a load current changes from 0mA to 100mA and an overshoot of 150.1mV for a current change of 100-0mA is observed for the adaptive bias transient enhanced LDR. The load regulation of 20.6V/mA and power supply rejection (PSR) of 47.8dB@ 10kHz is achieved due to the improved closed loop gain and bandwidth of LDR. The standard 180nm UMC CMOS process is employed. [ABSTRACT FROM AUTHOR]

A linear-switch mode hybrid envelope tracking (ET) supply modulator utilizing adaptive biasing and gain enhanced current mirror operational transconductance amplifier (OTA) with class AB output stage in parallel with a switching regulator is presented. In comparison to a conventional OTA design with similar quiescent current consumption, proposed approach improves positive and negative slew rate from 50 to 93.4 V/ \mu \texts and −87 to −152.5 V/ \mu \texts , respectively, dc gain from 45 to 67 dB while consuming same amount of quiescent current. The proposed hybrid supply modulator achieves 83% peak efficiency, power-added efficiency (PAE) of 42.3% at 26.2 dBm for a 10-MHz 7.24-dB peak-to-average power ratio (PAPR) long-term evolution (LTE) signal and improves PAE by 8% at 6 dB back off from 26.2-dBm power amplifier (PA) output power with respect to fixed supply. With a 10-MHz 7.24-dB PAPR quadrature-phase shift keying LTE signal the ET PA system achieves adjacent channel leakage ratio (ACLR) of −37.7 dBc and error vector magnitude (EVM) of 4.5% at 26.2-dBm PA output power, while with a 10-MHz 8.15-dB PAPR 64QAM LTE signal the ET PA system achieves ACLR of −35.6 dBc and EVM of 6% at 26-dBm PA output power without digital predistortion. The proposed supply modulator core circuit occupies 1.1-mm2 die area, and is fabricated in a 0.18- \mu \textm CMOS technology. [ABSTRACT FROM AUTHOR]

This paper presents a tunable linear OTA based on an improved adaptive biasing of degeneration triode-mode transistor and a new technique for compensating the linearity degradation due to the tuning action. Using the adaptive biasing circuit, the degeneration resistance is modulated such that to make constant transconductance in a wide range of input voltages. As the linearity would be lost at higher values of transconductance, a tune-dependent current is injected to the adaptive biasing circuit to remove the nonlinearities of OTA's second stage. Using 1.8 V supply voltage, the proposed OTA consumes 600 μ W in which the portion of adaptive biasing and the tune compensation circuits is 37 μ W . When a 0.9 Vp-p, 10 MHz input voltage is applied to the OTA which is tuned at highest G m , HD 3 decrement due to using adaptive biasing circuit is 3.7 dB, while it reduces to 11.3 dB due to using both adaptive biasing and tune compensation circuits. [ABSTRACT FROM AUTHOR]

In this paper, a robust low quiescent current complementary metal-oxide semiconductor (CMOS) power receiver for wireless power transmission is presented. This power receiver consists of three main parts including rectifier, switch capacitor DC–DC converter and low-dropout regulator (LDO) without output capacitor. The switch capacitor DC–DC converter has variable conversion ratios and synchronous controller that lets the DC–DC converter to switch among five different conversion ratios to prevent output voltage drop and LDO regulator efficiency reduction. For all ranges of output current (0–10 mA), the voltage regulator is compensated and is stable. Voltage regulator stabilisation does not need the off-chip capacitor. In addition, a novel adaptive biasing frequency compensation method for low dropout voltage regulator is proposed in this paper. This method provides essential minimum current for compensation and reduces the quiescent current more effectively. The power receiver was designed in a 180-nm industrial CMOS technology, and the voltage range of the input is from 0.8 to 2 V, while the voltage range of the output is from 1.2 to 1.75 V, with a maximum load current of 10 mA, the unregulated efficiency of 79.2%, and the regulated efficiency of 64.4%. [ABSTRACT FROM PUBLISHER]

This paper presents a hybrid-mode, operational transconductance amplifier (HM-OTA) to improve the dynamic response of an adaptively biased low dropout regulator (AB-LDR) while maintaining a low quiescent current. Using the proposed HM-OTA in the AB-LDR, we can achieve higher dc gain and wider loop bandwidth compared to a conventional current-mode OTA (CM-OTA). Additionally, the proposed HM-OTA provides a high discharging slew-rate at the gate of the PMOS power transistor during a low-to-high load step. So, the proposed HM-OTA helps to achieve a good dc load regulation as well as a reduced undershoot during load transient. At the same time, the regulator requires a small value of the output capacitor for achieving the loop stability compared to the conventional differential-mode OTA (DM-OTA). The conventional CM-OTA and the DM-OTA turn out to be special cases of the proposed HM-OTA that does not occupy extra space in silicon or consume additional power to realize. The AB-LDR using the proposed HM-OTA has been implemented in 0.18-\mum CMOS technology. The regulator consumes a quiescent current of 1.6-\muA at the no-load condition with a transient variation of 24 mV at Vo = 1.2 V for 0–50 mA of load step with a 1- \muF output capacitor. [ABSTRACT FROM PUBLISHER]

This paper presents a high slew-rate operational transconductance amplifier (OTA) based on a non-linear current mirror which dramatically reduces the quiescent current. The proposed circuit achieves less quiescent current than previously proposed architectures since no additional bias branches are needed. The compactness of the proposed architecture does not require so much silicon area as other more complex adaptive bias architectures. The proposed technique is compared with previous state of the art high slew-rate architectures. Additionally, this novel architecture was used to design a non-symmetrical OTA which was part of the feedback loop of a switched-capacitor DC-DC converter. This OTA occupies 420 μm fabricated in a 130 nm technology. Measurements results are presented showing that a slew-rate enhancement, from 1.5 to 535 mV/μs, is achieved in an OTA biased with 50 nA and loaded with 50 pF. [ABSTRACT FROM AUTHOR]

Single-stage regulator topologies are often preferred in embedded applications due to their low power consumption with a single-pole behavior, resulting in easy frequency compensation. Since the achievable differential gain from a single stage is low, the dc load regulation is poor over a wide dynamic range. This paper presents a single-stage, adaptively biased, low-dropout regulator to achieve a comparable dc load regulation similar to multistage topologies. This is achieved mainly by modifying the adaptive bias loop which amplifies both the common-mode and differential-mode signals. In addition, as the proposed regulator is stable for a wide range of output capacitors, including the capacitor-less (on-chip) and with-capacitor (off-chip) conditions, it is suitable for more generic applications. The proposed regulator is implemented in a standard 0.18- \mu \textm CMOS technology. The experimental results show that the regulator is capable of delivering up to 100 mA with a dc load regulation of 0.140 mV/mA and is stable with Co\leq 3.3 nF (capacitor-less) and Co\geq 1~\mu \text{F} (with-capacitor). [ABSTRACT FROM AUTHOR]

A current-efficient, capacitor-less low-dropout regulator (LDO) with fast-transient response for portable applications is presented in this paper. It makes use of an adaptively biased common-gate amplifier to extend loop bandwidth of the LDO at heavy loads. Moreover, a dynamic transconductance enhancement circuit based on capacitive coupling detects rapid voltage spikes at the output, providing an extra large current to charge or discharge the gate capacitance of power transistor momentarily during transient. The proposed circuit has been implemented in a 0.35 µm standard CMOS process. Experimental results show that this fully-integrated LDO can deliver 100 mA load current at 200 mV dropout voltage. It only consumes 15 μA quiescent current and is able to recover within 1 µs under the maximum load current change, with undershoot/overshoot voltages controlled below 250 mV. Loop stability is kept well at light loads ( I = 100 μA) even when a 100 pF output-parasitic capacitor is applied. [ABSTRACT FROM AUTHOR]

High performance of fully differential operational transconductance amplifier is designed and implemented using a 0.18-μm CMOS process. The implemented op-amp uses common mode feedback (CMFB) circuit operating in weak inversion region which does not affect other electrical characteristics due to eliminating common mode (CM) levels automatically leading to improve CM rejection ratio (CMRR) of the amplifier significantly. Moreover, the output stage has class-AB operation so that its current can be made larger due to increasing the output current dynamically using adaptive biasing circuit. Additionally, the AC currents of the active loads have been significantly reduced using negative impedances to increase the gain of the amplifier. The results show the GBW 2.3 MHz, slew rate 2.6 V/μs and 1% settling time 150 ns with a capacitive load of 15 pF. This amplifier dissipates only 6.2 μW from a 1.2 V power supply. [ABSTRACT FROM AUTHOR]

A fully integrated power delivery system with distributed on-chip low-dropout (LDO) regulators developed for voltage regulation in portable devices and fabricated in a 28 nm CMOS process is described. Each LDO employs adaptive bias for fast and power efficient voltage regulation, exhibiting 64 ps response time of the regulation loop and 99.49 % current efficiency. An adaptive compensation network is also employed within the distributed power delivery system to maintain a stable system response within 25 to 105 °C and 10 % voltage variations with a capacitive load of more than 472 pF. No off-chip capacitors are required. Under a 788 mA load current step with 5 ns load edge, the power delivery system exhibits less than 15 % voltage droop for nominal input and output voltages, and a minimum dropout of 0.1 V. Each of the LDO regulators with the adaptive networks and bias current generator occupies 85 μm × 42 μm in a 28 nm CMOS process. All of the test measurements are performed in a distributed power delivery system of six on-chip LDO regulators within a commercial high performance portable device. The proposed system is the first successful silicon demonstration of stable fully integrated parallel analog LDO regulators. [ABSTRACT FROM AUTHOR]

This paper presents a novel linearization technique for a transconductance amplifier. Resistive source degeneration as commonly used technique for linearization of the differential pairs suffers from input-dependent variations in degeneration resistance when passive resistor is substituted by active counterpart to achieve lower area usage and tuning ability. The proposed technique is based on using an auxiliary circuit to adaptively bias degenerative transistors to reduce the resistance nonlinearity caused by applying input voltage. The proposed transconductor employs $$\pm $$ 0.9 V power supply and totally consumes 139.2 $$\upmu $$ W in which the portion of auxiliary circuit including tuning circuit is only 17 %. Simulation results in 0.18 $$\upmu $$ m TSMC technology by Hspice simulator indicate 13.2 dB reduction in the third-order harmonic distortion of proposed transconductor's output current compared with conventional case, when a 1.2 Vp-p input voltage is applied at 10 MHz frequency. The corner case and Monte Carlo simulations verify the robustness of the proposed technique against the fabrication process errors. [ABSTRACT FROM AUTHOR]

This paper presents a two-stage power-efficient class-AB operational transconductance amplifier (OTA) based on an adaptive biasing circuit suited to low-power dissipation and low-voltage operation. The OTA shows significant improvements in driving capability and power dissipation owing to the novel adaptive biasing circuit. The OTA dissipates only 0.4 µW from a supply voltage of ±0.6 V and exhibits excellent high driving, which results in a slew rate improvement of more than 250 times that of the conventional class-AB amplifier. The design is fabricated using 0.18-µm CMOS technology. [ABSTRACT FROM AUTHOR]

A 60-GHz Doherty power amplifier (PA) implemented in 65-nm bulk CMOS process is proposed. A novel adaptive biasing network is devised to dynamically adjust the bias voltage of the peaking PA, counteracting its low transconductance caused by the class-C biasing condition. At 60 GHz, the fabricated Doherty PA achieves 22% drain efficiency with a saturation power of 13.2 dBm. The measured results show that over 17% and 8% efficiencies at peak and 6-dB back-off power regions are achieved, respectively, from 57 to 64 GHz. [ABSTRACT FROM PUBLISHER]

This paper presents a modified design method for linear transconductor circuit in 130 nm CMOS technology to improve linearity, robustness against process induced threshold voltage variability and reduce harmonic distortion. Source follower in the adaptively biased differential pair (ABDP) linear transconductor circuit is replaced with flipped voltage follower to improve the efficiency of the tail current source, which is connected to a conventional differential pair. The simulation results show the performance of the modified circuit also has better speed, noise performance and common mode rejection ratio compared to the ABDP circuit. [ABSTRACT FROM AUTHOR]