Search

Refrigeration systems based on cooling towers and chillers are widely used equipment in industrial buildings, such as shopping centers, gas and oil refineries and power plants, among many others. Cooling towers are used to recover the heat rejected by the refrigeration system. In this work, the refrigeration is composed of cooling towers dotted with ventilators and compression chillers. The growing environmental concerns and the current scenario of scarce water and energy resources have lead to the adoption of actions to obtain the maximum energy efficiency in such refrigeration equipment. This backs up the application of computational intelligence to optimize the operating conditions of the involved equipment and cooling processes. In this context, we utilize multi-objective optimization algorithms to determine the optimal operational setpoints of the cooling system regarding the cooling towers, its fans and the included chillers. We use evolutionary multi-objective optimization to provide the best trade-offs between two conflicting objectives: maximization of the effectiveness of the cooling towers and minimization of the overall power requirement of the refrigeration system. The optimization process respects the constraints to guarantee the correct and safe operation of the equipment when the evolved solution is implemented. In this work, we apply three evolutionary multi-objective algorithms: Non-dominated Sorting Genetic Algorithm (NSGA-II), Micro-Genetic Algorithm (Micro-GA) and Strength Pareto Evolutionary Algorithm (SPEA2). The results obtained are analyzed under different scenarios and models of the cooling system's equipment, allowing for the selection of the best algorithm and best equipment's model to achieve energy efficiency of the studied refrigeration system. [ABSTRACT FROM AUTHOR]

This work presents a novel approach to quantum computing by proposing a customizable hardware design of a dedicated processor that emulates the execution of quantum algorithms. Unlike software-based quantum computation simulators, which run on standard general-purpose computers and suffer from reduced performance, this hardware design, which is based on classical concepts of bits, registers and memories, aims to leverage pure parallelism and pipelined execution for efficient quantum computations via emulation. The architecture includes several key components: memories, computation unit, measurement unit and control unit. The quantum state memory stores the individual and group states of qubits. This memory is crucial for maintaining the quantum information required for quantum operations. Basic operators are stored in dedicated operator memory. Additionally, a scratch memory allows for larger operators to be dynamically built at runtime. The computation unit is responsible for performing complex number multiplications, which form the basis of tensor and matrix products necessary for executing quantum operations. A measurement unit enables quantum state sampling, which is an essential aspect of quantum computation. Furthermore, a control unit is incorporated to ensure the correct operation of the quantum processor's data path. It utilizes a microprogram to manage and coordinate the functional units. All the functional units communicate with each other through dedicated and shared data buses, depending on the frequency of information exchange. This enables efficient data transfer and coordination among the components. The proposed hardware design has been simulated and proved to be effective in executing quantum operations. By exploiting parallelism and employing a pipelined execution, this architecture overcomes the limitations of software-based simulators, delivering improved performance for emulating quantum algorithms. We use Grover's search algorithm as a benchmark to evaluate the performance of the proposed hardware design and compare it to software-based simulation and to hardware-based algorithm-dedicated emulation. [ABSTRACT FROM AUTHOR]

Modular exponentiation is a basic operation in various applications, such as cryptography. Generally, the performance of this operation has a tremendous impact on the efficiency of the whole application. Therefore, many researchers have devoted special interest to providing smart methods and efficient implementations for modular exponentiation. One of these methods is the sliding-window method, which pre- processes the exponent into zero and non-zero partitions. Zero partitions allow for a reduction of the number of modular multiplications required in the exponentiation process. In this paper, we devise a novel hardware for computing modular exponentiation using the sliding-window method. The partitioning strategy used allows variable-length non-zero partitions, which increases the average number of zero partitions and so decreases that of non-zero partitions. It performs the partitioning process in parallel with the pre-computation step of the exponent so no overhead is introduced. The implementation is efficient when compared against related existing hardware implementations. [ABSTRACT FROM AUTHOR]

Abstract: In this paper, we propose a massively parallel architecture for hardware implementation of genetic algorithms. This design is quite innovative as it provides a viable solution to the fitness computation problem, which depends heavily on the problem-specific knowledge. The proposed architecture is completely independent of such specifics. It implements the fitness computation using a neural network. The hardware implementation of the used neural network is stochastic and thus minimise the required hardware area without much increase in response time. Last but not least, we demonstrate the characteristics of the proposed hardware and compare it to existing ones. [Copyright &y& Elsevier]

Abstract: Modular exponentiation is an important operation in several public-key cryptosystems. It is performed using successive modular multiplications. For the sake of efficiency, one needs to reduce the total number of required modular multiplications. In this paper, we propose two efficient hardware implementations for computing modular exponentiations, which are based on the m-ary method. The m-ary method includes a power pre-computation step. The first design ignores the exponent and pre-computes all possible powers while the second takes advantage of the formation of the exponent to compute only those powers that are really necessary for the rest of the computation. As it can be expected, the implementation of the first architecture, compared with that of the second one, requires more time to complete an exponentiation. In compensation, however, the first should require less hardware area than the second. We provide a comparison of these two implementations using the performance factor, which takes into account both space and time requirements. [Copyright &y& Elsevier]

Abstract: Most of cryptographic systems are based on modular exponentiation, wherein the operands are considerably large. Generally, modular exponentiation is implemented using a chain of modular multiplications. One way of improving the throughput of a cryptographic system implementation is reducing the number of the required modular multiplications. Given the exponent, finding the minimal number of multiplications that are necessary to reach the exponentiation results is a hard problem. We take advantage of an evolutionary stochastic process, commonly called genetic algorithms, to compute minimal addition chains, allow us to reduce drastically the number of the required modular multiplications. In this paper, we investigate two different ways to implement modular exponentiation based on the evolved addition chain: the first approach consists of implementing all the exponentiation operation on hardware and the second approach combines software and hardware. While the first approach attempts to optimise the encryption/decryption throughput regardless of the cost of system implementation, the second attempts to reach a balance between the throughput and the cost of the implementation. [Copyright &y& Elsevier]

In this paper, genetic programming is used as an alternative means to automatically generate secure and minimal hardware designs of public-key cryptosystems such as the RSA cryptosystem. We evolve optimal hardware circuits for modular exponentiation, which is a cornerstone operation in many public-key cryptographic system. The evolved circuits minimize both space (i.e. required gate number) and time (i.e. encryption and decryption time). The evolved designs are shielded against side-channel leakage and hence secure. The structure of the cryptographic circuit is random and so the private key cannot be deduced using known attacks. We compare our results against existing well-known designs, which were produced by human designers based on the binary method. [ABSTRACT FROM AUTHOR]

Modular multiplication and modular exponentiation are fundamental operations in most public-key cryptosystems such as RSA. In this paper, we propose a novel implementation of these operations using systolic arrays based architectures. For this purpose, we use the Montgomery algorithm to compute the modular product and the left-to-right binary exponentiation method to yield the modular power. In the proposed design, we invest hardware area in the hope of improving encryption/decryption throughput. Our implementation improves time requirement as well as the time area factor when compared that of Blum’s and Paar’s. [Copyright &y& Elsevier]

The automatic speech recognition based on detection of phonemes provides advantages for online recognition of a speech represented by a sound signal. The development of a system for automatic speech recognition is multidisciplinary. It covers several areas of research, such as linguistics, signal processing and computational intelligence. In this work, the process starts with a speech signal pre-processing to extract the main features of the speech signal at a given instant of time. Inspired by the "divide and conquer" principle, we bridge the complexity gap of automatic speech recognition by devising models based on an ensemble of neural network experts, allowing to divide the huge decision space regarding speech recognition so that each expert takes care only of a delimited area of this decision space. This novel application of this strategy improves the precision, sensitivity and accuracy of the recognition process. Each included expert decides regarding each one of the pre-processed input samples. The decision set thus obtained is weighted. So, the expert with the highest weight for the output will determine the sample final classification. After that, a dynamic post-processing step, implemented as a recurrent neural network, is executed. It aims at mitigating the oscillatory effect that occurs during the recognition of classes with similar characteristics. In this work, two ensembles are investigated. The first is based on the clustering of similar phonetics classes while the second takes care of the imbalanced distribution of samples in the training set. The proposed model achieves 7.63% improvement in terms of accuracy with respect to the best so far related model for automatic speech recognition. • It provides an online tool for Automatic Speech Recognition for Portuguese language. • An ensemble of expert neural networks is explored, dividing the decision. • Expert only takes care of a well-delimited area of this decision space. • Two models are proposed: (1) grouping similar phonetics; (2) unbalanced dataset. • A dynamic post-processing using an RNN is performed, mitigating of output oscillatory effects. [ABSTRACT FROM AUTHOR]

Particle swarm optimization (PSO) is an evolutionary heuristics-based method used for continuous function optimization. Compared with existing stochastic methods, PSO is very robust. Nevertheless, for real-world optimizations, it requires a high computational effort. In general, parallel implementations of PSO provide better performance. However, this depends heavily on the parallelization strategy engineered as well as the number and characteristics of the exploited processors. In this paper, we analyze three different parallelization strategies: a Particle-oriented Strategy (PoS); a Dimension-oriented Strategy (DoS) and a Cooperation-oriented Strategy (CoS). PoS parallelizes the particle's work. DoS focuses on the work done with respect to each of the problem dimensions and does it in parallel. CoS subdivides the optimization problem into many simpler subproblems, each of which focuses on a distinct subset of the original problem dimensions. The optimization work for all the yielded subproblems is done in parallel. Note that in the second and third strategies, all particles act in parallel too. We map the three strategies onto a Graphics Processing Units (GPU)-based architecture. The performance of the implementations is evaluated using four benchmark functions, considering high-dimension instances. We compare the speedups achieved by the GPU-based implementations of the considered parallelization strategies to the reference sequential PSO implementation as well as to existing PSO implementation on Graphics Processing Units. [ABSTRACT FROM AUTHOR]

The localization problem arises from the need of robots of a swarm robotic system (SRS), or even nodes of a wireless sensors network (WSN), to determine their positions without the use of external references, such as the Global Positioning System (GPS). In this problem, the node location may be established thanks to distance measurements to existing reference nodes, using a range-based method. Reference nodes know their respective positions in the network. In the search for efficient yet accurate methods to determine node locations, some bio-inspired algorithms have been explored. In this sense, targeting a more accurate solution of the localization problem, we propose a new multi-hop method. Two algorithms were developed considering the proposed method: one based on the Particle Swarm Optimization (PSO), and the other based on the Backtracking Search Algorithm (BSA). The method includes a new technique to assess the confidence that should be granted to a contribution received from a neighboring node, and hence incorporating it into the localization computation accordingly. The achieved performance results prove the effectiveness of the proposed method in which the BSA-based algorithm has a performance better than the PSO-based algorithm. Also, the results evince the efficiency entailed by the confidence factor assessment technique, for some network configurations. The impact of the latter is more evident when the number of reference nodes in the network is reduced. This constitutes a very big advantage with respect to state-of-the-art localization methods. [ABSTRACT FROM AUTHOR]

Dynamic task allocation in a robotic swarm is a necessary process for proper management of the swarm. It allows the distribution of the identified tasks to be performed, among the swarm of robots, in such a way that a pre-defined proportion of execution of those tasks is achieved. In this context, there is no central figure to take care of the task allocation. So any algorithm proposal must be distributed, allowing every and each robot in the swarm to identify the task it must perform. This paper proposes a simple yet efficient distributed control algorithm to implement dynamic task allocation in a robotic swarm. In this algorithm, each robot that integrates the swarm runs the algorithm whenever it senses a change in the environment. The algorithm was implemented and extensively tested in different size swarms of robots. The corresponding performance and effectiveness are promising, as shown in the presented results and comparison. The swarm robot used is Elisa-III. [ABSTRACT FROM AUTHOR]

With the increasing of the integration capability intra-chip, nowadays numerous integrated systems explore a set ofprocessing elements, such as in multicore processors. An efficient interconnection of those elements can be obtained via the use ofNetwork on chip(NoC). This approach is similar to the traditional computer networks where, not restricted to multiprocessors, it is possible to interconnect several dedicated devices. Like other networks, NoCs can be arranged in different topologies, such as ring, mesh and torus. It has shared links that can be used in the transmission of packets of different nodes. Thus, the network congestion is an issue and must be treated to reduce delays. Algorithms based on ant colony optimisation have proven to be effective in static routing in systems designed to perform a fixed set of tasks, or where the communication pattern is known. This article introduces 3D ant colony routing (3D-ACR) and applies it as routing policy of NoCs having three different 3D topologies: mesh, torus and hypercube. Experimental results show that 3D ant colony routing performs consistently better compared with the previously proposed routing strategies. [ABSTRACT FROM PUBLISHER]

Nowadays, final products often encompass a certain intelligence therein to deal with variation or lack of precision in the sensing input data. This intelligence is usually acquired via the utilization of existing soft techniques, such as artificial neural networks, genetic algorithms and fuzzy control, among others. Thus, it is profitable to have on-the-shelf shell scalable and adaptive hardware designs that implement these soft techniques. This availability allows for an immediate embedding of any of those designs onto final products. This usually entails a reduced time-to-market of the product. Process control is one of the many applications that took advantage of the fuzzy paradigm. In general, controllers are embedded into the controlled device. This paper presents a novel design of a reconfigurable efficient parallel architecture to implement fuzzy controllers on hardware with almost no design effort for final users. The proposed architecture is herein proven suitable for embedding. It is customizable, so it allows the setup and configuration of the controller parameters, and hence its use for any problem application. Two fuzzy controllers that model autonomous car driving are implemented and their cost and performance evaluated. [ABSTRACT FROM AUTHOR]

Highlights: [•] Two novel congestion-aware algorithms based on ACO adapted to the routing problem. [•] An adaptive and static routing. [•] The proposed algorithms overcome the congested routes. [•] The found solutions improve the execution time of applications mapped onto Network-on-Chip. [ABSTRACT FROM AUTHOR]

Abstract: DNA sequence matching is used in the identification of a relationship between a fragment of DNA and its owner by mean of a database of DNA registers. A DNA fragment could be a hair sample left at a crime scene by a suspect or provided by a person for a paternity exam. The process of aligning and matching DNA sequences is a computationally demanding process. In this paper, we propose a novel parallel hardware architecture for DNA matching based on the steps of the BLAST algorithm. The design is scalable so that its structure can be adjusted depending on the size of the subject and query DNA sequences. Moreover, the number of units used to perform in parallel can also be scaled depending some characteristics of the algorithm. The design was synthesized and programmed into FPGA. The trade-off between cost and performance were analyzed to evaluate different design configuration. [Copyright &y& Elsevier]

Abstract: Radioactivity is the spontaneous emission of energy from unstable atoms. Radioactive sources have radionuclides. Radionuclide undergoes radioactive decay and emits gamma rays and subatomic particles, constituting the ionizing radiation. The gamma ray energy of a radionuclide is used to determine the identity of gamma emitters present in the source. This paper describes the hardware implementation of subtractive clustering algorithm to perform radionuclide identification. The hardware was proven to be effective for this task, allowing scalability to increase parallelism in the computations. [Copyright &y& Elsevier]

Abstract: There are several neural network implementations using either software, hardware-based or a hardware/software co-design. This work proposes a hardware architecture to implement an artificial neural network (ANN), whose topology is the multilayer perceptron (MLP). In this paper, we explore the parallelism of neural networks and allow on-the-fly changes of the number of inputs, number of layers and number of neurons per layer of the net. This reconfigurability characteristic permits that any application of ANNs may be implemented using the proposed hardware. In order to reduce the processing time that is spent in arithmetic computation, a real number is represented using a fraction of integers. In this way, the arithmetic is limited to integer operations, performed by fast combinational circuits. A simple state machine is required to control sums and products of fractions. Sigmoid is used as the activation function in the proposed implementation. It is approximated by polynomials, whose underlying computation requires only sums and products. A theorem is introduced and proven so as to cover the arithmetic strategy of the computation of the activation function. Thus, the arithmetic circuitry used to implement the neuron weighted sum is reused for computing the sigmoid. This resource sharing decreased drastically the total area of the system. After modeling and simulation for functionality validation, the proposed architecture synthesized using reconfigurable hardware. The results are promising. [Copyright &y& Elsevier]

Abstract: Network-on-chip (NoC) are considered the next generation of communication infrastructure in embedded systems. In the platform-based design methodology, an application is implemented by a set of collaborative intellectual property (IP) blocks. The selection of the most suited set of IPs as well as their physical mapping onto the NoC infrastructure to implement efficiently the application at hand are two hard combinatorial problems that occur during the synthesis process of Noc-based embedded system implementation. In this paper, we propose an innovative preference-based multi-objective evolutionary methodology to perform the assignment and mapping stages. We use one of the well-known and efficient multi-objective evolutionary algorithms NSGA-II and microGA as a kernel. The optimization processes of assignment and mapping are both driven by the minimization of the required silicon area and imposed execution time of the application, considering that the decision maker’s preference is a pre-specified value of the overall power consumption of the implementation. [Copyright &y& Elsevier]

Abstract: Network-on-chips (NoC) is considered the next generation of communication infrastructure in embedded systems, which are omnipresent in different environments, such as cars, cell phones, and digital cameras. In the platform-based design methodology, an application is implemented by a set of collaborating intellectual properties (IPs) blocks. The selection of the most suited set of IPs as well as their physical mapping onto the NoC infrastructure to implement efficiently the application at hand are two hard combinatorial problems. In this paper, we propose the use of multi-objective evolutionary algorithms to perform the assignment and mapping stages of any given application on a customized NoC infrastructure. The resulting NoC platform is custom-cut for the application at hand. Only the actually used resources, switches and channels by the application mapping are part of the customized implementation platform. The optimization is driven by the minimization of required hardware area, the imposed execution time and the necessary power consumption of the final implementation, and yet avoiding hot spots. [Copyright &y& Elsevier]