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This paper investigates the impacts of typical semiconductor material properties—electron affinity, bandgap, and dielectric constant, on the electrical performance of a p-type core–shell heterojunction nanowire FET by numerical simulations. At the heterojunction, a valence band offset of 200 meV forms a sufficient energy barrier confining the holes in the quantum well, resulting in the optimal OFF-state current. A higher dielectric constant of the shell region is found to be able to decrease the leakage current of the device. The optimum conditions from the parameter analysis are demonstrated by a realistic and achievable material combination of Si/SiGe for the core–shell configuration. This paper provides physical insights into the materialwise impacts for designing the proposed transistor showing the reduced OFF-current and a better subthreshold swing for low-power applications. [ABSTRACT FROM PUBLISHER]

This paper proposes a new dynamic behavior model for single-electron transistors (SETs). A comprehensive review of modeling techniques and previous models was carried out aiming to remark the originality of the new proposed technique. Once established that SET is a nonlinear system, five classes of nonlinear models were simulated and compared to each other. Characteristic SET curves obtained using Simulation of Nanostructures were used as benchmark. The mean squared error (mse) was used as metric, and the simulation time was computed for each model. Regarding these two criteria—least mse and least simulation time—the Hammerstein–Wiener model outperformed the others models. [ABSTRACT FROM AUTHOR]

In advanced technology nodes, an increase in power density, use of nonplanar architectures, and novel materials can aggravate local self-heating due to active power dissipation. In this paper, 3-D device simulations are performed to analyze thermal effects in fin-shaped field-effect transistors (FinFETs) and stacked-nanowire FETs (NWFETs). Based on empirically extracted equations, a new model for thermal resistance estimation is proposed, which for the first time takes into account the aggregate impact of a number of fins, number of gate fingers, number, and dimensions of stacked nanowires. We have extracted the proposed model against calibrated 3-D TCAD simulations over a range of device design variables of interest. Our results show that the model may be useful for estimation of thermal resistance in FinFETs and NWFETs with large layouts. [ABSTRACT FROM AUTHOR]

The field-plate (FP) technique suppresses the electric field crowding at the p-n junction by inducing the interface charges in the drift region. However, due to the modeling difficulty, the physical meaning cannot be elaborated via the conventional 2-D methods, not to mention the designing optimization. Therefore, the FP assistant reduced surface field effective concentration profile (ECP) is proposed in this paper to explore the physical insight of the FP assistant 2-D coupling. The ECP simplifies the sophisticated 2-D coupling by equating the FP assistant effect to the variation of the ECP. As a result, a simple and effective 1-D analytical model is presented to qualitatively and quantitatively explore the FP-induced surface field reshaping and its distinctive breakdown mechanism. The analytical solutions are found out to be consistent with the simulation results obtained from MEDICI, a commercial TCAD tool. [ABSTRACT FROM AUTHOR]

In this paper, a new continuous multilevel compact model for phase-change memory (PCM) is proposed. It is based on the modified rate equations with the introduction of a variable related to material melting. The model is evaluated using a large set of dynamic measurements and shows a good accuracy with a single model card. All fitting parameters are discussed, and their impacts are detailed. Full circuit simulation is performed. Good convergence and fast simulation time suggest that this new compact model can be exploited for PCM circuit design. [ABSTRACT FROM AUTHOR]

The layout-induced cylindrical breakdown may occur as a result of the multifinger or circular layout-induced 3-D curvature effect resulting in the breakdown voltage reduction of the power device significantly. In this paper, by using effective doping concentration (EDC) concept, the inherent 3-D problem is simplified as a 1-D problem. Based on the EDC concept, a 1-D analytical model is presented to qualitatively and quantitatively explore the impact of curvature effect on the breakdown mechanism of SOI lateral double diffused MOS. The analytical solutions are found out to be consistent with the simulation results well obtained from MEDICI, a commercial technology computer-aided design tool. To the best of our knowledge, the proposed model is the first 1-D model which can accurately describe the 3-D curvature effect. [ABSTRACT FROM AUTHOR]

In this paper, subthreshold channel potential, current, swing, threshold voltage, and drain-induced barrier lowering models of short-channel tri-gate junctionless field-effect transistors are presented. The models incorporate the effects of both substrate-induced surface potential and variable edges of channel. The quasi-3-D approach is used for the modeling of minimum of channel potential that is subsequently used in the drift–diffusion equation to obtain the current expression in subthreshold regime. Threshold voltage and subthreshold swing models are also based on the minimum of channel potential. The analytical results are compared with the simulation data obtained using 3-D visual TCAD device simulator from Cogenda Pvt., Ltd. [ABSTRACT FROM AUTHOR]

In this paper, a multiple trench split-gate silicon-on-insulator (SOI) lateral double-diffused MOSFET with a Schottky rectifier (MTS-SG-LDMOS) is proposed and its characteristics are studied using 2-D simulations. The new structure features double oxide trenches, a floating polysilicon split-gate, and a Schottky rectifier. Each oxide trench includes a vertical field plate which enhances the depletion of the drift region and modulates the bulk electric field. As the simulation results, when compared to the conventional SOI LDMOS (C-LDMOS), the breakdown voltage in the MTS-SG-LDMOS increases from 297 to 350 V, the specific on-state resistance ( R \mathrm{\scriptscriptstyle ON,\mathsf {sp}} ) decreases from 142.9 to 48.2 \textm\Omega \cdot \mathsf cm^\mathsf 2 , and the gate–drain charge ( Q {\mathsf {gd}} ) decreases from 19 to 9 pC. Moreover, the reverse recovery time of the proposed structure shows a 73.6% reduction as compared to the C-LDMOS device. [ABSTRACT FROM AUTHOR]

This paper proposes an analytical threshold voltage model for the dielectric pocket double gate (DP-DG) junctionless FETs (JLFETs). The channel potential function has been obtained by solving 2-D Poisson’s equation using an evanescent mode analysis with suitable boundary conditions. The potential function has then been used for modeling the threshold voltage to investigate the effects of the DP thickness and length on the short-channel effects of the structure. The effects of source and drain depletion regions have been included for improving the accuracy of the model. The model results of DP-DG JLFETs have been compared with the simulation data obtained from the 2-D TCAD ATLAS device simulator. [ABSTRACT FROM AUTHOR]

The overall purpose of this paper is the prediction of the ultimate electrical high-frequency performance potential for SiGe C HBTs under the constraints of practical applications. This goal is achieved by utilizing advanced device simulation tools with parameters calibrated to experimental results of most advanced existing technologies. In addition, detailed electrostatic and electrothermal simulations are performed for determining the parasitic capacitances, temperature increase, and safe operating area of aggressively scaled devices. The important figures of merit are then determined from circuit simulation employing an accurate compact model incorporating all relevant physical effects. Based on the vertical profile found in Part I, this paper focuses on achieving a balanced device design by lateral scaling. It is shown that the peak values of (fT, f\max) around (1, 1.5) THz may be achievable. Such a performance limit provides still significant headroom for further developing existing processes and makes SiGe C HBTs well-suitable for highly integrated millimeter-wave applications operating within the low-end of the terahertz gap. [ABSTRACT FROM PUBLISHER]

Process variations increasingly challenge the manufacturability of advanced devices and the yield of integrated circuits. Technology computer-aided design (TCAD) has the potential to make key contributions to minimize this problem, by assessing the impact of certain variations on the device, circuit, and system. In this way, TCAD can provide the information necessary to decide on investments in the processing level or the adoption of a more variation tolerant process flow, device architecture, or design on circuit or chip level. In this first of two consecutive papers, sources of process variations and the state of the art of related simulation tools are reviewed. An approach for hierarchical simulation of process variations including their correlations is presented. The second paper, also published in this issue, presents examples of simulation results obtained with this methodology. [ABSTRACT FROM AUTHOR]

In this paper, an analytic model is proposed, which provides, in a continuous manner, the current–voltage ( $I$ – $V$ ) characteristic of high-performance tunneling FETs (TFETs) based on direct bandgap semiconductors. The model provides the closed-form expressions for $I$ – $V$ based on: 1) a modified version of the well-known Fowler–Nordheim (FN) formula (in the ON-state) and 2) an equation that describes the OFF-state performance while providing continuity at the ON/OFF threshold by means of a term introduced as the continuity factor. It is shown that the traditional approaches, such as FN, are accurate in TFETs only through correct evaluation of the total band bending distance and the tunneling effective mass. General expressions for these two key parameters are provided. Moreover, it is demonstrated that the tunneling effective mass captures both the ellipticity of evanescent states and the dual (electron/hole) behavior of the tunneling carriers, and it is further shown that such a concept is even applicable to semiconductors with nontrivial energy dispersion. Ultimately, it is found that the $I$ – $V$ characteristics obtained by using this model are in close agreement with the state-of-the-art quantum transport simulations both in the ON- and OFF-state, thus providing the validation of the analytic approach. [ABSTRACT FROM PUBLISHER]

A compact model for the single-poly multitime programmable (MTP) memory cells is presented in this paper for the first time. It is based on the charge balance approach, while the traditional old model is on the fixed capacitive coupling approach. The proposed cell model has been implemented by Verilog-A and integrated into commercial SPICE simulator. The model supports both dc and transient analyses, and the simulated results are consistent very well with those from device simulation and measurement, whereas the results by the traditional old model deviate substantially. Furthermore, the comprehensive optimization of the MTP cells is made feasible thanks to the new model, such as device size, high voltage ramp rate, and reliability prediction. As a result, this compact cell model will be very useful for the designers to evaluate and optimize a single-poly MTP cell. [ABSTRACT FROM AUTHOR]

In this paper, we present an accurate and computationally efficient model for circuit simulation of ultrathin-body silicon-on-insulator MOSFETs with strong back-gate control. This work advances previous works in terms of numerical accuracy, computational efficiency, and behavior of the higher order derivatives of the drain current. We propose a consistent analytical solution for the calculation of front- and back-gate surface potentials and inversion charge. The accuracy of our surface potential calculation is on the order of nanovolts. The drain current model includes velocity saturation, channel-length modulation, mobility degradation, quantum confinement effect, drain-induced barrier lowering, and self-heating effect. The model has correct behavior for derivatives of the drain current and shows an excellent agreement with experimental data for long- and short-channel devices with 8-nm-thin silicon body and 10-nm-thin BOX. [ABSTRACT FROM AUTHOR]

In this paper, we propose an accurate, detailed, and ready-to-use model to evaluate quickly parasitic capacitances on several CMOS architectures: planar bulk, planar FDSOI, planar double gate (DG), and FinFET (in DG or triple-gate configuration). This model takes into account raised source drain, trench contacts and discreet contacts, bilayer spacers, and inner-fringe capacitance screening. It has been validated with 2-D (FlexPDE software) and 3-D (Raphael software) simulations. [ABSTRACT FROM PUBLISHER]

To simulate semiconductor devices and circuits working at high frequencies or under a large signal input and to better understand their physical effects, a physically based simulation method is proposed in this paper. It utilizes a physical-model-based field simulation to analyze the semiconductor devices in a circuit and incorporates the field simulation into an equivalent-model-based circuit simulation to simulate the circuit. For the field simulation, a genetic-algorithm-based curve-fitting approach is proposed to extract the parameters of the semiconductor devices’ physical models. The proposed method is employed for the analysis of a few circuits containing a commercial p-i-n diode with model number mot_bal99lt1. The feasibility and accuracy of the proposed method are validated through a comparison of its simulation results with the measurement data, and good agreement is observed. The other merits of the proposed method are also illustrated, including its ability to provide useful physical mechanisms for the better understanding of the behavior of the p-i-n diode under various working conditions. [ABSTRACT FROM PUBLISHER]

This paper presents a nanotechnology-based high-power-density and low-power-loss on-chip power inductor for dc–dc switching power converters. This power inductor utilizes a composite of bundled multiwalled (concentric) carbon nanotubes (BMWCNTs) and Fe (iron) in order to achieve high performance in a small size. Titanium (Ti) is then added as a coating material on the BMWCNT-based power inductor. The BMWCNT-based power inductor with a single layer and three turns occupies an area of \200\ \mu\m \times \200\ \mu\m. It exhibits an inductance of 206 nH, a quality factor of 427 at 20 MHz, and a dc rated current of 100 mA. The power inductor size and the performance characteristics are competitive with state-of-the-art power inductors. The design, analysis, modeling, and simulation results of the BMWCNT-based power inductor are presented and compared with state-of-the-art conventional power inductors from the literature. [ABSTRACT FROM AUTHOR]

Bias temperature instability (BTI) is a serious reliability concern for MOS transistors. This paper covers theoretical analysis, Monte Carlo simulation, and experimental investigation of the charge trapping component of BTI. An analytical model for both stress and recovery phases of BTI is presented. Furthermore, the model properly describes device behavior under periodic switching, also called AC-BTI or cyclostationary operation. The model is based on microscopic device physics parameters, which are shown to cause statistical variation in transistor BTI behavior. It is shown that a universal logarithmic law describes the time dependence of charge trapping in both stress and recovery phases, and that the time dependence may be separated from the temperature and bias point dependence. Analytical equations for the statistical parameters are provided. The model is compared with experimental data and Monte Carlo simulation results. [ABSTRACT FROM AUTHOR]

Although the recently proposed single-implicit-equation-based input voltage equations (IVEs) for the independent double-gate (IDG) MOSFET promise faster computation time than the earlier proposed coupled-equations-based IVEs, it is not clear how those equations could be solved inside a circuit simulator as the conventional Newton–Raphson (NR)-based root finding method will not always converge due to the presence of discontinuity at the G-zero point (GZP) and nonremovable singularities in the trigonometric IVE. In this paper, we propose a unique algorithm to solve those IVEs, which combines the Ridders algorithm with the NR-based technique in order to provide assured convergence for any bias conditions. Studying the IDG MOSFET operation carefully, we apply an optimized initial guess to the NR component and a minimized solution space to the Ridders component in order to achieve rapid convergence, which is very important for circuit simulation. To reduce the computation budget further, we propose a new closed-form solution of the IVEs in the near vicinity of the GZP. The proposed algorithm is tested with different device parameters in the extended range of bias conditions and successfully implemented in a commercial circuit simulator through its Verilog-A interface. [ABSTRACT FROM PUBLISHER]

In this paper, we propose a fully experimental method to extract the barrier lowering in short-channel saturated MOSFETs using the Lundstrom backscattering transport model in one-subband approximation and carrier degeneracy. The knowledge of barrier lowering at the operative bias point in the inversion regime is of fundamental importance in device scaling. At the same time, we also obtain an estimate of the backscattering ratio and the saturation inversion charge. With respect to previously reported works on extraction of transport parameters based on the Lundstrom model, our extraction method is fully consistent with it, whereas other methods make a number of approximations in the calculation of the saturation inversion charge, which are inconsistent with the model. The proposed experimental extraction method has been validated and applied to results from device simulation and measurements on short-channel poly-Si/SiON gate nMOSFETs with gate lengths down to 70 nm. Moreover, we propose an extension of the backscattering model to the case of 2-D geometries (e.g., bulk MOSFETs). We found that, in this case, backscattering is governed by the carrier transport in a few nanometers close to the silicon/oxide interface and that the value of the backscattering ratio obtained with a 1-D approach can be significantly different from the real 2-D value. [ABSTRACT FROM AUTHOR]