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This paper introduces a novel, cost-effective solution designed to achieve large absorption bandwidth within the THz spectrum employing a miniaturized, single-layer metamaterial structure. The designed structure features a single circular ring composed of an ohmic resistive sheet with notably higher sheet resistance than traditional metallic resonators. This distinctive design is implemented on a lossy dielectric polyimide substrate with a backing of metallic gold. Our developed absorbing structure demonstrates the capability to achieve a substantial absorption bandwidth ranging from 3.78 to 4.25 THz, maintaining a consistent absorption rate of over 90%. Moreover, we conducted an analysis to assess its absorption performance under various sheet resistance values within the top layer. Additionally, we characterized its angular stability and polarization insensitivity through oblique incident and polarization angle analysis. Finally, an RLC circuital and interference theory approach is adopted to justify its simulated results. The proposed absorber shows potential for a broad spectrum of applications, encompassing communication, imaging, and diverse integrated circuits operating within the THz band. [ABSTRACT FROM AUTHOR]

The transformer is an important component of electrical engineering for many applications including those for integrated circuits. For integrated circuit applications, the use of a synthetic transformer has been recognised to be a viable option for a number of applications. This paper presents two new designs of electronically-controllable CMOS active transformers. The first preposition is based upon a capacitive T-network embedded between two active CMOS gyrators each of which has been obtained by a parallel back-to-back connection of one non-inverting and other inverting electronically-controllable CMOS transconductor. This circuit requires thirty-two MOSFETs, all operating in saturation region. The second design simulates an inductive T-network using two CMOS electronically-controllable floating inductors and one electronically-controllable CMOS grounded inductor thereby employing eighty MOSFETs. The first design offers the advantage of realising a step up as well as step down transformer by appropriate selections of the transconductances of two transconductors. The second design although uses a larger number of MOSFETs than the former but has the advantage of using three grounded capacitors which is a desirable from the view point of IC implementation. It may also be mentioned that using more MOSFETs does not increase layout area significantly since the capacitors require more layout area than all the MOSFETs put together. The workability of both the designs, along with their various performance characteristics and non-ideal analysis, has been well corroborated by computer simulations using SPICE software using 0.18 µm CMOS technology parameters. The application of the proposed circuits in the design of double tunned band pass filter has also been shown and its workability too has been validated by computer simulations using SPICE software. [ABSTRACT FROM AUTHOR]

The growing complexity of integrated circuits (ICs) brings expensive manufacturing test cost. Adaptive testing becomes an important way to save test cost by predicting die quality to reduce the actual test content. However, reducing test items often results in unacceptable levels of test quality degradation. An adaptive testing method is proposed in the paper to reduce test cost while guaranteeing test quality. Two quality predictors are trained with a subset of test items and spatial information for subsequent decisions. The dies are clustered according to the prediction results, and the clustering results are graded. The distribution of the different grade classes determines the die quality of each grade. Experimental results using fabricated wafers and the associated test data show that the proposed method reduces more than 42% of test items, and can achieve better test quality, reducing test escapes and yield losses by more than 90% in the Circuit Probing test (CP). [ABSTRACT FROM AUTHOR]

The paper presents the results of thermal modeling of a half-bridge monolithic integrated circuit (IC) with integrated drivers and enhanced mode power high electron mobility transistors, based on a GaN-on-SOI heterostructure. It had been established that the main heat sources in the IC were the half-bridge GaN HEMTs. The heat from the half-bridge GaN HEMTs propagates in the chip and leads to heating of the logic block and gate drivers. Heating of half-bridge GaN HEMTs leads to increased channel resistance and IC output current drop. Heating of the gate drivers reduces driving current, as a result, increases the switching time of the half-bridge GaN HEMTs. Heating of the logic block increases the rise and fall times of the generated control signals, which worsens the dynamic characteristics of the IC. A comparative analysis of heat propagation for IC dies based on GaN-on-SOI and GaN-on-Si heterostructures showed that GaN-on-SOI structure has a 40% greater junction-to-backside thermal resistivity compared to GaN-on-Si structure. In this case, the specific thermal resistance in the direction of heat propagation from the hotspot of the transistor to the backside of the die for the GaN-on-SOI structure is almost two orders of magnitude greater than in the direction of its propagation to the frontside of the chip. The results obtained were used for IC layout optimization. The rearrangement of GaN-on-SOI IC functional blocks, as well as to introduction of additional heat-spreading elements on the frontside of chip were carried out during the optimization. [ABSTRACT FROM AUTHOR]

This paper continues the research on the circuit synthesis problem for a multiplexer function of logic algebra, which is a component of many integrated circuits and is also used in theoretical study. The exact value of the depth of a multiplexer with select lines in the standard basis is found under the assumption that the conjunction and disjunction gates are of depth 1 and the negation gate is of depth 0; the depth equals if . Thus, it follows from previous results that the exact depth value equals for all positive integers such that either or . Moreover, for , this value equals 2, and for , it equals either or . Similar results are also obtained for a basis consisting of all elementary conjunctions and elementary disjunctions of two variables. [ABSTRACT FROM AUTHOR]

This paper reports the design and numerical results of three new extremely compact and efficient flat-top band-pass plasmonic filters operating in the near-infrared region. The proposed structures are realized in metal–insulator-metal plasmonic waveguides based on stub, tilted T-junction and right-angle trapezoid configurations. A built-in parameterized genetic algorithm is applied to maximize the transmission efficiency, while at the same time contributing to shrinking down the size of the device structures. It is shown that the tunability of the optical filters can be realized by modulating their structural parameters to gain control over the band-pass filtering wavelengths. Numerical calculations are conducted based on the finite element method of CST Microwave Studio and demonstrate that the suggested ultra-compact plasmonic waveguide filters offer wide bandwidths of more than 270 nm, 424 nm, and 289 nm, with transmission efficiencies of higher than 80%, 74.2%, and 74.3%, respectively. The sizes of the proposed wavelength filters are 490 nm × 575 nm, 350 nm × 180 nm, and 420 nm × 150 nm, respectively, which make them attractive candidates for applications in high density photonic integrated circuits (PICs). As a result, because of the promising characteristics of the proposed topologies such as their high efficiency, compact size, tunability, and simple structure they may find applications in on-chip integration, laser technology, and multi-photon fluorescence. [ABSTRACT FROM AUTHOR]

In this paper, ultra-compact, high isolation-ratio optical isolators for use in wavelength-division multiplexing networks are presented. The isolator is composed of two parts, including a straight waveguide and a resonator. The performance of the isolator is investigated for two kinds of disk and ring resonators. The structure is based on the metal–insulator–metal configuration in which the metal parts are of gold and the insulator parts are of a magneto-optical material. The effecting parameters, including the dimensions of the disk/ring resonator, the gap between the waveguide and the resonator, and the waveguide material are comprehensively studied using the finite-difference time-domain method. By changing the geometrical variables and materials, the isolation ratio of the disk-and ring-based isolators can reach up to 33.47 dB and 29.06 dB, respectively. The footprint of both isolators is less than 1 μm2. The proposed isolators can be used in photonic integrated circuits due to their ultra-compact footprint, high isolation ratio, and CMOS-compatible structures. [ABSTRACT FROM AUTHOR]

Silicon (Si) waveguide crossing serves as an enabling technology for dense Si photonic integrated circuits. Efficient crossing designs significantly boost the performance of photonic devices with many crossings. In this paper, several fundamental optical logic functions, such as XOR, AND, OR, NOT, NOR, NAND, and XNOR, are reported at 1550 nm telecom wavelength using direct Si waveguide crossing. The proposed scheme is made up of three input waveguides and one output waveguide arranged in the shape of the symbol ' + ' with a microring resonator in the middle. The operation of the specified logic functions depends on the constructive and destructive interferences generated by the phase differences between the incident optical beams. Using the contrast ratio and amplitude modulation metrics, the performance of the target logic operations is evaluated. Additionally, it is investigated and assessed how much the critical operating parameters affect the spectrum transmission. The proposed waveguide-based scheme can achieve better performance compared to other reported designs of similar nature, according to simulation outcomes derived using Lumerical FDTD. [ABSTRACT FROM AUTHOR]

Since 2007, methods that utilize side-channel data to detect hardware Trojan (HT) problems have been widely studied. Machine learning methods are widely used for hardware Trojan detection, but with the development of integrated circuits (ICs), better results are usually obtained using deep learning methods. In this paper, we propose an architecture inspired by Residual-Block and Dense-Block and combine it with SE Attention Mechanism, which we named the Res-Dense-SE-Net network. By combining residual connectivity, dense connectivity, and attention mechanism, the Res-Dense-SE-Net network can enjoy the advantages of these three network architectures at the same time, which can improve the expressiveness and performance of the model. The Res-Dense-SE-Net network can capture the key features in the image better, and it can solve the problems of gradient vanishing and feature transfer efficiently, which can in turn improve the classification accuracy and the generalization ability of the model. Based on the publicly available AES series of hardware Trojans from TrustHub and the publicly available hardware Trojan-side channel data by Faezi et al., we evaluate the effectiveness of the method proposed in this paper. The experimental results show that when a single Trojan exists, the method proposed in this paper has a high accuracy rate; and when multiple types of hardware Trojans exist at the same time and need to be categorized, the categories of hardware Trojans can also be effectively identified, and the categorization accuracy is high compared with the existing deep learning methods. [ABSTRACT FROM AUTHOR]

Semiconductor wafer manufacturing relies on the precise control of various performance metrics to ensure the quality and reliability of integrated circuits. In particular, GaN has properties that are advantageous for high voltage and high frequency power devices; however, defects in the substrate growth and manufacturing are preventing vertical devices from performing optimally. This paper explores the application of machine learning techniques utilizing data obtained from optical profilometry as input variables to predict the probability of a wafer meeting performance metrics, specifically the breakdown voltage (Vbk). By incorporating machine learning techniques, it is possible to reliably predict performance metrics that cause devices to fail at low voltage. For diodes that fail at a higher (but still below theoretical) breakdown voltage, alternative inspection methods or a combination of several experimental techniques may be necessary. [ABSTRACT FROM AUTHOR]

Multiwavelength nanophotonic devices are essential components in photonic integrated circuits for on-chip all-optical signal processing applications with enhanced data-storage capacity and increased bandwidth. Wavelength demultiplexing is a widely used photonic processing function, required for photonic signal processing on compact silicon chip designs. In this paper, we study optical rainbow trapping in a line defect photonic waveguide, and propose to use that effect for demultiplexing the light at visible spectrum. A defect waveguide is created in graded-index photonic crystal (GRIN PC) structure (the structure is composed of Si- PC cylinders having gradually varying radii along one dimension) as main channel, which allows the rainbow-trapping along the waveguiding channel. Vertical (side) channels are introduced to the system for efficient wavelength demultiplexing with low crosstalks and high coupling efficiencies thanks to the fact that incident light is localized at different positions along the main channel for certain operating visible wavelengths of The corresponding inter-channel cross-talks of is obtained at these incident wavelengths, which strengthens the idea of using such a GRIN PC structure for efficient wavelength demultiplexing applications. The studied multichannel demultiplexing device is relatively compact with a footprint of , which could be fabricated via simple lithography processes on a single Si- wafer. As far as authors' knowledge, this is the first time in literature that GRIN PC waveguide is implemented for multichannel wavelength demultiplexing function. The proposed GRIN PC design could be implemented for color sensitive photo-detection, absorption enhancement and optical spectroscopy. [ABSTRACT FROM AUTHOR]

Encryption chips are specialized integrated circuits that incorporate encryption algorithms for data encryption and decryption, ensuring data confidentiality and security. In China, the domestic SM4 algorithm is commonly utilized, as opposed to the international AES encryption algorithm. These widely implemented encryption standards have been proven to be difficult to crack through crypt analysis methods Currently, power consumption side-channel attacks are the most prevalent method. They involve capturing power consumption data during the encryption process and subsequently recovering the encryption key from this data. The two leading methods are Differential Power Analysis (DPA) and machine learning techniques. DPA does not necessitate prior knowledge but relies heavily on the number of power consumption curves. With only 50 power consumption data points, the accuracy is a mere 80%. Machine learning methods require prior knowledge, achieving an accuracy rate above 95% with only 30 power traces, albeit with training times typically exceeding 15 min. In this paper, a distributed energy analysis attack approach was presented based on Correlation Power Analysis (CPA). The power consumption data was divided into 16 subsets, with each subset corresponding to 8 bytes of the key. By training each subset separately, the 8-byte key's corresponding power consumption data is reduced to only 100 dimensions, resulting in a 76% decrease in cracking time and a 3% improvement in cracking accuracy rate.This article also trains a more complex 256 classification model to directly crack the final key, achieving a success rate of 28% in cracking 128-bit passwords with only 1 power trace [ABSTRACT FROM AUTHOR]

This paper proposes a symmetric plasmonic bandpass filter topology based on metal–insulator-metal waveguide configuration. The proposed filter is numerically simulated using the finite difference time domain method. Silver and air have been used as metal and dielectric materials in the proposed structure, respectively. The model used to characterize silver is Johnson and Christy. By the introduction of nanorods to the filter structure, the transmittance value can be improved. As a result, a maximum transmission peak of 93% is obtained. Other advantages of the proposed plasmonic filter include having a high Q-factor, a bell-shaped transmission spectrum, and being single-mode. Therefore, the proposed plasmonic bandpass filter can potentially be used in photonic integrated circuits. [ABSTRACT FROM AUTHOR]

The dielectric loss of Cu with high thermal conductivity is large at high frequency, which cannot meet the performance requirements in high-integrated circuits. There is an urgent need for materials to reduce its dielectric loss. In this paper, the thermal conductivity and dielectric properties of the AlN coating-Cu substrate system were controlled by changing the N2 pressure. The results showed that the crystallinity of hcp-AlN in AlN coating increased significantly when the proportion of N2 pressure was increased. With the increase of the N2 pressure, the particle size on the surface and the roughness of the coating improved. The AlN coating prepared at high N2 pressure had high dielectric constant and low dielectric loss at high frequency compared to those of the coatings prepared at low N2 pressure. At the same time, the AlN coating prepared under high N2 pressure on the Cu substrate did not decrease the thermal conductivity of Cu substrate. The AlN-Cu system prepared in this paper had high thermal conductivity and good dielectric properties, providing theoretical guidance for integrated circuit packaging and capacitor applications. [ABSTRACT FROM AUTHOR]

This paper proposes field programmable gate array (FPGA) realization of fuzzy PI controller for typical industrial process called stirred tank heater system. Due to the complex nature of fuzzy controller families, its implementation on digital signal processors (DSPs) result computational time delay which, in other words, makes the processing speed slower. To address the limitations of DSP implementation, an alternative digital hardware programmable device called FPGAs are being largely used for digital implementation of algorithms with higher computational speed and accuracy. The proposed work is inspired by this quality of FPGAs and aims to take advantage of reliable performance of fuzzy PI controllers with its complexity and having no considerable impact on processing speed. Here, fast and novel design approach for rapid prototyping of fuzzy PI controller for stirred tank heater is presented thoroughly. Xilinx system generator SIMULINK add on from VIVADO is used to generate very high-speed integrated circuit hardware description language (VHDL) directly from MATLAB. The developed controller for stirred tank system is verified in fixed point arithmetic using Xilinx Simulink blocks. The VHDL code is then generated, synthesized, implemented, and made ready for physical implementation on Kintex-7 evaluation board. [ABSTRACT FROM AUTHOR]

In the present study, five nano logical gates have been designed by means of eight rectangular Kerr nonlinear resonators in a unique plasmonic structure. All the logical gates were simulated with a single nano plasmonic composition, capitalizing on the two-dimensional Finite-Difference-Time-Domain method. The results showed that, on average, the transmission differences for the AND, NOR, OR, NAND, and XOR gates were 98%, 99%, 200%, 94%, and 96%, respectively, with a time response of 50 femtoseconds for all gates. In addition, it was found that the calculation of manufacturing tolerance can be considered as a practical method to consider the production error of logic gates. In the end, this paper provides positive outcomes for the future of computational integrated circuits in photonics. [ABSTRACT FROM AUTHOR]

Soft errors are the primary concern in space and terrestrial integrated circuit applications. When a charged particle from space collides with a scaled memory circuit, a transient pulse is generated across the sensitive storage node, causing a bit flip throughout the storage nodes. This bit flip is stated as a soft error, which affects the semiconductor memory architecture's stability and reliability. This paper presents a 10 T SRAM (STS-10 T) cell that mitigates soft error challenges even at space temperature. To demonstrate the relative performance of the STS-10 T, existing radiation-hardened memory cells, such as the Quatro-10 T, PS10T, NS-10 T, RHBD-10 T, 10 T-SRAM, RHMD-10 T, QUCCE-10 T, and SIS-10 T, were evaluated. The read stability of the proposed STS-10 T memory cell is 2.6x/ 3x/ 1.5x/ 1.4x/ 1.25x/ 1.6x/ 2.03 × greater than that of the existing Quatro-10 T/ NS-10 T/ PS-10 T/ RHBD-10 T/ RHMD-10 T/ QUCCE-10 T/ SIS-10 T memory cells, respectively. Moreover, 1.48x/ 1.17x/ 1.18x/ 1.4x/ 1.01x/ 1.27x/ 1.45x/ 1.43 × greater write ability than Quatro-10 T/ NS-10 T/ PS-10 T/ RHBD-10 T/ 10 T-SRAM/ RHMD-10 T/ QUCCE-10 T/ SIS10T. In addition, when the supply voltage is at 1 V, the read and write access time, hold power, and critical charge is also improved. [ABSTRACT FROM AUTHOR]

This paper proposes a new design for a π-phase shifter and two π/2-phase shifters, which are based on a two-dimensional rods-in-air photonic crystal waveguide. The proposed devices have been designed using both triangular and square lattice photonic crystal structures. Notably, these phase shifters do not require any external energy source to operate. To calculate the band diagram of the PhC, the plane wave expansion method was utilized, while finite-difference time-domain simulation methodology was used to estimate and examine the performance of the proposed phase shifters. The simulation results demonstrate that the proposed π-phase shifter can achieve a bandwidth of 1.5THz, whereas the π/2-phase shifters, designed on triangular and square lattice can achieve bandwidths of 1.9THz and 1.35THz, respectively. Due to their straightforward design structure and energy independence, these devices are well-suited for future generations of all-optical photonic integrated circuits. [ABSTRACT FROM AUTHOR]

The Cu–Fe–P alloy is the mainstream material of IC lead frame at present, which plays a key role in electrical signal transmission and mechanical fixation between bearing chip and external circuit board. With the development of integrated circuits toward high integration and extreme miniaturization, copper alloy strips for lead frames are required to have excellent electrical and mechanical properties, as well as excellent softening resistance under short-term high temperature service conditions. In this paper, the effects of annealing temperature (300, 400, 500 °C) on texture orientation and strength, and precipitates characteristics (morphology, size, interfacial relationship, etc.) of as-cold rolled Cu–2.18Fe–0.03P alloy were studied by means of EBSD and TEM. It is found that annealing at low temperature does not change the texture type, but it affects the texture strength compared with the as-cold rolled alloy. Cubic texture {001} < 100 > and R-type texture {111} < 112 > appear in the annealed alloy. The texture strength increases with the increase in annealing temperature, and the preferred orientation is more obvious. In addition, we found that there are two kinds of precipitated phases in the copper matrix, namely spherical α-Fe phase and irregular Fe3P phase. We further find out the coexistence state of the two precipitates and their evolution with annealing temperature. With the increase in annealing temperature from 300 to 500 °C, the size of the main strengthening phase α-Fe increases and the orientation relationship between α-Fe phase and the matrix changes from coherent to semi-coherent. On this basis, we found that the decrease in texture strength, the change of coherence relationship of α-Fe phase, and the decrease in dislocation barrier are the main factors leading to the softening of Cu–2.18Fe–0.03P alloy at high temperature. The research results of this paper are meaningful in guiding the development of high-end copper alloy strip in the field of electronic information. [ABSTRACT FROM AUTHOR]

With the advent of the 5G information age, the production and processing of computer chips have attracted people's attention. In order to adapt to the rapid development in the field of chip manufacturing, higher requirements are placed on chemical mechanical planarization (CMP). Due to the porous structure of the polishing pad surface, the polishing pad is prone to clogging and its performance gradually decreases during the polishing process. Therefore, the use of diamond disc conditioner to dress the polishing pad in the CMP process is an indispensable part. In this paper, a new method of measuring the conditioner disc is proposed, the wax is melted and covered on the disc, and after a period of time, it solidifies on the surface of the dressing disc to obtain the protrusion height of the grains; this method has more advantages than measuring with an optical microscope because of the error caused by the diffuse reflection of the microscope. For diamond conditioners used in the experiments, the motion trajectory of abrasive grains is simulated, which is the basis on choosing the experimental method, and the material removal rate model of the polishing pad is established. In addition, after polishing the silicon wafer with a polishing pad for 2 h, the diamond conditioners with orderly distributed abrasive grains are used to dress the pad, the discs can remove the blocking material on the surface of the polishing pad after dressing 30 min, and the dressing effect and efficiency of the diamond disc with grain size of 100 μm are more obvious. The surface roughness and the liquid contact angle of the polishing pad before and after dressing are measured; after a period of conditioning, they can be restored to a state similar to that of the new polishing pad. General scheme of the research [ABSTRACT FROM AUTHOR]

Research on artificial neural network computing based on conventional integrated circuit chips has made significant progress, but it faces technical bottlenecks such as reduced energy consumption, computing speed, and efficiency. So, it is seeking integrated chips based on optical interconnections to solve the current dilemma. Fortunately, the small size and very localized graphene surface plasmon waves offer the possibility of optical integrated chips. In this paper, we propose a graphene-based one-bit optical numerical comparator. The comparator is located on the top of a 0.4-μm2 rectangular dielectric layer, mainly consisting of Y-shaped graphene nanoribbons. The on/off effect of the graphene nanoribbons is achieved by applying an external voltage to change the chemical potential energy of the graphene switching bands. The proposed optical numerical comparator with 9.55-μm TM mode light achieves a minimum extinction ratio of 31.12 dB and amplitude modulation of 0.77 dB, as shown by the finite-difference time-domain (FDTD) method. Compared with the current optical numerical comparators, it has the advantages of a high extinction ratio, small size, low loss, and high stability. In addition, the effect of process deviation of graphene nanoribbons on the reliability of the designed optical numerical comparator is analyzed by simulation. It is beneficial to developing integrated photonic devices and has some significance for developing ultra-high-frequency and integrating artificial neural network computing. [ABSTRACT FROM AUTHOR]

The fabless nature of integrated circuits manufacturing leaves them vulnerable to modifications by ill-intentioned third party. There arises a necessity for security measures during their manufacturing to protect them from covert modifications known as hardware Trojans. Static analysis of gate-level synthesized integrated circuits can prove helpful in detecting the presence of unwanted circuitry within the host. This paper proposes a static analysis technique of gate-level integrated circuits using supervised probabilistic classifier through effective threshold analysis. New and existing relevant features are extracted that relates to hardware Trojan properties and normalised accordingly. Effective features are selected using their feature importance values. Variance threshold has been used to create a high entropy feature subset to train a supervised model using XGBoost algorithm with relevant hyperparameters. Threshold values of the probabilistic classifier are determined through analysis of threshold obtained using receiver operating characteristic and precision-recall curves. The chosen techniques showcase hardware Trojan detection with high accuracy over gate-level synthesized circuits. [ABSTRACT FROM AUTHOR]

This paper designs a novel E-plane waveguide magic-T in 220 GHz and develops a high-power solid-state power amplifier (SSPA) operating at 210–230 GHz in combination with eight InP high electron mobility transistor terahertz monolithic integrated circuits (TMICs). The 8-way divider-combiner network is composed of low-loss WR-4 novel E-plane waveguide magic-T. The matching load of waveguide magic-T is the air outside the waveguide module, which is connected to the pyramidal horn antenna of WR-4 waveguide to WR-10 waveguide. A monolithically integrated dipole-to-waveguide transition eliminates the need for wirebonding and additional substrates. The low-loss corporate power combining and low-loss dipole-to-waveguide transition achieve high-power combining efficiency of SSPA. The hydroxyl-iron is placed in the upper cavity of TMIC to prevent the cavity from resonance. The SSPA module demonstrated small-signal gain ≥ 10 dB from 210 to 229 GHz. The saturated output power was > 100 mW from 215 to 227 GHz and peak output power of 110 mW with 83% power combining efficiency at 220 GHz. [ABSTRACT FROM AUTHOR]

This paper presents the design and numerical investigation of tunable, ultra-compact, and highly-efficient plasmonic filters based on stepped impedance resonators (SIRs). The proposed devices are realized in metal–insulator-metal (MIM) plasmonic waveguide systems and exhibit more degrees of freedom and high flexibility to design resonator-based devices, thanks to the SIRs. The principle of conventional SIRs is discussed in terms of equivalent circuit model and characteristic impedance. Among the three proposed plasmonic filters, one of them acts as a short-wavelength, while the other two nanostructures work as long-wavelength cut-off filters at near-infrared region (NIR) and telecom wavelengths. Simulation results are carried out by a finite element method (FEM)-based solver and indicate that the cut-off wavelengths of the proposed resonators found to be at 1187 nm, 1265 nm, and 999 nm, respectively, can be easily tuned by modulating their structural parameters. In addition to the mentioned remarkable properties of the designed structures including the size which are found to be 500 nm × 310 nm, 350 nm × 285 nm, and 210 nm × 195 nm, respectively, the simple structures of the proposed topologies facilitate their fabrication process. Therefore, the suggested devices can contribute to the development of miniaturized, tunable, and efficient optical components for photonic integrated circuits (PICs) applications and in optical wireless communication systems. [ABSTRACT FROM AUTHOR]

In this paper, four individual structures based on graphene-plasmonic nano combinations are proposed for detection of corona viruses and especially COVID-19. The structures are arranged based on arrays in the shapes of half-sphere and one-dimensional photonic crystal formats. The half-sphere and plate shaped layers are made of Al, Au, SiO2 and graphene. The one-dimensional photonic crystals lead the wavelength and peak corresponding to the absorption peak to lower and higher amounts, respectively. In order to improve the functionality of the proposed structures, effects of structural parameters and chemical potentials are considered. A defect layer of GZO is positioned in the middle of one-dimensional photonic crystal layers to shift the absorption's peak wavelength to the appropriate wavelength range for diagnosing corona viruses (~300 nm to 600 nm). The last proposed structure is considered as a refractive bio-sensor for detection of corona viruses. In the final proposed structure (based on different layers of Al, Au, SiO2, GZO and graphene), corona viruses are considered as the biomolecule layer and the results are obtained. The proposed bio-sensor can be a good and functional candidate for detection of corona viruses and especially COVID-19 in photonic integrated circuits with the satisfying sensitivity of ~664.8 nm/RIU (refractive index unit). [ABSTRACT FROM AUTHOR]

Although analog-to-digital converters (ADCs) are critical components in mixed-signal integrated circuits (IC), their performance has not been improved significantly over the last decade. To achieve a radical improvement (compact, low power and reliable ADCs), spintronics can be considered as a proper candidate due to its compatibility with CMOS and wide applications in storage, neuromorphic computing, and so on. In this paper, a proof-of-concept of a 3-bit spin-CMOS Flash ADC using in-plane-anisotropy magnetic tunnel junctions (i-MTJs) with spin–orbit torque (SOT) switching mechanism is designed, fabricated and characterized. In this ADC, each MTJ plays the role of a comparator whose threshold is set by the engineering of the heavy metal (HM) width. Such an approach can reduce the ADC footprint. Monte-Carlo simulations based on the experimental measurements show the process variations/mismatch limits the accuracy of the proposed ADC to 2 bits. Moreover, the maximum differential nonlinearity (DNL) and integral nonlinearity (INL) are 0.739 LSB (least significant bit) and 0.7319 LSB, respectively. [ABSTRACT FROM AUTHOR]

Hardware Trojan (HT) is a severe security threat during the development of an integrated circuit that can deviate the IC from its normal function and/or leak sensitive information during in-field operations. Trojans are often inserted during the fabrication phase, and to have Trojan-free ICs; it is highly desirable to detect them during post-silicon testing. Different test pattern generation-based HT detection techniques are reported in the literature to detect the Trojan during post-silicon testing. The existing methods provide low coverage and require a large number of test patterns. This paper proposes a new test pattern generation-based HT detection technique that provides high coverage while requiring less number of patterns. The proposed technique generates the optimal number of test patterns that activate the rare events by framing the problem as multi-objective optimization and solving it through a non-dominated sorting genetic algorithm (NSGA-II). The Trojans are mostly inserted using rare-triggered nodes (highly vulnerable, low controllable, and low observable). Thus, our technique applies the generated patterns during post-silicon testing to activate Trojans. Further, we also present the use of checker (detection) logic along with a proposed approach to effectively detect the Trojan during testing. The experimental evaluation on ISCAS benchmarks shows that the proposed technique provides 12 times higher trigger coverage with 1/3 fewer test patterns than the best-known existing genetic algorithm-based technique. [ABSTRACT FROM AUTHOR]

This paper presents a novel flexible concurrent testing scheme for non-feedback and feedback bridging faults in integrated circuits. All the existing concurrent testing schemes for non-feedback and feedback bridging faults available in the literature are designed with very straightforward manner and these schemes do not provide any idea regarding flexibility in design of the tester circuit. However, providing flexibility in design of the tester circuit is one of the important criteria to be included in concurrent testing of modern integrated circuits. To the best of my knowledge, the proposed scheme will be treated as first concurrent testing scheme that provides flexibility in design of the tester circuit for both non-feedback and feedback bridging faults. This work aims to provide flexibility in tester circuit design by dropping some of wires that are tapped from Circuit Under Test (CUT) to the tester circuit. Dropping some of tap wires from CUT to the tester circuit reduces load on CUT and this helps in reducing the area overhead of the tester circuit. Thus, flexibility in concurrent testing is achieved by dropping some of tap wires during design of tester circuit. Further, dropping some of tap wires (flexibility) in tester circuit design provides a trades-off analysis between area overhead, fault coverage and fault detection latency. The proposed scheme is verified using different ISCAS89 benchmark circuits and results illustrate that flexibility in design of tester circuit is achieved through dropping some of tap wires from CUT to the tester circuit. Further, it reduces area overhead greatly with minimal compromise in fault coverage. [ABSTRACT FROM AUTHOR]

This paper presents design and numerical investigations of an ultra-compact, and highly-efficient plasmonic absorber based on metal–insulator–metal waveguides. The proposed device offers multiple narrow-band absorption at visible and near-infrared wavelengths with peak absorbance between 81 and 100%. The finite element method has been used to simulate the proposed structure. The simulation results show that the resonance wavelengths can be easily modulated by tuning the coupling distances between the input and output ports and the triangular resonators. To find the optimized size of the proposed structure, maximize its efficiency, and attain narrow-band resonances, a parameterized genetic algorithm has been used. Taking into account the obtained notable specifications of the proposed structure, it can contribute to the development of miniaturized and efficient optical components for photonic integrated circuits. [ABSTRACT FROM AUTHOR]

Reduction of the crosstalk (CT) between contiguous photonic components is still a big challenge in fabricating high packing density photonic integrated circuits (PICs). Few techniques to accomplish that goal have been offered in recent years but all in the near-IR region. In this paper, we report a design for realizing a highly efficient CT reduction in the MIR regime, for the first time to the best of our knowledge. The reported structure is based on the silicon-on-calcium-fluoride (SOCF) platform with uniform Ge/Si strip arrays. Using Ge strips shows better CT reduction and longer coupling length (Lc) than the conventional Si based devices over a wide bandwidth in the MIR region. The effect of adding a different number of Ge and Si strips with different dimensions between two adjacent Si waveguides on the Lc and hence on the CT is analyzed using both full vectorial finite element method and 3D finite difference time domain method. An increase in the Lc by 4 orders of magnitude and 6.5 times are obtained using Ge and Si strips, respectively, compared to strips-free Si waveguides. Consequently, crosstalk suppression of − 35 dB and − 10 dB for the Ge and Si strips, respectively, is shown. The proposed structure is beneficial for high packing density nanophotonic devices in the MIR regime, such as switches, modulators, splitters, and wavelength division (de)multiplexers, which are important for MIR communication integrated circuits, spectrometers, and sensors. [ABSTRACT FROM AUTHOR]

Knowledge of the positions, polarizations, and local environment effect on the light coupling efficiency from a single photon source to an optical waveguide is critically important for the development of an integrated single photon emitter. In this paper, we contribute to a holistic investigation on the dependence of the wideband coupling efficiency and Purcell enhancement factor on the emitter positions, orientations, refractive indices and geometrical parameters of SiNx waveguides for broadband CMOS-compatible quantum photonic integrated circuits using FDTD analysis in very near-infrared ranges. The obtainable spectral range with respect to SiNx waveguide dimensions and optical parameters, the polarization-dependent coupling efficiency of a single photon source with respect to the displacement from the waveguide edge facet, the horizontal and vertical positional variations, and the etching required to maximize and maintain the coupling efficiency values over the spectral range are discussed. [ABSTRACT FROM AUTHOR]

On-line performance monitoring of RF integrated circuits throughout their operating lifetime is a promising way to enhance their reliability. This paper explores the feasibility of adapting the indirect test strategy to implement on-line RF performance monitoring. After stating the principle of the proposed solution, we consider the fundamental requirements necessary to adapt the indirect test strategy. Finally, a proof of concept is established through a practical case of study by monitoring the power level delivered by the RF transmitter of a wireless microcontroller: hardware measurement results demonstrate the potential of this approach. [ABSTRACT FROM AUTHOR]

A study was made of a thermal interface based on a two-dimensional allotropic modification of carbon (graphene), presented in the form of a powder, for cooling integrated circuits. Such physical properties of the thermal interface as thermal conductivity, heat capacity, thermal diffusivity, and density are determined by the empirical method. The process of heat transfer in the most efficient thermal interface sample during the operation of integrated circuits in the ANSYS engineering analysis system is presented. The prospects of using pressed graphene powder as a thermal interface in order to eliminate the use of a binder are described. The paper also makes a comparison with the most effective type of thermal interfaces currently in use. [ABSTRACT FROM AUTHOR]

B Abstract: b Integrated circuits (ICs) with a single chip (die) are typically tested with a test flow consisting of two test instances: (1) wafer sort for the bare chip and (2) package test for the packaged IC. For ICs with stacked chips - 3D Stacked ICs - there are many possible test instances, even more test flows, and no commonly used test flow. We implemented the TFSA, three straightforward test flow schemes and an exhaustive search, and experimentally compared the test flow schemes on three different test architecture design approaches. [Extracted from the article]

When the integrated circuit (IC) feature size is reduced to 0.13 μm and below, copper (Cu) becomes the new wiring material in interconnect materials. The double damascene process is the only process for Cu patterning that is mature and has been successfully applied to IC manufacturing, so Cu interconnection chemical–mechanical polishing (CMP), which can achieve the surface nanoscale accuracy required by lithography level, is of great importance to the IC industry. The slurry is the most important component of the CMP materials and has a significant impact on the surface quality of the polished wafer. Therefore, how to select suitable additives to improve the chemical effect and obtain excellent post-polishing surface and good slurry stability while saving cost is an urgent issue to be considered. The research progress of each component in Cu interconnection slurry was discussed in this paper, mainly focusing on the advantages and disadvantages of acidic and alkaline slurries, and the research progress of oxidants, complexing agents, surfactants, and corrosion inhibitors as well as their respective action mechanisms were analyzed in detail, which will be a great contribution to the IC field. It will facilitate the optimization of the slurry for further development of new Cu interconnection CMP slurry. [ABSTRACT FROM AUTHOR]

In this paper, we simulated and designed an all-optical Fredkin gate. The proposed structure is very simple and compact. We used air holes with radii of 177 nm in a silicon slab waveguide in a square lattice with a lattice constant of a = 466 nm. First, we created input and output waveguides in the structure. After that, by imposing a non-linear ring resonator, we controlled the coupling of light. This ring is composed of doped glass with linear and non-linear refractive indices of 1.4 and 10–14 m2/w respectively. The results of the time analysis showed that the worst rising time of the proposed gate is 0.61 ps and hence is very fast. We set the parameters of the lattice in a way that the proposed device works on λ = 1550 nm. All of the mentioned features make this gate suitable for all-optical integrated circuits. [ABSTRACT FROM AUTHOR]

A novel design for a plasmonic sensor, consisting of a metal–insulator–metal waveguide with a coupled circle-semi-ring resonator is proposed and investigated in this paper. We carried out the theoretical analysis for the wave-guiding characteristics by utilizing the two-dimensional (2D) finite-difference time-domain method. The effects of the electromagnetic wave transmission, field profile distribution, temperature and refractive index (RI) sensing characteristics on the structural parameters were studied in detail. The simulation results indicate that proposed sensor possesses a RI sensitivity up to 990 nm/refractive index unit and a temperature sensitivity of − 0.42 nm/°C with optimized geometric parameters. The compact waveguide structure may be widely utilized in areas of sensing and integrated circuits. [ABSTRACT FROM AUTHOR]

On-chip ultrafast all-optical switching is highly desirable and important for all-optical information processing and photonic integrated circuits (PIC). Although numerous theoretical and experimental all-optical switching has been demonstrated, feasible switching scheme with compact size, ultrafast response, ultralow switching energy and ease to fabricate is still challenging. In this paper, we theoretically and numerically study the all-optical switching based on the Fano resonance in a silicon-polymer compound photonic crystal nanobeam side-coupled with a slotted nanobeam cavity. On one hand, owing to the cavity mode confined in the slotted region filled with polymer materials, the overwhelmingly large Kerr coefficient and ultrafast response can be fully utilized. Fano resonances with sharp asymmetric lineshape is in favor of improving switching operation on the other hand. Even under the excitation of 100 fs pump pulse, obvious all-optical switching can be achieved. Sub-picojoule switching energy, 462 fs switching time and switching contrast as high as 55.6% are realized simultaneously. Our proposed structure is compatible with the complementary-metal–oxide–semiconductor (CMOS) technology, which shows great potential in realizing high-performance and practical integratable all-optical switching. [ABSTRACT FROM AUTHOR]

In this paper, a programmable low-power analog front-end (AFE) integrated circuit (IC) for biomedical signal monitoring systems is presented. The whole system includes four parts, instrumentation amplifiers (IA), programmable gain amplifiers (PGA), programmable bandwidth filters (PBF) and successive approximation register analog-to-digital convertors (SAR ADC). The proposed IA employs a pseudo-differential structure to enhance the input impedance of the system. A novel hybrid bandwidth extension technology is introduced in the proposed PGA to correct the low-frequency distortion and improve the low-frequency bandwidth. In the design of PBF, the current steering technology is applied to achieve an area-efficient and energy-efficient architecture. Furthermore, a novel efficient switching scheme and a self-calibration dynamic element matching method are presented in the design of SAR ADC to reduce the power consumption and eliminate the effect of capacitor mismatch. In 0.18 μm CMOS technology, this AFE IC consumes 46.8 μW and occupies 0.36 mm2. It achieves a variable gain from 40.4 to 55.1 dB under different modes designed for different biomedical signals. The spurious-free dynamic range and signal-to-noise plus distortion ratio of the proposed SAR ADC are 71.3 and 53.3 dB, respectively, along with a figure of merit of 0.18 pJ/conv. [ABSTRACT FROM AUTHOR]

The Boolean satisfiability (SAT) methods are one of the efficient approaches used to solve the problems of Boolean matching and the equivalence checking of digital circuits. In combination with classic routing algorithms and optimization techniques, these methods demonstrate better results than the classic routing algorithms in terms of the speed of operation and the quality of the results. In this paper, the modern practice of using the SAT methods in computer-aided design systems for VLSI is analyzed. The examples of modern SAT approaches to the problems of routing and the formal equivalence checking of digital circuits' descriptions within the technological mapping as a part of the FPGA design flow are considered. The algorithm of the detailed routing of the FPGA switching blocks using the satisfiability problem is developed and presented. The results of its work are demonstrated on the example of the programmable logic block of the integrated circuit 5400TP094 made in Russia. The block has the island architecture, where the configurable logic blocks and switching blocks form a regularly repeated layout template. The properties of the chosen classic architecture allow us to expand the region of the presented algorithm to the entire class of island style of FPGA. The algorithm is tested on the project benchmarks ISCAS-85, ISCAS-89, and LGSynth-89. The comparison of the developed SAT-based algorithm with the well-known routing algorithm Pathfinder is presented by the criteria of the elapsed time and the achieved degree of routed nets in the switching blocks. It is specified that the considered Boolean satisfiability methods for the routing problem are capable to prove the circuit's unroutability, unlike the Pathfinder algorithm whose results can only implicitly indicate it. The paper demonstrates that the application of a more efficient SAT solver significantly accelerates the work of the suggested detailed routing algorithm. [ABSTRACT FROM AUTHOR]

This paper proposes a visual management scheme of medical things with a color-change radio frequency identification (RFID) tag. The color-change RFID tag employs a specific RFID tag integrated circuit (IC) and a laminated pH-indicating paper. The IC has energy harvesting and switched ground functions, which enable it to generate electricity to the laminated pH-indicating paper. This phenomenon causes electrolysis of NaCl solution absorbed in the laminated pH-indicating paper. Electrolysis generates alkaline matter to change the color of the pH-indicating paper. This paper gives a new and sensitive structure of the laminated pH-indicating paper. The proposed advanced color-change RFID tag with new laminated pH-indicating paper succeeds in changing its color noticeably at a 1 m distance using an RFID reader radiating 1 W radio waves. The color change was observed 3–5 s after starting radio wave irradiation. The results of this experiment also confirm that the changed color can be held for over 24 h. Furthermore, two demonstrations of the visual management system of medical things (patient clothes and sanitizers) are presented. [ABSTRACT FROM AUTHOR]

The paper presents a mathematical apparatus based on the set-theoretic approach, which allows the prompt configuration of software routing within the design flow of user circuits in the basis of heterogeneous field-programmable gate array (FPGA) or reconfigurable system on a chip (SoC). The variety and interchangeability of technological and design solutions, the variety of forms and methods of routing resources programming for the implementation of user project nets entail the need to ensure quick adjustment of computer-aided design (CAD) tools for possible changes in the architecture of the basic (FPGA' or SoC's) chip. Taking into account this requirement, by means of the above mentioned mathematical apparatus, the paper provides a generalized description of the routing resources of a heterogeneous FPGA or a reconfigurable SoC, and formalizes the task of routing the nets of user designed circuits. One can also use the given formal descriptions during the analysis of the architectural solutions space within the design flow of problem-oriented heterogeneous FPGAs and reconfigurable SoCs. [ABSTRACT FROM AUTHOR]

Pollution that comes from vehicles is the most significant cause in the ecosystem and is increasing every day. This leads to several environmental challenges, including global warming in which Plants and animals are affected significantly. The hybrid E-motorcycle (HE-M) is a technology that helps sort out these kinds of issues. Two or three power sources for complete rechargeable combustion are used in the hybrid electric motor. This paper used two independent electric power units: the drive unit and the integrated circuit (IC) motor unit. One power unit can be used up to 50–90 km from the electric drive and its eco-friendliness motor. It can be converted to an IC motor that makes the motorcycle more flexible, high-speed and long-distance operations. The initial motorcycle is fitted with continuous variable transmission. HE-M has been introduced to overcome the drawbacks and achieve high automatic mode performance. This paper consists of three HE-M modes, two energy management techniques applied, the HE-M servo motor control system and liquid crystal display monitor are addressed. Furthermore, road testing results explicitly demonstrate that the motor's pollutant emissions can be minimized at lower speeds or in operation causes and significantly enhanced by inadequate cruising space for electric motors. [ABSTRACT FROM AUTHOR]

This paper contains the results of calculation of the rate and number (probability) of random single event effects (upsets and failures) in radio electronic equipment (REE) caused by space ionizing radiation during an interplanetary flight of a spacecraft. Based on the analysis of the results, the criteria for the selection of upset-resistant and failure-resistant integrated circuits in the onboard electronic equipment were determined. [ABSTRACT FROM AUTHOR]

Hardware Trojan (HT) intrusion at different integrated circuit (IC) phases is the most important concern for the semiconductor industries. Recently, machine learning (ML) models have been used to detect HT from the pre-silicon IC phase, which utilizes either structural or SCOAP gate level netlist features. However, the main concern is that an adversary may poison the training dataset by flipping the target labels to malign the ML model training, which further provides an incorrect prediction on the test dataset. Thus, due to the malicious training of ML models, the Trojan-inserted ICs are missed out and can easily perform their malicious activities. Hence, it is of utmost importance to scan the training dataset and identify the poisoned input samples before applying ML models for HT detection. Therefore, this paper proposes a new technique that first identifies the poisoned training samples, which consist of SCOAP features, and then detects HTs from the unseen gate-level netlist. The proposed technique employs a robust ensemble Categorical Boosting (CatBoost) model, which avoids the problem of target leakage by using the concept of ordered boosting. Further, a label flipping poisoning attack based on a stochastic hill-climbing search is proposed, which flips the labels of the handful of samples that maximizes the validation dataset loss by deteriorating the model performance. Moreover, a defense method is proposed which utilizes CatBoost object importance and k-nearest neighbor to detect malicious training samples and restore their original labels. Finally, the CatBoost model is trained on the clean dataset to detect the HT nets from the unseen gate-level netlist accurately. Experimental results shows that the proposed attack method increases the on-an-average loss up to 58 % and 54 % on Trust-Hub and DeTrust benchmarks. Whereas the proposed defense method accurately identifies the poisoned input labels from the training dataset with on-an-average 99 % accuracy on these benchmarks. [ABSTRACT FROM AUTHOR]

This paper contains the results of calculation of the rate and number (probability) of random single event effects (upsets and failures) in radio electronic equipment (REE) caused by space ionizing radiation during an interplanetary flight of a spacecraft. Based on the analysis of the results, the criteria for the selection of upset-resistant and failure-resistant integrated circuits in the onboard electronic equipment were determined. [ABSTRACT FROM AUTHOR]

In the modern era, advances in CMOS technology have increased the number of transistors and the complexity of computations that can be performed on each chip. Due to the many limitations of this technology, to reduce the size of the chips to the nanotechnology level and to continue Moore's law, the unique properties of quantum cellular automata have made it a candidate for future integrated circuits. Operational units such as logic and arithmetic units are the main components of processors, among which the operation of addition and subtraction is the most widely used arithmetic operator, and the design of redundant ternary adder without publishing the carry affects the performance of processors. The main aim of this paper is to design a redundant full adder and full subtractor by employing a carry and borrow bit generator module based on ternary QCA (TQCA) innovation. Based on this, the block diagram structure of the ternary redundant adder/subtractor-based TQCA circuit is presented, which includes a proposed new carry/borrow generator gate based on TQCA. The proposed full adder design has 423 ternary cells, area 0.09 µm2 and cost 647.19, and the full subtractor has 431 ternary cells, area 0.09 µm2 and cost 710.7. For validation, the circuits were simulated with the TQCAsim software. The results of this innovation show that the proposed architecture has significant advantages. [ABSTRACT FROM AUTHOR]

His paper presents a new tunable positive and negative active inductor simulator and positive and negative capacitance and resistance multiplier. The proposed designs use only one second-generation voltage-mode conveyor (VCII+), one OTA and two passive elements. Applications to the proposed designs in the design of different types of filters are also presented. The functionality of the designs is confirmed using simulation and experimentally. [ABSTRACT FROM AUTHOR]

Designing reliable Networks on Chip (NoCs) is critical, especially with the continuous scaling down of integrated circuit technology, which exposes NoCs to various types of faults. In this paper, a reliability-aware application mapping technique for improving the reliability of heterogeneous NoCs is proposed. It is based on a hybridization of the Multi-Objective Particle Swarp Optimization (MOPSO) algorithm and Reinforcement Learning (RL). At design time, MOPSO and RL perform the optimization of an initial mapping and the prediction of fault-tolerant remapping scenarios, respectively. To teach and to produce an intelligent agent capable of generating an optimal adaptive remapping scheme to address run-time permanent processing element (PE) failures. Two models of RL agents are trained, each based on a different mechanism of task migration: 1) step-based agent and 2) swap-based agent. Experiments were carried out to assess the performance of our innovative technique on various sizes of NoCs, using real benchmarks and varying the levels of heterogeneity and failure in the NoC. The results of the experiments reveal that using RL to solve the reliability problem in NoCs yields interesting results in terms of reliability, energy consumption, execution time, and cost migration. [ABSTRACT FROM AUTHOR]

Dielectric singularities (DSs) constitute one of the most exotic features occurring in the effective permittivity of artificial multilayers called hyperbolic metamaterials (HMMs). Associated to DSs, a rich phenomenology arises that justifies the ever-increasing interest profuse by the photonic community in achieving an active control of their properties. As an example, the possibility to "canalize" light down to the nanoscale as well as the capability of HMMs to interact with quantum emitters, placed in their proximity, enhancing their emission rate (Purcell effect), are worth mentioning. HMMs, however, suffer of an intrinsic lack of tunability of its DSs. Several architectures have been proposed to overcome this limit and, among them, the use of graphene outstands. Graphene-based HMMs recently shown outstanding canalization capabilities achieving λ/1660 light collimation. Despite the exceptional performances promised by these structures, stacking graphene/oxide multilayers is still an experimental challenge, especially envisioning electrical gating of all the graphene layers. In this paper, we propose a valid alternative in which indium-tin-oxide (ITO) is used as an electrically tunable metal. Here we have numerically designed and analyzed an ITO/SiO2 based HMM with a tunable canalization wavelength within the range between 1.57 and 2.74 μm. The structure feature light confinement of λ/8.8 (resolution of about 178 nm), self-focusing of the light down to 0.26 μm and Purcell factor of approximately 700. The proposed HMM nanoarchitecture could be potentially used in many applications, such as ultra-fast signal processing, high harmonic generation, lab-on-a-chip nanodevices, bulk plasmonic waveguides in integrated photonic circuits and laser diode collimators. [ABSTRACT FROM AUTHOR]