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In this article, we investigate extensively the bipolar-switching properties of Al2O3- and HfO2- based resistive-switching memory cells operated at low current down to <1 μA. We show that the switching characteristics differ considerably from those typically reported for larger current range (>15 μA), which we relate as intrinsic to soft-breakdown (SBD) regime. We evidence a larger impact of the used switching-oxide in this current range, due to lower density of oxygen-vacancy (Vo) defects in the SBD regime. In this respect, deep resetting and large memory window may be achieved using the stoichiometric Al2O3 material due to efficient Vo annihilation, although no complete erasure of the conductive-filament (CF) is obtained. We finally emphasize that the conduction may be described by a quantum point-contact (QPC) model down to very low current level where only a few Vo defects compose the QPC constriction. The large switching variability inherent to this latter aspect is mitigated by CF shape tuning through adequate engineering of an Al2O3\HfO2 bilayer. [ABSTRACT FROM AUTHOR]

Analog in-memory compute (AiMC) is a promising approach to efficiently process deep neural networks (DNNs). Due to its small size and nonvolatility, oxide resistive random access memory (OxRRAM) is being considered as a memory device to map neural network weights in AiMC systems. However, OxRRAM conductance variability can have a severe impact on neural network accuracy. This variability depends on the conductance range, in which the OxRRAM device is programed. In this work, the conductance variability is characterized by a range of operating regimes. Next, the DNN accuracy is determined by applying the measured conductance distributions as noise on the neural network weights during training and inference. The software equivalent accuracy is achieved for only high current compliance values on small data sets. This has implications on the AiMC system, in which this device is intended to be used. [ABSTRACT FROM AUTHOR]

Ferroelectric Si-doped HfO2 is a promising candidate for future generation memory devices. However, such devices are vulnerable to significant threshold voltage shifts resulting from charge trapping in oxide defects. We use complementary characterization and modeling techniques to reveal significant electron trapping/de-trapping behavior, together with a strong temperature dependence of the electron emission kinetics in ferroelectric layers, which results from the onset of polarization of the ferroelectric layer. This can lead to an apparent difference in the defect characteristics in ferroelectric-HfO2 compared to the paraelectric-HfO2 structures they are shown to closely resemble when this contribution is decoupled. The results demonstrate the presence of a defect band closely aligned to the silicon conduction band, which can easily be accessed during device operation. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the unipolar resistive-switching mechanism in TiN\NiO\Ni cells, whereby the NiO layer is deposited by metal-organic chemical vapor deposition. Irrespective of the cell size down to 80 nm, controlled unipolar switching is observed only on condition the Ni electrode is used as anode. Local elemental analyzes revealed enhanced oxygen concentration at the NiO\Ni interface after reset operation. Based on this result as well as on the quantum-mechanical modeling of the conduction for different resistance states, the reset switching is analyzed in terms of electrochemically assisted oxidation process of the conductive filament close to the Ni anode. Electrical switching results on various stack configurations confirm the major impact of the electrode materials on the reset performances, bringing important insights into the mechanisms involved in the unipolar switching of this system. Literature data are discussed on the basis of this learning, suggesting possible extension of these considerations to other oxide-based switching systems. [ABSTRACT FROM AUTHOR]

Results from an extensive reliability characterization of HfLaSiO(N) devices, with TaN gate electrodes, are reported. It is shown that the effect of the lanthanum, initially deposited as La2O3, on a SiO2/HfSiO(N) stack, permeates the Si/SiO2 interface. A lower midgap interface state density is observed at this interface, but increased densities are seen towards the band edges. The presence of lanthanum in the dielectric results in defects in the interface layer and in the high-κ dielectric. A profile of defects in the gate stack is suggested, inferred from a combination of electrical measurements. From the location of the defects, it is argued that the reliability of lanthanum-incorporated devices is not compromised by its presence, thus enabling a reliable route to Vt tuning of n-type metal oxide semiconductor devices. [ABSTRACT FROM AUTHOR]

This work presents a detailed analysis of the ability of high-κ materials to recover from Fowler-Nordheim stress-induced degradation. Forming gas and high temperature rapid thermal anneal steps are compared to determine their efficiency at trap recovery. The annealing responses of the technologically relevant HfSiON and HfO2 materials (equivalent oxide thickness <2 nm) are correlated with structural differences in these dielectrics, trap generation rate, charge centroids, and defect de-passivation. It is shown that stress-induced damage can be fully recovered for HfO2 by high temperature annealing. [ABSTRACT FROM AUTHOR]

Interface state generation is a major reliability issue for metal-oxide-semiconductor based devices. The generation can take place not only during stresses, but also after terminating the stress. Our attention is focused on analyzing the dynamic behavior of the generation after substrate hot hole injection. Despite previous efforts in this area, the generation kinetics is not fully understood, and there is insufficient information on the process limiting the generation rate. We start by showing that the normalized generation kinetics is insensitive to either the defect density or the processing condition. We then investigate the effect of various stressing parameters on the kinetics, including the oxide field strength during and posthole injection, the stress time, the energy and current of hot holes. This is followed by examining why the available models are inapplicable in our cases, including hydrogen transportation, trapped hole conversion, and coupling models. Finally, we propose both hydrogen emission and detrapping of a certain type of hole traps as the rate limiting processes, and the relative importance of these two is addressed. [ABSTRACT FROM AUTHOR]

This article investigates the H-anneal induced positive charge generation in the gate oxide of metal-oxide-semiconductor field-effect transistors fabricated by a submicron complementary metal-oxide-semiconductor process. A significant number (~10cm) of fixed and mobile positive charges are generated at 450degreesC. Properties (reactivity, electrical and thermal stability) of these positive charges are compared with the positive charges observed in the buried oxide of silicon-on-insulator devices. The differences in these two are investigated, in terms of their transportation time across the oxide, uniformity and sources of hydrogen. Attention is paid to the role played by boron in the generation and the possible connection between the positive species observed here and the defects responsible for the positive bias temperature instability. Efforts are made to explain the difference in reactivity between the H-anneal induced positive species and the hydrogenous species released by irradiation or electrical stresses. c 2001 American Institute of Physics. [DOI: 10.1063/1.1384860]. [ABSTRACT FROM AUTHOR]

After terminating electrical stresses, the generation of interface states can continue. Our previous work in this area indicates that the interface state generation following hole injection originates from a defect. These defects are inactive in a fresh device, but can be excited by hole injection and then converted into interface states under a positive gate bias after hole injection. There is little information available on these defects. This article investigates how they are formed and attempts to explain why they are sensitive to processing conditions. Roles played by hydrogen and trapped holes will be clarified. A detailed comparison between the interface state generation after hole injection in air and that in forming gas is carried out. Our results show that there are two independent processes for the generation: one is caused by H[sub 2] cracking and the other is not. The rate limiting process for the interface state generation after hole injection is discussed and the relation between the defects responsible for this generation and hole traps is explored. © 2001 American Institute of Physics. [ABSTRACT FROM AUTHOR]

Presents information on a study which investigated the electrical characteristics of metal-oxide semiconductor capacitors with thin gate dielectric stacks. Methodology; Results; Conclusions.

To obtain reliable magnetic tunnel junctions (MTJs) for sensor and memory applications, the quality of the Al[SUB2]O[SUB3] tunnel barrier is extremely important. Here, we studied the reliability of MTJs with a 1.6 nm Al[SUB2]O[SUB3] tunnel barrier formed by ultraviolet light assisted oxidation. In the stress measurements, prebreakdown current jumps and, finally, breakdown are observed. We show, by using statistics, that both the current jumps and the final breakdown can be attributed to single trap generation. Moreover, we can relate the current jump height to the trap location. In this way, we reveal the breakdown mechanism in MTJs and illustrate the importance of reliability studies. [ABSTRACT FROM AUTHOR]

The development of magnetic random access memory requires very reliable magnetic tunnel junctions (MTJs). However these devices are prone to dielectric breakdown. To investigate the reliability of the MTJs, we performed constant voltage stress tests. This study shows the area scaling and the voltage dependence of the time-to-breakdown t[sub BD] of exchange biased, naturally oxidized MTJs. The fraction of broken devices F is plotted on a Weibull scale. The Weibull fit of our data shows clearly that t[sub BD] scales with the area, meaning that the breakdown sites are randomly distributed. Moreover, the Weibull distributions have a constant slope β (=0.35) and show no tails. This suggests that only one breakdown mode is observed. It is not clear yet whether an intrinsic or extrinsic failure mechanism is causing the breakdown, but considering the small Weibull slope, extrinsic breakdown caused by randomly distributed process-induced defects in the oxide is most plausible. Second, the voltage dependence of t[sub BD] is studied. To fit the data, a linear dependence of 1og(t[sub BD]) on stress voltage is assumed. It is however not yet proven whether this model is applicable for ultrathin Al[sub 2]O[sub 3] barriers. [ABSTRACT FROM AUTHOR]

Ferromagnetic tunnel junctions are very sensitive to degradation and breakdown, due to the ultrathin (∼1 nm) tunnel barrier. When the junction is stressed with a constant current or voltage, a conductance change of the tunnel junction is observed. Sufficiently high stress will lead to breakdown of the junction. As in SiO[sub 2] gate oxide reliability studies, the Weibull distribution plot can be obtained from the time to breakdown data. The dependence of the Weibull function on the area and the stress conditions is studied for the Al[sub 2]O[sub 3] barrier of the tunnel junctions. This is the first step of a systematic study of reliability, which is an important issue for the use of tunnel junctions in, e.g., magnetic random access memory applications. © 2001 American Institute of Physics. [ABSTRACT FROM AUTHOR]

Since the early days of the investigation on resistive switching (RS), the independence of the ON-state resistance with actual cell area has been a trademark of filamentaryswitching. However, with the continuous downscaling of the memory cell down to 10 x 10 nm² and below, the persistence of this phenomena raises intriguing questions on the conductive filaments (CFs) and its dimensions. Particularly, the cell functionality demonstrated at relatively high switching current (> 100 µA) implies a high current density (> 106 A/cm²) inside a CF supposedly confined in few hundreds on nm3. We previously demonstrated a methodology for the direct observation of CFs in integrated devices namely scalpel SPM, which overcomes most of the characterization challenges imposed by the device structure and the small CF lateral dimensions. In this letter, we use scalpel SPM to clarify the scaling potential of HfO2-based valence change memory (VCM) by characterization of CFs programmed at relatively high switching current and by AFM tip-induced RS experiments. Besides the demonstration of a remarkable scaling potential for the VCM technology, our results are also used to clarify the present understanding on the AFM-based experiments. [ABSTRACT FROM AUTHOR]

The nanoscale resistive switching in hafnium oxide stack is investigated by the conductive atomic force microscopy (C-AFM). The initial oxide stack is insulating and electrical stress from the C-AFM tip induces nanometric conductive filaments. Multimode resistive switching can be observed in consecutive operation cycles at one spot. The different modes are interpreted in the framework of a low defect quantum point contact theory. The model implies that the optimization of the conductive filament active region is crucial for the future application of nanoscale resistive switching devices. [ABSTRACT FROM AUTHOR]

In this letter, a tip-induced cell relying on the conductive atomic force microscope is proposed. It is verified as a referable replica of an integrated resistive random access memory (RRAM) device. On the basis of this cell, the functionality of sub-10 nm resistive switching is confirmed in hafnium oxide stack. Moreover, the low current switching behavior in the sub-10 nm dimension is found to be more pronounced than that of a 50×50 nm2 device. It shows better ON/OFF ratio and low leakage current. The enhanced memory performance is ascribed to a change in the shape of the conductive filament as the device dimensions are reduced to sub-10 nm. Therefore, device downscaling provides a promising approach for the resistance optimization that benefits the RRAM array design. [ABSTRACT FROM AUTHOR]