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Self-heating in fully depleted silicon-on-insulator (FDSOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) is experimentally studied using the gate resistance thermometry technique, in a wide temperature range from 300 down to 4.2 K. We demonstrate that below 160 K, the channel temperature increase ($\Delta {T}$) due to self-heating starts to deviate significantly from the linear variation with the dissipated power, leading to an apparent power dependent thermal resistance. This power dependence is interpreted in terms of temperature dependent thermal conductivity. The thermal resistance dependence on the active device temperature (${T}_{\text {Device}}$) indicates that the former one is mainly driven by the thermal conductivity of the oxide layer. Moreover, based on this dependence we reconstructed the channel temperature increase for each dissipated power and ambient temperature, and we found that the calculated values were in a good agreement with the experimental ones. Results indicate that even at low temperatures, thermal resistance does not depend significantly on the silicon channel thickness (ranging from 7 up to 24 nm), whereas the buried-oxide thinning (145 and 25 nm) strongly reduces the magnitude of the thermal resistance. Finally, this paper intends to fill the gap of experimental data concerning self-heating in advanced FDSOI transistors at low temperatures, revealing limitations and perspectives that should be taken into account for future work. [ABSTRACT FROM AUTHOR]

Low-frequency noise (LFN) of high-k/metal stack nMOS and pMOS transistors is experimentally studied. Results obtained on 32-nm complementary metal–oxide–semiconductor (CMOS) technologies, including LFN spectra and normalized power spectral density data analysis, are presented. These results indicate that the carrier number fluctuation is the main noise source for both nMOS and pMOS devices. As noise performance may strongly vary between different devices on one chip, the variability of the LFN when scaling down devices was also evaluated. A model known in the literature was used and enhanced in order to understand the noise level variability. A statistical analysis of the noise variability is also presented showing the dependence of the standard deviation with the device area. The comparison with former results from 45-nm poly/SiON technology demonstrates a better control of noise variability in the 32-nm CMOS technology. [ABSTRACT FROM PUBLISHER]

Thanks to their structure, the SOI technologies present several intrinsic advantages for analog and RF applications. Indeed, as it is well established now, these technologies allow the reduction of the power consumption at a given operating frequency. Moreover, the high-insulating properties of SOI substrates, in particular when high resistivity substrate is used, make that these technologies are perfect candidates for mixed-signal applications. In the present paper, we will discuss the performances of the SOI technologies in radio-frequency range. First of all, the high-frequency behavior of SOI substrates, thanks to the characterization of transmission lines, will be shown. The impact of the SOI substrate resistivity on the performances of passive components will also be analyzed. Then, an overview of RF performances of SOI MOSFETs for two different architectures, fully- and partially-depleted, will be achieved and compared to the bulk ones. Finally, the influence of some specific parasitic effects, such as the kink effect, the self-heating effect and the kink-related excess noise, on the RF performances of SOI devices will be studied, thanks to a specific high-frequency characterization. [ABSTRACT FROM AUTHOR]

In this letter, we demonstrate the existence of the source–drain series resistance mismatch and its impact on drain current variability with regard to the other mismatch parameters. To this end, we propose a new methodology for the drain current mismatch study based on $Y$ -function, enabling a precise determination of the various variability sources in advanced fully depleted silicon on insulator (SOI) MOS devices. [ABSTRACT FROM AUTHOR]

The impact on the extracted low‐frequency noise (LFN) parameter values due to LFN variability in CMOS devices is investigated. First, it is demonstrated that the noise level dispersion follows a log normal statistical distribution. Then, based on this feature, it is explained why the mean values from the linear data are different from the mean values (or median values) calculated from the log noise data. Finally, the consequence of this finding in terms of LFN characterisation issues and Monte Carlo LFN variability circuit simulation is discussed. [ABSTRACT FROM AUTHOR]

The impact on the extracted low-frequency noise (LFN) parameter values due to LFN variability in CMOS devices is investigated. First, it is demonstrated that the noise level dispersion follows a log normal statistical distribution. Then, based on this feature, it is explained why the mean values from the linear data are different from the mean values (or median values) calculated from the log noise data. Finally, the consequence of this finding in terms of LFN characterisation issues and Monte Carlo LFN variability circuit simulation is discussed. [ABSTRACT FROM AUTHOR]

The impact of dynamic variability due to low-frequency fluctuations on the operation of CMOS inverters, which constitute the basic component of SRAM cell, is investigated. The experimental methodology to characterise the effect of dynamic variability in a CMOS inverter is first established based on fast I-V measurements of the load current following the application of a ramp input voltage Vin(t). It is shown that, for small ramp rise times, the load current characteristics IDD(Vin) exhibit a huge sweep-to-sweep dispersion due to low-frequency noise. The impact of such dynamic variability sources on the inverter's output characteristics Vout(Vin) is finally demonstrated, revealing a 20% noise margin reduction for the smallest inverter cell. [ABSTRACT FROM AUTHOR]

Investigates the low frequency noise behavior in fully depleted SOI/metal oxide semiconductor transistors in both ohmic and saturation regimes. Data on static measurements in the ohmic and saturation regimes; Noise in the saturation regime for SOI transistors.