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In addition to the haze, the captured images may also contain some amount of noise. The image dehazing approaches may be invalid when the input hazy image contains significant noises. To mitigate the effects of both haze and noise, a joint framework for image dehazing and denoising is vital. An effective framework for joint dehazing and denoising for single-image in real-time is proposed here. The VLSI design for the proposed framework is also presented. In the low-frequency (LF) subband, a hardware-friendly dehazing algorithm that makes use of the saturation-based transmission map (TM) estimation technique is used. In the high-frequency (HF) subbands, wavelet denoising combined with hard thresholding rule is used to improve the denoising capabilities. This research displays a competitive performance in the image quality of the dehazed visuals and computational effectiveness in the presence of Gaussian noise when compared to previous sophisticated dehazing algorithms. The hardware complexity of the suggested framework is reduced by using discrete wavelet transform (DWT) structures based on fractional wavelet filter (FrWF) and canonical-signed-digit (CSD) method. To the best of our knowledge, this is the first attempt to design and implement VLSI architecture for simultaneous dehazing and denoising in the wavelet domain. The proposed architecture is defined using Verilog hardware description language (HDL) and synthesized using the Cadence genus compiler. When employing the CSD technique, the proposed framework reduces area and power by 5.09% and 1.75%, respectively. The maximum operating frequency of the proposed architecture is 96.25 MHz. [ABSTRACT FROM AUTHOR]

In the event of an epileptic attack, the Field-Programmable Gate Array (FPGA)-accelerated Convolutional Neural Network (CNN) model is paired with Electroencephalogram (EEG) acquisition equipment to produce a reliable production system that can be used in clinical medical diagnosis. Additionally, this study includes cybersecurity to protect both the epileptic patient’s data and the prediction system. Epilepsy is a frequent neurological disorder that manifests as recurrent seizures, a sign that indicates rapid intervention is necessary to minimize adverse events and improve patient health. The study provides a new real-time design for predicting epileptic seizures based on the Application-Specific Integrated Circuit (ASIC)-based Very Large-Scale Integration (VLSI) architecture. As a first step, EEG data from epilepsy patients were captured and pre-processed. Afterwards, faults and artefacts in the data were removed. Additionally, data was divided into short-time windows and then classified as either ictal, pre-seizure, or interictal. The CNN model was adapted for EEG signal analysis and then trained with categorized data. This technique is more effective and efficient for predicting epileptic seizures accurately, which is advantageous for patient monitoring and treatment. Additionally, cybersecurity measures were implemented to secure patient data and the prediction system. [ABSTRACT FROM AUTHOR]

Polar codes are the popular error-correcting codes and increased their attention after being adopted for the control channel in fifth-generation new radio (5G NR) standards. An efficient hardware architecture for polar code is often required with minimal encoding and decoding complexity. This work proposes a Multi-folded pipelined architecture and analyzes the performance in terms of latency, hardware utilization, and throughput. The designed architecture has two folded architectures interconnected in parallel to output 4-bits simultaneously. Folding transformations are used to reduce the number of idle processing elements (PEs) in every stage leading to the effective utilization of PE. Precomputation is effectively utilized in the PE to reduce the critical path delay, which improves the maximum operating frequency. A Loop-based shifting register (LSR) is employed to reduce the number of registers used. The analytical model for latency and utilization rate has been derived from the scheduling of the proposed architecture. The proposed design shows 63–71% higher hardware utilization than conventional semi-parallel design for code length N = 512 suitable for the physical downlink control channel (PDCCH) in 5G NR. The architecture is also implemented in Virtex-6, ZYNQ-Ultrascale+ MPSoC device for maximum supported code length of 5G NR, i.e., up to 2 10 , compared with the existing decoders. The proposed design also has the benefit of lesser look-up-table (LUT) consumption and zero random-access-memory (RAM) usage with some additional registers, making it suitable for resource-constraint applications. [ABSTRACT FROM AUTHOR]

An efficient 2-D Finite Impulse Response (FIR) filter is designed using modified McClellan transformations with optimized coefficients. The P3 transformation is considered to attain sharp circular symmetry filters to reduce the complexity of the architecture of the 2-D FIR filter. The filter coefficients are represented in Canonical Signed Digit (CSD) space to construct the filter architecture by multiplierless design. The CSD representation is optimized using the Cuckoo Search Algorithm (CSA) with fitness function Mean Square Error (MSE). Further, a Fully Direct (FD) type architecture of a 2-D FIR filter is implemented according to the obtained CSD-based coefficients for the length of N × N = 11 × 11 . Each row filter structure is realized and explored. All the hardware structures of row filters were realized and integrated using Verilog HDL and synthesized by Genus tools provided by the CADENCE Vendor in a 45 nm CMOS generic library. The area, delay, and power reports are generated by this synthesis tool and compared with the existing 2-D FIR filter architectures. The area, power, and delay values of the proposed filter architecture are decreased by 28.9%, 49.59%, and 36.02%, respectively to the conventional filter architecture. The Power-Delay-Product (PDP) and Area-Delay-Product (ADP) values of the proposed filter architecture are reduced by a minimum of 2.14 and 1.96 times, and a maximum of 4.31 and 66 times to the existing filter architectures respectively. [ABSTRACT FROM AUTHOR]

The complex harmonic wavelet (CHW) for the discrete signal is orthogonal, compact support in the frequency domain but is not complex conjugate symmetric for positive and negative half-planes. The modified complex harmonic wavelet (MCHW) transform is the improved version of CHW as it is the complex conjugate symmetry along with other desired properties of CHW such as orthogonality, and compact support in the frequency domain. Due to the complex conjugate symmetry, MCHW has lesser computational complexity compared to CHW. This paper introduces a new VLSI architecture for MCHW for hardware implementation and prototyped on a commercially available virtex5 field-programmable gate array (FPGA). For the validation of the proposed implementation, the real-time captured results in the logic analyzer are verified with simulation results. The maximum operating frequency targeting the above-mentioned FPGA device is reported as 92.82 MHz. The total on-chip power of the above implementation is 1.117W, out of which 84 mW is the dynamic power dissipation at a toggle rate of 12.5 %. Finally, for the area utilization of the above implementation, its resource utilization targeting the above FPGA device is reported. [ABSTRACT FROM AUTHOR]

Communication channels with memory are often sensitive to burst noise, which drastically reduces the decoding performance of standard channel code decoders, and this degradation worsens as channel memory increases. Hence, interleavers and de-interleavers are usually used to reduce the effects of burst noise at the expense of increased latency in the communication system. The delay imposed by interleavers/de-interleavers and the performance deterioration induced by channel memory are unacceptable in novel applications that require ultra-low latency and high decoding performance. Guessing Random Additive Noise Decoding (GRAND) is a universal Maximum Likelihood (ML) decoding technique for short-length and high-rate channel codes. GRAND Markov Order (GRAND-MO) is a hard-input variant of GRAND that has been specifically developed for communication channels with memory that are subject to burst noise. GRAND-MO can be used directly on hard demodulated channel signals, removing the requirement for extra interleavers/de-interleavers and considerably reducing overall latency in communication systems. This paper describes a high-throughput GRAND-MO VLSI architecture that can achieve an average throughput of up to 52 Gbps and 64 Gbps for code lengths of 128 and 79, respectively. Furthermore, we propose improvements to the GRAND-MO algorithm to simplify hardware implementation and reduce decoding complexity. When compared to GRANDAB, a hard-input variant of GRAND, the proposed improved GRAND-MO algorithm yields a decoding performance gain of 2 ∼ 3 dB at a target FER of 10 - 5 . Similarly, as compared to the (79, 64) BCH code decoder, the proposed GRAND-MO decoder has a 33% reduced worst-case latency and a 2 dB gain in decoding performance at a target FER of 10 - 5 . [ABSTRACT FROM AUTHOR]

Ultrareliable low-latency communication (URLLC), a major 5G new-radio (NR) use case, is the key enabler for applications with strict reliability and latency requirements. These applications necessitate the use of short-length and high-rate channel codes. Guessing random additive noise decoding (GRAND) is a recently proposed maximum likelihood (ML) decoding technique for these short-length and high-rate codes. Rather than decoding the received vector, GRAND tries to infer the noise that corrupted the transmitted codeword during transmission through the communication channel. As a result, GRAND can decode any code, structured or unstructured. GRAND has hard-input as well as soft-input variants. Among these variants, ordered reliability bits GRAND (ORBGRAND) is a soft-input variant that outperforms hard-input GRAND and is suitable for parallel hardware implementation. This work reports the first hardware architecture for ORBGRAND, which achieves an average throughput of up to 42.5 Gb/s for a code length of 128 at a target frame error rate (FER) of 10−7. Furthermore, the proposed hardware can be used to decode any code as long as the length and rate constraints are met. In comparison to the GRAND with ABandonment (GRANDAB), a hard-input variant of GRAND, the proposed architecture enhances decoding performance by at least 2 dB. When compared to the state-of-the-art fast dynamic successive cancellation flip decoder (Fast-DSCF) using a 5G polar code (PC) (128, 105), the proposed ORBGRAND VLSI implementation has $49\times $ higher average throughput, $32\times $ times more energy efficiency, and $5\times $ more area efficiency while maintaining similar decoding performance. [ABSTRACT FROM AUTHOR]

Purpose: The paper aims to develop a systematic approach to design, integrate, and implement a set of crypto cores in a system-on-chip SoC) environment for data security applications. The advanced encryption standard (AES) and PRESENT block ciphers are deployed together, leading to a common crypto chip for performing encryption and decryption operations. Design/methodology/approach: An integrated very large-scale integration (VLSI) architecture and its implementation for the AES and PRESENT ciphers is proposed. As per the choice, the architecture performs encryption or decryption operations for the selected cipher. Experimental results of the field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) implementations and related design analysis are provided. Findings: FPGA implementation of the architecture on Xilinx xc5vfx70t-1-ff1136 device consumes 19% slices, whereas the ASIC design is implemented in 180 nm complementary metal-oxide semiconductor ASIC technology that takes 1.0746 mm2 of standard cell area and consumes 14.26 mW of power at 50 MHz clock frequency. A secure audio application using the designed architecture on an open source SoC environment is also provided. A test methodology for validation of the designed chip using an FPGA-based platform and tools is discussed. Originality/value: The proposed architecture is compared with a set of existing hardware architectures for analyzing various design metrics such as latency, area, maximum operating frequency, power, and throughput. [ABSTRACT FROM AUTHOR]

This paper presents a generalized novel design of a family of multiplier free orthogonal wavelet filter banks (FBs) with low complexity. In the proposed method, maximum number of zeros at $z=-1$ is ensured for a desired length of analysis and synthesis filters. A new class of technique is proposed to obtain dyadic filter coefficients based on double shifting orthogonality property with allowable deviation from original filter coefficients. This is achieved by slightly altering perfect reconstruction (PR) condition to obtain dyadic filter coefficient. A general closed form expression is formulated using double shifting orthogonality property to reduce the error between original filter coefficients and proposed dyadic filter coefficients. The designed wavelet FB improved time-frequency product, Sobolev regularity and frequency selectivity (low energy in error) over well known existing wavelet FBs. In addition, a fixed point VLSI architecture is proposed for the designed family of orthogonal wavelet FBs. The suggested architecture is designed and implemented on Kintex7 FPGA board. The proposed family of orthogonal wavelet FBs is multiplier less with significantly reduced adders, shifters and dynamic power dissipation. The performance of the proposed wavelet FB is validated on two different applications namely image compression and medical image retrieval. The proposed FBs are tested on well known datasets such as CLASSIC, EPFL, RAISE, and FiveK for image compression and on three different medical image databases such as NEMA, OASIS, and EXACT09 for image retrieval. [ABSTRACT FROM AUTHOR]

In this paper, we propose a low-complexity and high-speed VLSI architecture design methodology for complex square root computation using COordinate Rotation DIgital Computer (CORDIC). The proposed methodology is independent of angle computation in the CORDIC unlike the state-of-the-art methodologies. The proposed methodology is modelled in VHDL and synthesized under the TSMC 45-nm CMOS technology @ 1 GHz frequency. The synthesis results show that the proposed design saves 18.39%, 4.06% and 17.26%, 2.56% on chip area and power consumption when compared with the state-of-the-art methodologies without loss in accuracy. The proposed design saves the latency of 16 and 14 clock cycles when compared with the state-of-the-art implementations. The proposed design can process 23.4 and 127.344 billion additional samples per one joule energy when compared with the state-of-the-art designs. [ABSTRACT FROM AUTHOR]

The irrational coefficients of orthogonal wavelet filters require a large amount of hardware for their implementation. This results in huge memory requirement, increased power dissipation and reduction in speed of operation. This paper presents a new class of multiplier free db3 orthogonal wavelet filter bank with significantly reduced power dissipation, adders and shifters. In this paper, dyadic filter coefficients of db3 have been obtained by slightly altering double-shifting orthogonality property for perfect reconstruction. The proposed db3 wavelet filter improved time–frequency product, Sobolev regularity and frequency selectivity. Also, the VLSI architecture is suggested for the proposed db3 wavelet filter banks to analyse the hardware computational complexity. The performance of the proposed db3 wavelets achieved satisfactory performance for feature extraction in medical image retrieval and fingerprint recognition of infants and toddlers. [ABSTRACT FROM AUTHOR]

Performing the image compression over the resource constrained hardware is quite a challenging task. Although, there has been various approaches being carried out towards image compression considering the hardware aspect of it, but still there are problems associated with the memory acceleration associated with the entire operation that downgrade the performance of the hardware device. Therefore, the proposed approach presents a cost effective image compression mechanism which offers lossless compression using a unique combination of the non-linear filtering, segmentation, contour detection, followed by the optimization. The compression mechanism adapts analytical approach for significant image compression. The execution of the compression mechanism yields faster response time, reduced mean square error, improved signal quality and significant compression ratio performance. [ABSTRACT FROM AUTHOR]

The discrete wavelet transform is commonly used as a denoising step for many applications, like biomedical applications which are usually suffering from low SNR of the recorded signal. However, the choice of appropriate threshold value for DWT coefficients plays significant role in reconstructing the denoised signal. This paper presents a design of real -time wavelet denoising architecture which is suitable for wide range of real-time denoising applications. In this design, an adaptive thresholding approach based on feedback control loop is proposed to make the architecture more applicable for real-time wavelet denoising. This thresholding method considers a noise level estimator module based on first detail coefficients level 𝑑1 to calculate the unknown standard deviation of background noise. The proposed architecture is developed using MATLAB to simulate the suggested denoising method. The performance of the proposed denoising method is studied in terms of integral gain 𝐺 of feedback control and window size 𝑀 with respect to the improvement in SNR and settling time. The results imply that the proposed denoising architecture is suitable for real-time denoising applications with acceptable improvement in SNR approximately 8 dB. [ABSTRACT FROM AUTHOR]

This brief presents a novel VLSI architecture for computing discrete wavelet packet transform (DWPT) for the continuous flow of data. Each stage of the proposed multi-stage architecture consists of the bit-reordering circuit and serial wavelet filter. The conventional wavelet filter has been modified for single path serial data. The intermediate coefficients are reordered with the help of a bit reordering circuit in order to maintain a continuous flow of data from input to output end with minimum memory and minimum latency. In comparison to the recently published architectures, the proposed one not only reduces the memory requirement by more than 50% but also achieves a 100% hardware utilization ratio. Furthermore, the area and power requirements are reduced by more than 60% and 50%, respectively. [ABSTRACT FROM AUTHOR]

A novel sparsity adaptive compressed sensing (CS) scheme based on Reed-Solomon (RS) codes is proposed to reduce the amount of sampled data, which can adjust the sampling rate adaptively to achieve data sampling and reconstruct the original data accurately by any decoding algorithm on the finite field. Moreover, the proposed sparsity adaptive reconstruction architecture can greatly improve the data reconstruction efficiency of the proposed CS scheme. The simulation results show that the sparsity adaptive scheme can reduce 83.6% of the sampled data. The results illustrate that the proposed architecture needs about 95k gates and operates at 500 MHz to achieve the throughout of 4.0 Gb/s, which can greatly improve the efficiency of the communication system. Meanwhile, it is at least 21.4% more area-efficient compared with previously reported fixed sampling rate architecture based on RS codes. [ABSTRACT FROM AUTHOR]

This paper presents a digital signal processing (DSP) architecture for real-time and distortion-free recovery of electrically-evoked compound action potentials (ECAPs) from stimulus artifacts and periodic noises in bidirectional neural response telemetry (NRT) system. In this DSP architecture, a low computation-cost bidirectional-filtered coherent averaging (BFCA) method is proposed for programmable linear-phase filtering of ECAPs, which can be easily combined with the alternating-polarity (AP) stimulation method to reject stimulus artifacts overlapped with ECAP responses. Design techniques including the configurable folded infinite-impulse response (IIR) filter and division-free averaging are also presented for efficient hardware implementation. Implemented in 180-nm CMOS process, the proposed DSP architecture consumes 10.03-mm2 area and 2.35-mW post-layout simulated power. The efficacy of the DSP architecture in recovering ECAPs from recorded neural data contaminated by overlapped stimulus artifacts and periodic noises is validated in in-vivo electrical nerve stimulations. Experiment results show that compared with the previous coherent averaging technique, the proposed DSP architecture improves the signal-to-noise ratio (SNR) of ECAP responses by 11 dB and achieves a 3.1% waveform distortion that is 17.1× lower. [ABSTRACT FROM AUTHOR]

Pseudo Random Bit Generator (PRBG) is a need factor for getting data through transmission in different cryptographic applications. In the normal existing Pseudo random bit generation systems like Linear Feedback Shift Register (LFSR), Linear Congruential Generator (LCG), Coupled LCG (CLCG), and Dual Coupled LCG (Dual-CLCG), the last ends up being more secure. This technique relies upon correlations that causes pseudorandom bit generation at a non-uniform stretch. The drawbacks listed for this technique are excessive memory usage, high-initial clock latency, failing to grasp the foremost length sequence. In this paper we have proposed a Modified Dual-CLCG technique at a uniform clock rate to produce pseudorandom number. The tale commitment of the arranged PRBG method is to have pseudorandom bit with low power. The present proposed architecture offers significant improvement in terms of power and speed in comparison to other reported architectures. Architecture for LCG is compared with different devices so that Artix 7 shows least power having a value of 0.042W. The execution of PRBG strategy is simulated utilizing VHDL and is reconfigurable utilizing Artix 7 FPGA board. [ABSTRACT FROM AUTHOR]

'Fast Fourier transform' (FFT), being a prevalent algorithm for the proficient computation of 'discrete Fourier transform,' constitutes one of the major sub-modules in numerous real-time signal processing systems. In this article, a new approach of CORDIC-based high-radix FFT architecture has been demonstrated. Having identified the complex rotation as the most time-consuming elementary operation of FFT, the number of such complex rotations has been optimized by adopting radix-8-based FFT computation. To add to this, CORDIC is employed to realize the complex rotation, keeping aside its multiplier–accumulator (MAC)-based counterpart, for further economizing the VLSI implementation of the proposed FFT architecture. Furthermore, the requirement of CORDIC blocks for last three stages of radix-8 FFT computation has totally been mitigated by utilizing SCALE blocks as the rotation in those stages can be expressed in terms of π / 4 or its multiples. RAM is arranged in the form of memory banks to provide parallel data path operations, and RAM switching is performed in between stages for sustaining continuous data flow circumventing data access hazards. The throughput of the proposed radix-8 architecture is eight outputs per clock cycle, while the maximum clock frequency is limited only by the propagation delay of an adder. Hardware utilization and comparative performance evaluation have been reported to prove the proposed architecture's supremacy. Our proposed prototype radix-8 architecture has been successfully implemented on Zynq UltraScale+ FPGA using Xilinx Vivado 18.2 software for verifying its feasibility in practical applications. [ABSTRACT FROM AUTHOR]

Transform model estimation (TME) is a geometric operation, widely utilized in real-time imaging systems. Considering the massive computational load of matrix algebra-based TME realizations, most of the imaging systems resort to highly paralleled software-platform-based TME execution, which is power-intensive and expensive. Due to low-speed and power intensiveness, existing hardware for TME is not capable enough to meet the requirements of real-time systems. In this article, a hardware-realizable method of three-degree-of-freedom TME is formulated encompassing both the conventional CORDIC and the proposed modified CORDIC. The novelties of the proposed TME method and the corresponding architecture are that its latency sublinearly varies with the precision and the total computation time (CT) is almost independent of the input image sizes. The performance of prototype 16-bit fixed-point TME architecture (realized using VHDL in Xilinx Vivado 18.2) is compared with the software-counterpart. The proposed TME hardware is utilized along with other standard hardware modules to realize image registration (IR) operation. The proposed IR architecture achieves, on average, 60% reduction in total CT, $1.61 \times $ increase in maximum operating frequency with a comparable accuracy, only at the cost of 23% increase in power consumption with respect to other existing IR hardware. [ABSTRACT FROM AUTHOR]

This article proposes an encoding method based on a two-step encoding algorithm for the 12 quasi-cyclic (QC)-low-density parity-check (LDPC) (QC-LDPC) codes specified in the IEEE 802.11n/ac/ax standards. The proposed approach jointly considers all codes of the particular set, instead of targeting each code separately. The proposed algorithm performs multiplication by inverse matrices. The complexity of the multiplications is significantly reduced by the introduced encoding method. It allows the implementation of full-parallel architectures that execute the encoding process within a single clock cycle, or more for pipelined implementations, for any of the supported codes. A corresponding VLSI encoding architecture based on XOR-gate trees is also proposed. The proposed solution exploits the structure and features of the involved matrices to extract common subexpressions (CSs) using common sub-expression sharing techniques (CSST). Such expressions result due to common features of the original matrices and the corresponding inverses, identified in this article. Innovative subexpression extraction procedures that target the specific codes as a set are introduced here. Furthermore, illustrative single-clock hardware encoders derived by the proposed technique are integrated into 90- and 45-nm technologies at 1 GHz occupying 125 and 107 KGates, respectively, achieving throughput rates up to 1.62 Tbps. [ABSTRACT FROM AUTHOR]

Dedicated hardware realisation of 'Discrete Wavelet Transform' (DWT) is highly demanded for real-time multimedia operations in any handheld gadgets, as DWT is a popular transform-domain mathematical tool widely employed for many applications. Several DWT techniques exist in the literature assisting the software-based DWT realizations, inappropriate for real-time operations. There exist several hardware-based solutions for DWT. But most of the VLSI architectures of DWT fail to offer balanced performance, i.e. such architectures show good performance with respect to certain metrics while sacrificing other performance metrics. In this article, a convolutional DWT-based pipelined and tunable VLSI architecture of Daubechies 9/7 and 5/3 DWT filter is presented. The proposed architecture is designed with an ardent focus of maintaining balanced performance. The presented design, which blends the merits of convolutional and lifting DWT while dumping their demerits, is prepared area and memory efficient by employing 'Distributed Arithmetic' (DA) in our own ingenious method. Comparative experimental results justify the superiority of the proposed design regarding 30% area reduction, memory saving, remarkable clock frequency attainment and acceptable computation time. The proposed 2D DWT architecture is applied for real-time image decomposition. The outcomes of such real-time on-board testing prove the practicability of the presented work. [ABSTRACT FROM AUTHOR]

In this brief, a novel approximation method and its optimized hardware implementation are proposed for the sigmoid function used in Deep Neural Networks (DNNs). Based on piecewise approximation and truncated Taylor series expansion, the proposed method achieves very good approximation with low complexity while exploiting data representation with powers of two. In addition, by analyzing gradients of the sigmoid function, a small trick is introduced to improve the approximation precision. Furthermore, to reduce the hardware complexity and shorten the critical path, sampled values of the function are generated with simple logical-mapping. It is shown that the proposed approximation schemes can be implemented with purely combinational logic and the sigmoid function can be computed in one clock cycle. The experimental results demonstrate that the mean absolute errors are at the order of $1\times 10^{-3}$. Compared with prior arts, the new design can obtain significant improvement in critical path with comparable performance. [ABSTRACT FROM AUTHOR]

In this brief, we propose a low complexity VLSI architecture design Methodology for Wigner Ville Distribution (WVD) computation. The proposed methodology performs both auto and cross WVD computations using only the half number of Fast Fourier transform (FFT) computations as opposed to the state of the art methodologies. The FPGA implementation for proposed methodology was performed for 16 bit fixed point and 32 bit single precision floating point numbers on the Xilinx Virtex-7 FPGA (XC7vx485tffg). The proposed methodology saves 49% energy consumption when compared with the state of the art methodology. However it can be noted that the proposed methodology is independent of the VLSI implementation platform and technology node. [ABSTRACT FROM AUTHOR]

In this work we present least squares (LS) approach to design linear phase Finite Impulse Response (FIR) filter. Since the design of FIR digital filters is non-analytic, we aim at ideal zero-phase magnitude response and minimize the weighted error in passband and stopbands. The problem of least squares can then be solved non-iteratively by solving system of linear equations. Solution of which yields impulse response that is both real and symmetric. Frequency response of the proposed LS FIR filter shows a flat passband, and higher stop-band attenuation than traditional window based FIR design and comparable attenuation with Parks–McClellan method of the same order. In addition we have implemented LS FIR filter on FPGA based VLSI architectures. Performance evaluation of proposed LS FIR design on VLSI architecture shows comparable throughput, area and power consumption compared to classical filter design approaches. [ABSTRACT FROM AUTHOR]

To enable the continued scaling of distributed storage, failure recovery schemes that have low latency and low redundancy are indispensable. Minimum storage regenerating (MSR) codes have been developed to achieve this goal. Compared to other MSR codes, the recent coupled-layered (Clay) codes have many advantages such as low sub-packetization level, small finite field for construction, and uniform repair bandwidth over data and parities. This brief proposes efficient VLSI architectures for Clay encoder and decoder. Through exploiting subfield elements of finite fields, the logic complexity is substantially lowered. Additionally, the buffer size is reduced by optimizing the coupling scheme. For an example Clay code with (n,k)=(6,4), the proposed designs achieve 12% and 24% logic complexity reduction on the encoder and decoder, respectively, under the same timing constraint. [ABSTRACT FROM AUTHOR]

This article presents a piecewise linear approximation computation (PLAC) method for all nonlinear unary functions, which is an enhanced universal and error-flattened piecewise linear (PWL) approximation approach. Compared with the previous methods, PLAC features two main parts, an optimized segmenter to seek the minimum number of segments under the predefined software maximum absolute error (MAE), raising the segmentation performance to the highest theoretical level for logarithm, and a novel quantizer to completely simulate the hardware behavior and determine the required bit width and ${\text {MAE}}_{c}$ (MAE in circuits) for hardware implementation. In addition, the hardware architecture is also improved by simplifying the indexing logic, leading to nonredundant hardware overhead. The ASIC implementation results reveal that the proposed PLAC can improve all metrics without any compromise. Compared with the state-of-the-art methods, when computing logarithmic function, PLAC reduces 2.80% area, 3.77% power consumption, and 1.83% ${\text {MAE}}_{c}$ with the same delay; when approximating hyperbolic tangent function, PLAC reduces 6.25% area, 4.31% power consumption, and 18.86% ${\text {MAE}}_{c}$ with the same delay; when evaluating sigmoid function, PLAC reduces 16.50% area, 4.78% power consumption with the same delay, and ${\text {MAE}}_{c}$ ; and when calculating softsign function, PLAC reduces 17.28% area, 11.34% power consumption, 12.50% delay, and 33.28% ${\text {MAE}}_{c}$. [ABSTRACT FROM AUTHOR]

The metric-first-based multiple-input–multiple-output (MIMO) detection algorithm can achieve optimal performance with large stack size, which leads to huge memory consumption and extremely high-sorting complexity. This article presents the algorithm and architecture of a soft-input–soft-output metric-first MIMO detection. The proposed algorithm divides the global stack into multiple local stacks for each nonleaf of the tree. Furthermore, each level of the search tree is performed in parallel to improve the throughput and hardware efficiency. In the proposed algorithm, the hybrid enumeration strategy significantly reduces the computational complexity by avoiding the full enumeration and sorting. The simulation results show the novel algorithm can achieve good performance with lower complexity than other metric-first methods. The proposed detector has been designed for a $4\times 4\,\,64$ -QAM MIMO system and implemented in SMIC 65-nm CMOS technology. The detector can operate at 333-MHz clock frequency and achieve a maximum throughput of 799.2 Mb/s at a 17.3-dB signal-to-noise ratio with area equivalent 242 kg and power consumption of 102.3 mW, and the hardware efficiency is 3.3 Mb/s/kg. Compared with other detectors based on the metric-first algorithm, this article has an obvious advantage in terms of throughput and hardware efficiency. [ABSTRACT FROM AUTHOR]

A novel high-efficient reconstruction architecture of compressed sensing and an area-efficient integrated source-channel decoder based on Reed-Solomon (RS) code are proposed in this letter. The proposed reconstruction architecture only includes a parameter calculation (PC) block and a target locator and evaluator solution (TLES) block, resulting in 30 times higher throughput rate achieved and 85% area saved compared with previously reported reconstruction architecture based on orthogonal marching pursuit (OMP) algorithm. Moreover, the proposed integrated source-channel decoder can reduce 15.3% and 28.5% area respectively for the sampling rate of 25% and 12.5%. [ABSTRACT FROM AUTHOR]

This paper proposes an area-efficient fixed-point architecture for the computation of the discrete cosine transform (DCT) of multiple sizes in high efficiency video coding (HEVC). This result is obtained by comparing different DCT factorizations in order to find the most suitable one for implementation in the HEVC encoder. The recursive structure of fast algorithms, which decompose the $N$ -point DCT by means of two $N/2$ -point DCTs, is exploited to execute computations of small-size DCTs in parallel, thus maximizing the hardware re-usability while maintaining a constant throughput. The simulation results prove that the proposed solution features reduced rate-distortion loss es, with relevant complexity saving compared with the state-of-the-art implementations. Finally, the proposed architecture is exploited to design two families of architectures for the 2D-DCT, namely, folded and full-parallel. [ABSTRACT FROM AUTHOR]

This paper is dedicated to a hardware architecture development for JPEG2000 entropy decoding unit (EDU) which consist of two parts: context modeling unit (CMU) and arithmetic decoding unit (ADU). To achieve a high throughput we propose an efficient pixel skipping scheme to save clock cycles for non-context position in CMU and realize the ADU logic by combinational circuit to keep the result of ADU within the same clock of context which can reduce the latency to zero clock cycle between CMU and ADU. We show that the proposed EDU architecture attains a throughput of 68.66–232.14 Mbps for a single decoding core depending on compression ratios, and consumes 95.79 mW based on SMIC 0.13 um technology. In comparison with the state-of-the-art decoders the proposed EDU architecture provides consistent reconstruction performance with software decoder and comparable throughput, memory and power consumption. [ABSTRACT FROM AUTHOR]

The Lempel–Ziv–Welch (LZW) algorithm is an important dictionary‐based data compression approach that is used in many communication and storage systems. The parallel dictionary LZW (PDLZW) algorithm speeds up the LZW encoding by using multiple dictionaries. This simplifies the parallel search in the dictionaries. However, the compression gain of the PDLZW depends on the partitioning of the address space, i.e. on the sizes of the parallel dictionaries. This work proposes an address space partitioning technique that optimises the compression rate of the PDLZW. Numerical results for address spaces with 512, 1024, and 2048 entries demonstrate that the proposed address partitioning improves the performance of the PDLZW compared with the original proposal. These address space sizes are suitable for flash storage systems. Moreover, the PDLZW has relative high memory requirements which dominate the costs of a hardware implementation. This work proposes a recursive dictionary structure and a word partitioning technique that significantly reduce the memory size of the parallel dictionaries. [ABSTRACT FROM AUTHOR]

Implementation of Canny edge detection algorithm significantly outperforms the existing edge detection techniques in many computer vision algorithms. However, Canny edge detection algorithm is complex, time-consuming process with high hardware cost. To overcome these issues, a novel Canny edge detection algorithm is proposed in block level to detect edges without any loss. It uses sobel operator, approximation methods to compute gradient magnitude and orientation for replacing complex operations with reduced hardware cost, existing non-maximum suppression, block classification for adaptive thresholding and existing hysteresis thresholding. Pipelining is introduced to reduce latency. The proposed algorithm is implemented on Xilinx Virtex-5 FPGA and it provides better performance compared to frame-level Canny edge detection algorithm. The synthesized architecture reduces execution time by 6.8 % and utilizes less resource to detect edges of 512 × 512 image compared to existing distributed Canny edge detection algorithm. [ABSTRACT FROM AUTHOR]

Running discrete Fourier transform (running DFT) is being used to overcome the drawbacks of ping pong buffer technique by employing fast Fourier transform (FFT) for real time spectrum analyzer, However, the major drawback of existing MAC or CORDIC (CO-ordinate Rotational DIgital Computer) based computation of running DFT is error accumulation due to finite precision machine and iterative computation which deteriorate the output in long run. Hence, two new alternative CORDIC based architectures with trade-off area and throughput for the computation of running DFT with refreshing mechanism are proposed in this paper to circumvent the problem of error accumulation. The novelty of these two proposed architectures is low hardware complexity or high throughput and provides the spectrum updates on sample-by-sample basis within tolerable error limit. The proposed designs are implemented using verilogHDL and synthesized using commercially available 0.18μ m CMOS technology to estimate its computation performances. The first order hardware complexities of these proposed architectures are compared with existing architectures. The proposed designs in this paper have potential applications for continuous monitoring of Fourier spectrum in the domain of power spectrum analysis, biomedical signal monitoring systems and communication system. [ABSTRACT FROM AUTHOR]

Otsu's global automatic image thresholding operation is used in various image processing applications. It needs computation of normalized cumulative histogram, mean and cumulative moments that are compute-intensive operations. In this paper, a custom architecture is presented for an efficient computation of Otsu's algorithm along with its utilization as an intellectual property (IP) core in a field programmable gate array (FPGA) based system-on-chip (SoC) environment for the application of connected component analysis (CCA). A self-normalization technique is employed, where single-cycle, read-modify-write operations are performed with block random access memories (BRAMs) and digital signal processing (DSP)slices. The architecture is designed for 640 × 480 size of images that are captured by a high-resolution analouge camera and buffered in a DDR2 SDRAM of Xilinx ML-507 platform at 25.175 MHz clock frequency. The embedded PowerPC processor core is used to control the frame acquisition process. Experimental results on Virtex-5 xc5vfx70t FPGA device show that the architecture utilizes 1.4% slices, 2.7% BRAMs and 3.9% DSP48E slices. The total power consumption of the design is 1440.59 mW. The proposed architecture as an IP core is able to work in real-time with standard VGA resolution video and requires low computational resources. [ABSTRACT FROM AUTHOR]

This study presents a very‐large‐scale integration (VLSI) architecture for the triangular windowed sliding discrete Fourier transform (SDFT) based on COordinate rotation DIgital computer (CORDIC) algorithm. In the literature, the triangular windowed SDFT is obtained by direct cascading of two SDFT modules, whereas the idea of direct cascading leads to the error in the odd bins of the spectrum. The proposed architecture is modified to provide the correct outputs with a high‐throughput rate compared to the existing designs. The SDFT has a recursive structure, and therefore it accumulates the error over iterations as the computation proceeds. A refreshing mechanism is utilised to limit the inaccuracy at the final output. The concept of generalised architecture as an area efficient implementation for obtaining more number of discrete Fourier transform (DFT) bins is introduced. An architecture is implemented using Verilog HDL on FPGA as well as in ASIC platform, and its arithmetic verification is performed in MATLAB. [ABSTRACT FROM AUTHOR]

Since decades, the fractional Fourier transform (FrFT) has attracted researchers from various domains such as signal and image processing applications. These applications have been essentially demanding the requirement of low computational complexity of FrFT. In this paper, FrFT is simplified to reduce the complexity, and further an efficient CORDIC-based architecture for computing discrete fractional Fourier transform (DFrFT) is proposed which brings down the computational complexity and hardware requirements and provides the flexibility to change the user defined fractional angles to compute DFrFT on-the-fly. Architectural design and working method of proposed architecture along with its constituent blocks are discussed. The hardware complexity and throughput of the proposed architecture are illustrated as well. Finally, the architecture of DFrFT of the order sixteen is implemented using Verilog HDL and synthesized targeting an FPGA device ”XLV5LX110T”. The hardware simulation is performed for functional verification, which is compared with the MATLAB simulation results. Further, the physical implementation result of the proposed design shows that the design can be operated at a maximum frequency of 154 MHz with the latency of 63-clock cycles. [ABSTRACT FROM AUTHOR]

The paper presents an efficient VLSI architecture for fast Motion Estimation in video codec using modified Adaptive Rood Pattern Search Algorithm. The proposed architecture uses an interleaved memory arrangement and an early check technique to compute the Sum of Absolute Differences. The proposed design can process High Definition (1080p) video frames in real time while optimizing the hardware area. The architecture has been implemented in verilog HDL and mapped to 45 nm FPGA. It uses only 6.8K gates for the implementation of the datapath and the controller. It achieves a maximum frequency of 120 MHz. However, working at 100 MHz, it is able to process 60 HD (1920×1080) frames per second while consuming 39 mW of power. The proposed architecture achieves premium speed with an optimum power and area requirements and can be suitably incorporated in light-weight video-intensive devices like smart-phones, tablet computers. [ABSTRACT FROM AUTHOR]

Data-access scheme affects the complexity of parallel architectures performing computation of multi-level two-dimensional (2-D) discrete wavelet transform (DWT). In this paper, we made a study on the data-access schemes considered in the existing parallel 2-D DWT architectures. Based on this study, a novel data-access scheme is proposed to avoid data multiplexing, which is common in the existing parallel architectures. Further, a block formulation is presented for vector computation of multi-level lifting 2-D DWT. A generic design of processing unit for computing one-level 2-D DWT is derived using the proposed block formulation. The proposed generic design resizes by a single parameter, i.e., the input-vector size. A regular and modular parallel architecture is derived using the generic processing unit design. The proposed parallel architecture easily scalable for higher block sizes as well as higher DWT levels without sacrificing its circuit regularity and modularity. This is an important feature of the proposed architecture. Comparison result shows that the proposed architecture for three-level DWT and block size 64 offers a saving in 24% area-delay-product (ADP) and 10% power consumption, and higher saving for higher block sizes than the best available similar structure without any overhead memory unlike the existing structure. [ABSTRACT FROM AUTHOR]

Large integer multiplication has been widely used in fully homomorphic encryption (FHE). Implementing feasible large integer multiplication hardware is thus critical for accelerating the FHE evaluation process. In this paper, a novel and efficient operand reduction scheme is proposed to reduce the area requirement of radix-r butterfly units. We also extend the single-port, merged-bank memory structure to the design of number theoretic transform (NTT) and inverse NTT (INTT) for further area minimization. In addition, an efficient memory addressing scheme is developed to support both NTT/INTT and resolving carries computations. Experimental results reveal that significant area reductions can be achieved for the targeted 786432- and 1179648-bit NTT-based multipliers designed using the proposed schemes in comparison with the related works. Moreover, the two multiplications can be accomplished in 0.196 and 2.21 ms, respectively, based on 90-nm CMOS technology. The low-complexity feature of the proposed large integer multiplier designs is thus obtained without sacrificing the time performance. [ABSTRACT FROM AUTHOR]

Featured Application: Wireless Body Sensor Network, Wireless Body Area Network, Remote Healthcare, Internet of Things and Wearable Device. Data transmission of electroencephalography (EEG) signals over Wireless Body Area Network (WBAN) is currently a widely used system that comes together with challenges in terms of efficiency and effectivity. In this study, an effective Very-Large-Scale Integration (VLSI) circuit design of lossless EEG compression circuit is proposed to increase both efficiency and effectivity of EEG signal transmission over WBAN. The proposed design was realized based on a novel lossless compression algorithm which consists of an adaptive fuzzy predictor, a voting-based scheme and a tri-stage entropy encoder. The tri-stage entropy encoder is composed of a two-stage Huffman and Golomb-Rice encoders with static coding table using basic comparator and multiplexer components. A pipelining technique was incorporated to enhance the performance of the proposed design. The proposed design was fabricated using a 0.18 μm CMOS technology containing 8405 gates with 2.58 mW simulated power consumption under an operating condition of 100 MHz clock speed. The CHB-MIT Scalp EEG Database was used to test the performance of the proposed technique in terms of compression rate which yielded an average value of 2.35 for 23 channels. Compared with previously proposed hardware-oriented lossless EEG compression designs, this work provided a 14.6% increase in compression rate with a 37.3% reduction in hardware cost while maintaining a low system complexity. [ABSTRACT FROM AUTHOR]

This brief proposes a new selective-sampling technique that enables spectrum sensing of orthogonal-frequency division multiplexing primary users with 64, 128, 256, 512, and 1024 subcarriers for contemporary cognitive-radio wireless networks. Reconfigurable and memory-efficient very-large scale-integration architecture of the time-domain cyclostationary detector, based on this new technique, has been designed for spectrum sensing. In addition, we present robust coordinate rotation digital-computer architecture for our detector that reduces the computational error to achieve adequate performance. Our detector is post-layout simulated in 90-nm CMOS process and field-programmable gate array implemented that processes the real-world signals captured using universal-software radio peripheral transceivers. In comparison with the state-of-the-art technique, this design alleviated memory requirement by 99% and other hardware resources by 33%. [ABSTRACT FROM AUTHOR]

Due to the sparse multipath characteristic of the channel, millimeter wave (mmWave) channel estimation can be treated as a sparse signal recovery problem. By exploiting the channel sparse characteristics with compressive sensing (CS) theory, sparse signal recovery algorithms can be used for channel estimation. Orthogonal matching pursuit (OMP) algorithm is one of the most popular CS reconstruction algorithms. Hence, in this paper, we present OFDM-based mmWave sparse indoor channel estimation using the OMP algorithm. However, the computational effort for OMP remains high, even for problems of moderate size in real-time applications. Hence, a new VLSI architecture for mmWave channel estimation using the OMP algorithm is designed and simulated using Xilinx 15.4 Vivado HLS simulator in this paper. Our empirical results illustrate the efficacy of the proposed approach. [ABSTRACT FROM AUTHOR]

Acoustic feedback is one of the major issues associated with the hearing aid users which limits the maximum amount of gain available for amplification and degrades the sound quality. In this paper, partitioned time-domain block LMS (PTBLMS) algorithm is proposed for efficient hardware realization of acoustic feedback cancellers (AFCs) in hearing aids. A full-parallel and a folded structure is derived using the proposed PTBLMS algorithm. The folded structure utilizing the time multiplexing of convolution and correlation operation and performing them in one arithmetic unit enables better hardware utilization. A low-complexity design is employed for realization of power normalization unit (for calculating normalized convergence factor) which involves squaring and division operations. The theoretical analysis illustrates that the proposed AFC structures offer L times higher throughput rate and requires proportionately less hardware resource than the existing one where L is the block length. ASIC synthesis results reveal that the proposed folded structure involves nearly 79% less area-delay product and 86% less energy per sample compared to the existing structure. [ABSTRACT FROM AUTHOR]

Binary weight convolutional neural networks (BCNNs) can achieve near state-of-the-art classification accuracy and have far less computation complexity compared with traditional CNNs using high-precision weights. Due to their binary weights, BCNNs are well suited for vision-based Internet-of-Things systems being sensitive to power consumption. BCNNs make it possible to achieve very high throughput with moderate power dissipation. In this paper, an energy-efficient architecture for BCNNs is proposed. It fully exploits the binary weights and other hardware-friendly characteristics of BCNNs. A judicious processing schedule is proposed so that off-chip I/O access is minimized and activations are maximally reused. To significantly reduce the critical path delay, we introduce optimized compressor trees and approximate binary multipliers with two novel compensation schemes. The latter is able to save significant hardware resource, and almost no computation accuracy is compromised. Taking advantage of error resiliency of BCNNs, an innovative approximate adder is developed, which significantly reduces the silicon area and data path delay. Thorough error analysis and extensive experimental results on several data sets show that the approximate adders in the data path cause negligible accuracy loss. Moreover, algorithmic transformations for certain layers of BCNNs and a memory-efficient quantization scheme are incorporated to further reduce the energy cost and onchip storage requirement. Finally, the proposed BCNN hardware architecture is implemented with the SMIC 130-nm technology. The postlayout results demonstrate that our design can achieve an energy efficiency over 2.0TOp/s/W when scaled to 65 nm, which is more than two times better than the prior art. [ABSTRACT FROM AUTHOR]

Tail-biting convolutional codes (TBCC) have been extensively applied in communication systems. This method is implemented by replacing the fixedtail with tail-biting data. This concept is needed to achieve an effective decoding computation. Unfortunately, it makes the decoding computation becomes more complex. Hence, several algorithms have been developed to overcome this issue in which most of them are implemented iteratively with uncertain number of iteration. In this paper, we propose a VLSI architecture to implement our proposed reversed-trellis TBCC (RT-TBCC) algorithm. This algorithm is designed by modifying direct-terminating maximumlikelihood (ML) decoding process to achieve better correction rate. The purpose is to offer an alternative solution for tail-biting convolutional code decoding process with less number of computation compared to the existing solution. The proposed architecture has been evaluated for LTE standard and it significantly reduces the computational time and resources compared to the existing direct-terminating ML decoder. For evaluations on functionality and Bit Error Rate (BER) analysis, several simulations, System-on-Chip (SoC) implementation and synthesis in FPGA are performed. [ABSTRACT FROM AUTHOR]

This study proposes an efficient very large scale integration (VLSI) architecture for quadruple throughput fixed point multiply accumulate circuit (MAC). The proposed n × n bits MAC is used to perform one n × n bits or two n × (n/2) bits or four (n/2) × (n/2) bits MAC operations in parallel. The objective of the proposed MAC is to improve throughput of the existing MAC designs. The proposed and existing designs are implemented by 45 nm CMOS TSMC library and the results show that the proposed architecture achieves better improvement in throughput than existing designs. For example, the proposed 32 × 32 bits MAC architecture achieves 60.4% of improvement in throughput over existing array multiplier‐based double throughput MAC. [ABSTRACT FROM AUTHOR]