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The article offers tips on how to rein chip power, as well as reinvigorate the integrated circuits industry. It suggests embracing co-design, wherein it highlights that processor and systems-on-chip developers achieved their advantage by co-designing packaging, power sources, and software to lessen power without inflating cost or diminishing performance. It recommends to lower the operating voltage. It also proposes to scale performance, adopt 3-D/optical interconnect, and try new materials.

Focuses on chip-packaging technology. Applications; Features; Comparison with other electronic packaging technologies; Configurations in development; Product standardization.

Part II. Looks at the attempt by packing technologists to put more memory in less computer space. Discussion of stacking technologies; Single-chip packages; Move of 3-D memory packages into the mainstream; Price of StackTek's plastic encapsulated Uniframe dynamic random access memory (DRAM) modules; DensePac Microsystems Inc.; More. INSET: A method for comparing packaging prices.

Reports on the marketing of passive devices in chip-scale packages (CSP). Types of passive devices; Definition of a CSP; Growth markets for passive devices in CSP.

Focuses on the proliferation of packaging. Die-bonding architectures; Economic impact of packaging; Tape automated bonding; Alternatives to traditional wire bonding; Size reduction, manufacturing flexibility and handling capability issues. INSET: Who's doing what in BGAs..

Describes the mixed dielectric approach in designing for high-density electronic packaging. Improving electrical performance; Advantages; Performance estimates.

Focuses on the process of developing new electronic packages and evaluating their reliability. Progression of chip-scale-packaging infrastructure; Development of individual package designs; Organizations involved in package development; Die-assembly processes. INSET: Novel lead-frame scheme leads to small.., by Young-Gon Kim..

Focuses on chip-scale packages. Development and qualification cycles; Applications; Performance and compatibility issues; Design concerns; Paradigm shift taking hold in integrated circuit packaging.

Focuses on the technological advances in surface mount packaging technology. Development challenges faced by the electronics industry to address packaging requirements; Revenue generated by surface mount technology; Requirements for enhanced performance and portability of electronic products; Forecast of demand for surface mount components; Data on surface mount usage.

The article focuses on the technology Package-on-Package (PoP) implemented on mobile phone handsets. It discusses the advantages of PoP stacking on handset design, wherein derived products can be created from base design by varying the size of memory or features, on die stacking, and simplification of PCB designs. With the advantages of PoP stacking, it is supported by IDMs, memory suppliers, and assembly equipment vendors along with the development of system logic chips to handle stacking.

The article looks that the available options for the packaging of multiproject wafers (MPWs). These include open-cavity packaging, which is ideal for probing silicon devices and focused ion-beam analyses; chip-scale packaging, which offers protection for the die surface while reducing stress between the PCB and the die; and the stacked-die method.

The article informs that Tessera Inc. is going to officially roll out its MicroPILR packaging technology on April 16, 2007. The company is initially positioning its product as a package-on-package alternative aimed at chips for mobile consumer systems. Tessera said that chip makers will be able to pack onto a substrate many more of the tiny MicroPILR columns than the taller and fatter solder balls traditionally used today.

The article informs that International Business Machines Corp. is going to sample its first commercial devices to make direct metal connections between chips marks a small but significant milestone on the road to 3-D packaging. In April 2007, some semiconductor technologists are going to meet to create a first draft of an industry road map for through-silicon via technology.

The article reports on the warning of a chip design interconnect crisis in the integrated circuits industry by experts at the IEEE International Solid-State Circuits Conference in San Francisco, California, and discusses the application of 3-D packaging technology on the crisis. IBM Corp., Intel Corp. and Qimonda AG outlined the schemes and concepts of 3-D packaging technology. The technology stacks various chips vertically and connects them by silicon vias or related techniques.

The article focuses on the redistributed chip packaging technique used by the Freescale Semiconductor Inc. in Austin, Texas. It saves about 30 percent reduction in packaged die area and thickness using photolithography and copper plating steps to produce chip to chip interconnection that changes traditional wire bonding packages. The company is expected to produce complete manufacturing by 2008 and plans to license the technology to other semiconductor and packaging companies.

This article informs that California Micro Devices Corp.'s 0.4-mm-pitch chip-scale package (CSP) Centurion EMI filter arrays tout higher filtering performance and a reduced form factor along with electrostatic discharge (ESD) protection for wireless handsets. In addition, the fine-pitch application-specific integrated passives are priced to offer significant savings when compared with 0.5-mm CSP ASIP devices and equivalent solutions housed in TDFN packages. The company also noted that the devices offer a combination of EMI filtering performance and ESD protection that cannot be met by discrete components, ceramic-based products or even similar ASIP architectures housed in TDFN packages.

Focuses on the design of the multicore processor and new ethernet acceleration technology developed by Intel Corp. Application of the new central processing unit's technology; Advantage of the performance of the system's design; Impact of the utilization of the multiple core in the enhancement of the delivery of the processor performance.

Reports that XCom Wireless Inc. has begun sampling packaged MEMS-based relays and varactors that achieve 18-GHz frequencies with Q factors in the 150 range. Uses two U.S.-based foundries, which Roger Kuroda, vice-president of engineering declined to identify and expects to move into commercial production; Components of sampled devices; Receives venture capital funding from the Ardesta firm in Detroit; Objectives of MEMS in starting sampling packaged.

Describes a design methodology for an integrated circuit, its package board and its target system board. Design and analysis of the system interconnect; Conceptualization of design.

Describes a complete system view of integrated circuit (IC)-to-package-to-board. Modeling and implementation of a front-side bus through IC, package and board on a personal computer design; Design of the front-side bus system.

Reports on the trend among electronics component suppliers to integrate capacitors and resistors into arrays and networks and to turn to chip-scale and ball-grid-array packaging. Space savings, assembly cost reductions and faster throughput as advantages; Ability of the packaging approach to lower parasitic inductance, equivalent series resistance (ESR) and stray capacitance.

Examines packaging designs for radio frequency integrated circuits. Growth in the wireless industry; Trend in commercial frequency allocations; Plastic package technology.

Reports that U.S. firm Intel Corp. has started using stacked-die packaging to increase memory capacity in integrated circuit systems. Description of stacked-die packaging and stacked memory configuration; Initial use of stacked-die packaging for cell phones; Stacked-die packaging efforts by Intel, Amkor Technology Inc. and the International Microelectronics Consortium.

Describes an atomic-level bonding technique for microelectromechanical system packaging developed by Ziptronix Inc. Potential applications; Advantages over encapsulation methods; Cost benefits.

Presents information on Ohmite Manufacturing Company's ball-grid-series resistor arrays. Its total package power rating; Applications of the resistor arrays; Pricing per 500,000-piece quantities.

Presents information on the plastic ball grid array packages offered by Fairchild Semiconductor Corporation. Price range in lots of 1,000; Contact information.

Reports on the packaging plans of vendors for power metal oxide semiconductor field effect transistors (MOSFET) and integrated circuits as of December 2000. Power MOSFET packaging technologies from International Rectifier; Application of strip trench technology; Advances in trench fabrication technologies.

Deals with the problems with packaging technology for integrated circuits discussed during the HD International technical conference in 2000. Outsourcing by companies in the United States; Evolution of packaging technology; Applications of multichip packages.

Provides information on the evolution of microelectronic packaging components and wafers in the United States. Details on RCA Corporation's Micromodule Program in 1958; Implication of Jack Kilby's invention of the solid circuit built on a single semiconductor chip; Other inventions which took over the emergence of micromodules.

Reports that Apres Technologies company is releasing Scorpion, a suite of products for analyzing noise and `hot spots.' Foundation of Apres; Founder of Apres; Information about Scorpion module's substrate-interconnect-packaging (SIP) Noise Probe; SIP Probe's levels of analysis.

Focuses on the potentials of ball-grid array (BGA) for extending packaging interconnection capability. Types of BGA; Performance and reliability; Financial issues; Comparison of BGA with pin-grid array and quad flat pack; Requirements.

Reports on developments in electronics packaging in Japan. Study of 11 sites in Japan under the auspices of the Japanese Technology Evaluation Center; Focus on making finer pitch in packaging; Using quad flat packs, tape-automated bonding; pin grid arrays; ball grid arrays; Dimensions in packaging; Using ceramics and plastics to plot for inexpensive, lightweight consumer products; Entry into the multichip modules market.

Reports on the agenda of the International Electronic Packaging Society conference on September 12-15, 1993 in San Diego, California. Chip-on-board interconnection; Advances in conventional single-chip packages; Motorola's direct chip attach; Availability of viable infrastructure; Cost in comparison with standard packaging.

Focuses on the trend toward surface-mount assembly processes that makes ball-grid array (BGA) packaging a choice for many types of devices. Advantage of BGA packaging; Why several manufacturers are incorporating heat spreaders into their BGA packages; How companies maintain the cost of complex devices with the use of BGA packaging.

Discusses the changes in the packaging process of silicon devices. Advantage of chip-scale packages (CSP) in memory applications; Limitations of the implementation of CSPs; Primary focus of flip-chip packages development in North America.

Discusses the popularity of ball-grid-array (BGA) packaging in electronic engineering. Growth of BGAs; What chip scales can provide; Sales of BGAs; Exploration of chip BGAs by several companies.

Focuses on personal computer (PC) board assembly design technologies that demonstrate the challenges facing test engineers. Surface mount technology (SMT); Component technology; Automatic optical inspection (AOI) or automated vision-system technology; Ball grid arrays; X-ray testing for solder-joint connections prior to functional test; HP 5DX system's image analysis engines.

Discusses the importance of alternate packaging solutions to cope with the trend to greater miniaturization of electronic devices. Increased functionality per unit area on personal computer (PC) boards; Impact of product repackaging on product value; Cost of miniaturization; Package elimination using COB or other bare-die technology; ASIC integration; Issue of component availability.

Describes the advantages of direct chip-attach (DCA) or flip chip approach in electronic packaging. Increasing performance and functionality; Benefits of placing components closer together; Flip-chip process.

Reports on developments in electronic packaging involving printed-circuit boards. Integrated circuit density requirements; Impact of increasing densities; Increasing lead counts in the electronic data processing; Performance applications.

Focuses on chip-scale electronic packaging. Features; Applications; Technological developments; Comments from contract manufacturers.

Focuses on the emerging packaging technologies to address assembly work issues for electronics manufacturers. Development of standard, leaded quad flat packs (QFP); Advanced area-array packages such as ball-grid array (BGA) and flip chip; Non-standard surface mount packages such as tape-automated bonding (TAB); Acceptance of TAB, chip on board (COB), flip-chip and direct attach technologies.

Suggests that very small packages called chip-scale packages (CSP) are competing with raw die that threatens to replace packaged ICs altogether. The lack of formal packaging standards covering CSPs; Actions by the Electronic Industries Association-Japan; Hitachi's 672-pin face-gown ball-grid array (FD-BGA); The use of flex foil in small portable applications; How CSP compares with other package alternatives.

Discusses 3-D packaging and talks about some of the differences between a 3-D all-silicon device and a 3-D assembly of 2-D packages. The Irvine Sensors-Jet Propulsion Lab 3-D artificial neural network and how it uses 3-D electronics; When the first-generation 3-D stacked silicon products appeared; More.

Focuses on the importance of packaging aspects when designing sub-0.5 micron components. The importance of handling packaging concurrently with chip design; Die size and package selection; Area flip-chip technology; Power variations in CMOS chips related to fluctuations in logic activity, and the creation of thermal `minicycles' that degrade the solder-joint life.

Reports on the proposal for the establishment of an advanced national electronics Packaging Research Center in the United States. Goal of the center; Basic research; Market studies.

Focuses on technological innovations in ball-grid-array (BGA) packages. Efforts by manufacturers to increase BGA production and lower manufacturing costs to compete with quad flat-packs (QFP); Introduction of die-size package; Tessera Inc.'s licensing of chip-scale packaging technology; Development of a wafer-processing scheme by researchers at Sandia National Laboratories in Albuquerque, New Mexico.

Discusses the importance of quality control checks for multichip modules (MCMs). Material challenges to multichip manufacturers; Quality-control strategy of the MicroModule Systems Inc.; Material selection and process changes; Impact of bare-die supply on feasibility, quality and realibility; Importance of long-term relations between MCM manufacturers and major integrated circuits suppliers; Stress tests to MCM.

Discusses the debate on the use of array and peripheral packaging technology. Use of the technologies by semiconductor companies; Acceptance of the pin-grid array package; Popularity of peripheral-leaded packages; Use of direct chip-attach to reduce size and weight by eliminating extra packaging; Advantages of flip-chip technology; Combination of flip-chip with pin-grid arrays.

The article focuses on the adoption of the Silicon Integration Initiative of standards to enhance and develop integrated circuit (IC) design by turning to three dimensional (3D) packaging. It says that Si2 is introducing the Open3D Project to render interoperable 3D design that flows through open standards. Companies are interested in their quest to devise standards for 3D chips based on through-silicon vias (TSVs) with an Open3D meeting which aims to set initial standards for 2012.