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This article presents a low-jitter and low-spur charge-sampling phase-locked loop (CSPLL). A charge-domain sub-sampling phase detector is introduced to achieve a high phase-detection gain and to reduce the PLL in-band phase noise. Even without employing any power-hungry isolation buffers, the proposed phase detector dramatically suppresses the reference spurs by both minimizing the modulated capacitance seen by the voltage-controlled oscillator (VCO) tank and by reducing the duty cycle of the sampling clock. A 50μW RF-dividerless frequency-tracking loop is also introduced to lock the CSPLL robustly when the VCO faces a sudden frequency disturbance. Fabricated in a 40-nm CMOS process, the prototype CSPLL occupies a core area of 0.13 mm 2 and synthesizes 9.6-to-12-GHz tones using a 100-MHz reference. At 11.2 GHz, it achieves a reference spur of −77.3 dBc and an RMS jitter of 48.6 fs while consuming 5 mW.

This article presents a millimeter-wave (mmW) frequency synthesizer based on a new charge-sharing locking (CSL) technique. A charge-preset capacitor is introduced for charge sharing with a resonant LC-tank for phase correction, while the resulting charge residue on the sharing capacitor is processed by a digital frequency-tracking loop (FTL) against the process, voltage, and temperature (PVT) variations. Furthermore, a general phase noise (PN) theory of CSL, with injection locking (IL) being a special case, is proposed based on a unified multirate z-domain model, supporting any frequency division ratio N and CSL (or IL) strength β. The new theory sheds light not only on all IL-like PN phenomena (chiefly, its ``loop'' bandwidth being up to half of the reference frequency, and the oscillator PN increasing 3 dB beyond the ``loop'' cutoff frequency) but also on how to choose the CSL bandwidth via the sharing capacitor in order to optimize the rms jitter performance. The prototype in 28-nm CMOS achieves 77-fs rms jitter in 21.75--26.25 GHz while consuming 16.5 mW for mmW quadrature frequency generation.

Fully integrated power management circuits are promising candidates to provide small form factors and meet high power density demand of modern computing platforms. This article presents a new fully integrated dc-dc converter topology based on electromagnetically coupled class-D LC oscillators that enables up to 2.5 GHz switching frequency, allowing aggressive scaling of the on-chip passives. On-chip transformers and flying capacitors are designed to electromagnetically couple the two oscillators, and gigahertz-range switching frequency is achieved by the quasi-adiabatic switching of the parasitic capacitors. The proposed converter is implemented in a 0.18-μm CMOS process occupying 1.61 mm² for 7.8 nH inductance (high efficiency version) and 0.37 mm² for 3.1 nH (high power density version), achieving 1 W/mm² peak power density. This work also proposes a duty-cycling scheme that improves the efficiency under light loads, which stays close to the peak from 4 μW up to 0.5 W, and in continuous operation mode the output voltage ripple is 12 mV without attaching any output capacitor thanks to the four-phase electromagnetic power delivery scheme.

Autonomous-driving features necessitate a fault-tolerant (FT) power-management unit in 48-V automotive applications. This article presents a monolithic single-phase closed-loop masterless FT four-to-one hybrid Dickson converter IC for high-conversion-ratio 48-V automotive multi-phase applications. The chip includes: 1) a mixed-signal droop-based valley-current ON-time quasi-fixed-frequency control, which enables masterless multi-phase operation capability; 2) single-point short-circuit fault and open-circuit fault detection and blocking of any power switches or flying capacitors; 3) an optimized high-voltage (HV) power stage with fully integrated flying-capacitor-sourced gate drivers without any external bootstrap capacitors; 4) a glitch-free cross-coupled bootstrapped HV level shifter; and 5) a dual-leg bidirectional closed-loop current-sensing circuit optimized for the hybrid Dickson topology. The design was fabricated in a 0.13- $\mu \text{m}$ 90-V automotive silicon-on-insulator (SOI) bipolar-CMOS–DMOS (BCD) process. The measured results confirm the operation over 20–60-V input, 3.3-V nominal output, 3-A maximum load, and 320-kHz effective switching frequency within the automotive-grade −40 °C–+125 °C ambient temperature. The design achieves above 90% measured efficiency at maximum conversion ratio and load at room temperature. A three-phase system is used to evaluate and confirm the fault-blocking capability and continuous power delivery upon detection of a fault.

Current retinal prostheses (RPs) have not achieved useful vision restoration, as their resolution is limited by power dissipation and complexity of interconnect. This article presents an inductively powered wireless system on a chip (SoC) for an electrically controlled, optically addressed retinal prosthetic system. The SoC interfaces to a co-fabricated nanoengineered photosensitive electrode array using only two wires. To reduce the thermal dissipation near sensitive retinal tissue, the proposed design pushes voltage regulation and charge-balanced stimulation control off the implant via a duty-cycled wireless charge metering technique. A calibration technique compensating for power fluctuation caused by eye movement is also presented. Implemented in 180-nm CMOS and delivering up to $3~\mu \text{C}$ of charge at 20-nC resolution, the SoC achieves 73% RF-to-stimulation power efficiency.

This article presents a fully integrated Cryo-CMOS system on chip (SoC) for quantum computing. The proposed SoC integrates a radio frequency (RF) pulse modulator for qubit state manipulation, a multi-tone signal generator and a coherent receiver for qubit state readout, and 22 DACs for high-speed voltage pulsing of qubit gates. By adopting frequency division multiplexing and direct digital synthesis (DDS), the RF pulse modulator can control up to 16 qubits over a single RF line, and the readout receiver can detect the state of up to six qubits simultaneously. The proposed SoC also integrates a microcontroller for low latency on-chip signal processing and increased flexibility in implementing quantum instruction sets. A detailed analysis of qubit-state readout fidelity and the impact of finite DAC resolution on two-qubit gate fidelity is also included in this article, together with an electrical specification summary. The SoC is implemented in Intel’s 22 nm FFL fin field-effect transistor (FinFET) process, and it is characterized both at room and 4 K temperatures. The performance of each specific block is measured, with the readout characterized in a loop-back configuration. Generation of the control signals required for a full Rabi oscillation experiment is also demonstrated. This article also describes the cryogenic thermalization techniques used to integrate the SoC in the dilution refrigerator and shows temperature measurements during operation.

A 10–35-GHz mixer-first receiver is proposed for use in digital multiple-input–multiple-output (MIMO) arrays. Techniques are proposed to enhance the linearity of such receivers, both at baseband and the RF mixer switches. Techniques to mitigate charge sharing due to local oscillator (LO) overlap are also proposed. Detailed simulation results are provided to illustrate the benefits of these techniques. An integrated circuit prototype is fabricated in 28-nm bulk CMOS and fully characterized. The receiver has built-in programmability to tradeoff gain for linearity. The receiver achieves a peak in-band IIP3 of +14.1 dBm, a peak gain of 14.5 dB, and a noise figure of 12.5 dB, in its nominal setting.

In this article, a fully integrated capacitorless low-dropout regulator (LDO) is presented for Internet-of-Things (IoT) edge sensor application. To achieve sub-1-V operation and fast transient response with low quiescent current, the conventional operational transconductance amplifier (OTA)-based error amplifier (EA) is replaced with oscillator-based voltage-to-time converter and time-domain signal processing, including time-domain edge-based frequency comparator (FC) and event-driven voltage mode charge pump (CP). Compared with the conventional phase frequency detector (PFD), the proposed clock-edge-based FC achieved more than six times power reduction. Event-driven CP is adopted to drive analog power transistor and the transient response is enhanced by feedforward capacitor $C_{\mathrm {FD}}$ and coarse–fine CP control. To further reduce the power consumption, multi-voltage domain and clock frequency optimization are implemented. A prototype chip is fabricated in a standard 65-nm CMOS process. The design only consumes 310-nA quiescent current while achieving 0.5–1.2-V input range, $1.0\times 10^{6}$ load dynamic range, and 3-fs figure of merit (FoM).

This article presents a relative-prime-based time-interleaved (RP TI) sub-ranging successive-approximation register (SAR) analog-to-digital converter (ADC) with on-chip background skew calibration. The proposed calibration aligns the sampling time of every fine ADC (F-ADC) to that of a particular coarse ADC (C-ADC) that works as a reference ADC. To avoid the unwanted calibration tone from the reference ADC, the C-ADC is also time-interleaved to make all samples undergo the same kick back. By setting the numbers of the time-interleaved channels of the C-ADCs and F-ADCs in a relative-prime relationship, every C-ADC can be evenly shared by every F-ADC; thus, the timing skews between the interleaved sub-ADCs are calibrated by adjusting the sampling edges of every F-ADC to the particular C-ADC working as a reference ADC. An 18-channel TI 10-bit 2.2-GS/s SAR ADC was implemented as a prototype with 28-nm CMOS. Owing to the proposed on-chip background skew calibration, the peak tone by skew was reduced by 23 dB from −40 to −63 dB, which corresponds to the residual skew reduction from 1.6 ps to 113 fs near the Nyquist input. Thus, the prototype ADC achieved a spurious free dynamic range (SFDR) over 52.8 dB and a signal-to-noise-and-distortion ratio (SNDR) over 44.9 dB with 18.2-mW power consumption, which leads to a Walden figure-of-merit (FoM) of 57.8 fJ/conversion-step.

This article presents a 6.78-MHz single-stage dual-output regulating rectifier for miniaturizing the true wireless devices. The proposed rectifier topology realizes ac–dc power conversion and dual-output voltage regulation simultaneously in one single stage, using only four on-chip power transistors, thereby reducing chip area and off-chip components and improving the system power conversion efficiency. We integrate high voltage (HV) and low voltage (LV) transistors in the proposed dual-output rectifier for HV and LV output voltages, respectively. The proposed two independent three-level current-wave modulation (CWM) controllers realize voltage conversion and regulation for each output independently, with the instant transient response and no cross-regulation problem. The proposed dual-output regulating rectifier, fabricated in 0.18- $\mu \text{m}$ CMOS using 1.8-/3.3-V devices, can deliver a total maximum power of 1.02 W at the dual-output voltages of 1.8 and 3.3 V. The circuit achieves a measured peak efficiency of 91.9% with an instant load-transient response for a load current step between 20 and 200 mA. The cross-regulation between the dual-output voltages is unnoticeable.

This article describes a 2.1-MHz relaxation oscillator (RxO) for energy-harvesting Internet-of-Things (IoT) sensor nodes. The RxO features an asymmetric swing-boosted RC network and a dual-path comparator to surmount the challenges of sub-0.5-V operation while achieving temperature resilience. The former enables alternating the common-mode voltages at the output of the RC network to facilitate the sub-0.5-V operation, while the latter is outfitted with a delay generator for tracking the temperature-sensitive delay of the comparator. Prototyped in 28-nm CMOS, the RxO occupies a tiny footprint of 5,200 $\mu \text {m}^{2}$ . The power consumption is 1.4 $\mu \text{W}$ at 0.35 V. The measured temperature stability is 158 ppm/°C (average of seven chips) over −20 °C–120 °C. It scores the best energy efficiency (667 fJ/cycle) among the reported MHz-range RxOs and has a figure-of-merit (181 dB) that compares favorably with the state-of-the-art.

In response to fast-growing high-voltage (HV) power IC market demands, this article presents a tri-state double step-down (DSD) power converter to achieve direct 12V/24V- to-1V dc–dc power delivery with high efficiency and high power density. By taking advantage of the benefits from both three-level and DSD converter topologies, the converter allows the use of lower voltage rating power devices and thus facilitates high switching frequency operation with smaller power passives. An online flying capacitor voltage ( $V_{\mathrm {CF}}$ ) rebalancing scheme is introduced to optimize switching nodes voltages and minimize power path mismatch for improved reliability and efficiency. During startup transients, an in-situ precharge rate regulation technique manages the charging process on flying capacitors precisely in avoidance of potential device breakdown. An IC prototype of this design was fabricated using a 180 nm HV bipolar-CMOS-DMOS (BCD) process with an active area die of 6.3 mm2. At 3-W output power, a chip power density of 476 mW/mm2 is accomplished. The online $V_{\mathrm {CF}}$ rebalancing reduces voltage mismatch between the flying capacitors by 16.7%. The converter achieves peak efficiencies of 88.3% and 92.1% for 24V/1V and 12V/1V conversion, respectively.

An 8-bit 10-GHz 8 $\times $ time-interleaved successive-approximation-register (SAR) analog-to-digital converter (ADC) incorporates an aggressively scaled digital-to-analog converter (DAC) with grouped capacitors in a symmetrical structure to afford a threefold reduction in the bottom-plate parasitic capacitance. A detailed study rigorously analyzes the effect of gradient on the proposed DAC layout. The DAC additionally implements quantized sub-radix-2 scaling with redistributed redundancy. A high-speed dual-path bootstrapped switch decouples the critical signal from the nonlinear parasitic capacitance to boost the sampling spurious-free dynamic range (SFDR) by more than 5 dB. Fabricated in a 28-nm CMOS process, the ADC demonstrates an SNDR of 36.9 dB at Nyquist while consuming 21 mW, yielding a figure-of-merit of 37 fJ/conv.-step, the best among state-of-the-arts.

Fully integrated voltage regulators (FIVRs) can improve the performance and reduce the power consumption of a system-on-chip (SoC) by providing point-of-load voltage regulation with dynamic voltage scaling. The desirable attributes of FIVRs include high power efficiency, high power density, and fast transient response, which are difficult to achieve due to on-chip area constraint and parasitic effects. Low-quality and low-density on-chip inductors and capacitors are currently the main performance-limiting factors. This article presents a switched-inductor-capacitor (SIC) voltage converter that can operate more efficiently with compact on-chip air-cored metal-tracked inductors than existing step-down voltage converters. The SIC converter consists of an inductor, a flying capacitor, and three power switches, and it can provide fine-grained voltage regulation by using pulsewidth-modulation (PWM) control. The unique SIC converter topology eases the on-chip inductor integration by positioning the inductor at the input power supply and reducing the current stress of the inductor. A proof-of-concept fully integrated SIC voltage regulator is fabricated in a 65-nm CMOS process, with an area of 1.3 mm $\times $ 0.5 mm excluding pads. The output voltage can be regulated from 0.6 to 0.9 V given a 1.2-V input power supply. The output voltage ripple is below 56 mV over the entire range of output voltages and load currents. The peak power efficiency is 78% at an output of 0.9 V and 406 mA. The peak power density is 730 mW/mm2, and the peak current density is 820 mA/mm2.

Thin-film transistor (TFT) technologies often have only n-type conductivity, and therefore, the realization of CMOS-like logic gates becomes a challenge. Conventional approaches to realize logic gates in such technologies result in limited swing and excessive direct-path current. In this article, we propose logic gates that mitigate these problems. As a proof of concept, a three-to-eight decoder and a column of pixel circuits with n-type only a-Si:H TFTs have been fabricated on flexible plastic substrates. Simulation and measurement results demonstrate that the decoder maintains unity stage-to-stage gain, while its static leakage current is reduced by 85% compared with the conventional implementation. The layout area is reduced by 20% compared with prior implementations. In addition, the circuit performance under applied mechanical strain was also consistent with the theory.

To satisfy the requirements for multi-standard frequency generation, mode-switching oscillators are developed to increase the frequency tuning range without incurring considerable phase noise penalty. However, this improvement in the tuning range is often limited by the parasitics of the circuitry for mode selection and tuning. To address this challenge, this work presents a dual-core octave-tuning VCO using a switch-less tertiary magnetic coupling loop. The design employs the benefits of transformer-switching without incurring switch loss and quality factor degradation and also the benefits of mode switching without the parasitics from the mode selection and tuning network. The VCO employs a non-constant $RC$ scaling for the capacitors’ bank, across the tuning bits, and positive feedback dc-coupled inductive-degenerated output buffer to maximize the tuning range. Implemented in 22 nm fully depleted silicon-on-insulator (FDSOI), the dual-core VCO achieves a 72% tuning at 8–17 GHz and a figure-of-merit-tuning ( $\text {FoM}_{T}$ ) of 208.8 dBc/Hz at 11 GHz. The chip operates from a 0.45 V supply with a power consumption of 17–33 mW and a core area of 0.39 mm2. To the best of our knowledge, the VCO achieves the highest $\text {FoM}_{T}$ and lowest supply for designs over 10 GHz.

This article presents a single-trim switched capacitor (SC) CMOS bandgap reference (BGR) for battery monitoring applications. For a single-temperature trimming, $\beta $ -compensation and curvature correction techniques are employed to minimize non-proportional-to-absolute-temperature (PTAT) errors. In conjunction with these techniques, this article proposes dynamic element matching (DEM) techniques with low-pass filtering which employs the decimation filter of a delta-sigma analog-to-digital converter (ADC) in a digital domain. It achieves a further reduction of non-PTAT errors resulting from mismatches of the bias current, of the PNP transistor current gain ( $\beta $ ), and of the gain coefficient in the SC summing amplifier. The remaining PTAT errors are canceled out using a single room-temperature trimming. The bandgap circuit is implemented using vertical PNP transistors with a $\beta $ of about 2.7 at 27 °C in a 0.18- $\mu \text{m}$ CMOS process. The proposed SC BGR achieves a $3\sigma $ inaccuracy of +0.02%, −0.12% from −40 °C to 125 °C. From a 1.8-V supply voltage, it consumes $17~\mu \text{A}$ at 27 °C and occupies an active area of 0.38 mm2.

A proactive clock-gating system (PCGS) in a 7-nm Qualcomm® Hexagon™ digital signal processor (DSP) improves performance or energy efficiency by reducing the magnitude of supply voltage ( $V_{\mathrm {DD}}$ ) droops. The PCGS integrates a digital power meter (DPM) to monitor the power per cycle based on microarchitectural events and a voltage-clock-gating (VCG) circuit with a power-delivery-network (PDN) model to predict the $V_{\mathrm {DD}}$ response to DPM power changes. When the PDN model anticipates a potential $V_{\mathrm {DD}}$ -droop violation, the VCG adapts the clock frequency ( $F_{\mathrm {CLK}}$ ) by gating the global clock to reduce the actual $V_{\mathrm {DD}}$ -droop magnitude. Silicon measurements of the PCGS in the 7-nm DSP demonstrate a 10% higher $F_{\mathrm {CLK}}$ or 5% lower $V_{\mathrm {DD}}$ .

On-chip oscillators are popular clocking solutions for a wide range of circuits and systems due to their ease of integration and low form factor, but their energy efficiency is typically limited to the pJ/cycle range by a number of contributors, such as active biasing currents, frequency dividers, and comparators. This work presents an on-chip oscillator for energy-efficient Internet-of-Things (IoT) applications based on a duty-cycled digital frequency-locked loop (DFLL) that reduces energy by disabling energy-hungry components and only periodically reactivating them to keep the output frequency stabilized during temperature drifts. A test chip is implemented in 65-nm CMOS and achieves 18.8 fJ/cycle (10.5 nW at 560 kHz) while maintaining an average steady-state temperature stability of 96.1 ppm/°C from 0 °C to 100 °C.

To reduce the circuit area and support a 10-bit fully nonlinear gamma correction, a new column driver architecture constructed with a 10-bit one-stage low-voltage resistor string digital-to-analog converter (RDAC) (LVDAC) and a switched-capacitor amplifier (SC-AMP) is proposed. Because the LVDAC is implemented with low-voltage (LV) MOSFETs instead of high-voltage (HV) MOSFETs, the circuit area is drastically reduced. In addition, there is no need to use level shifters that must be used in the traditional column driver between the LV logic circuit and the HV DAC, thus further decreasing the circuit area. By utilizing a one-stage DAC architecture, the effective bit resolution of nonlinear gamma correction can be increased compared with previous two-stage DACs, in which the output voltages of the coarse DAC are interpolated. The output voltage of LVDAC is amplified by SC-AMP to reach the requisite HV to drive the display panel. In designing the SC-AMP, the effects of non-idealities, such as random offset voltage, capacitance mismatch, parasitic capacitance, and switching error are quantitatively analyzed, and circuit techniques to suppress the effects are presented. The proposed column driver was fabricated using a 90-nm CMOS process. The circuit area of the proposed 10-bit column driver is only 69.0% of that of the conventional 8-bit column driver because the conventional 8-bit HV RDAC (HVDAC) using 5-V MOSFETs is replaced by the proposed 10-bit LVDAC using 1.2-V MOSFETs, along with the SC-AMP with a gain of four to support the 5-V output voltage range. The measurement results show that the differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.2/−0.18 and +0.42/−0.06 LSB, respectively, with an LSB voltage of 4.5 mV. The measured maximum deviation of voltage outputs (DVOs) between 50 channels is 7.9 mV.

This article presents the control circuit of a power converter that regulates the computing speed of a digital circuit. The proposed circuit implements a digital delay regulation of a digital delay line (DDL) matched with the ring oscillator (RO) that clocks the digital subsystem. The converter regulates the supply voltage of the digital subsystem so that the propagation delay through the DDL matches a time reference. Consequently, the frequency of the RO tracks the DDL delay and the frequency keeps a controlled value over process, voltage, and temperature (PVT). A 65-nm CMOS prototype validates the proposed method. The prototype includes an Arm Cortex-M33 CPU and memories optimized for sub-threshold operation. With the proposed method, the computing performance of the CPU is guaranteed for running real-time application while minimizing the supply voltage margins.

This article presents a multiprotocol DSP-DAC-based SerDes architecture. The lookup table (LUT)-based DSP provides flexible number of taps for equalization, and soft switching driver allows 1.2-Vpp transmit swing to achieve higher SNR. The architecture employs cascaded phase-locked loop (PLL)-based flexible clocking to support a wide range of data rates from 10 to 112 Gb/s. The $LC$ PLL generates 10.25–14.5 GHz but distributes a divided version of the clock between 2.25 and 3.625 GHz with less than 140-fs integrated jitter. The local ring PLL multiplies the clock to 28 GHz but keeps the jitter less than 180 fs thanks to wide loop bandwidth. The transmitter is implemented in 7-nm FinFET consuming 175 mW with 1.56-pJ/bit efficiency.

A 135-Mb 0.021- $\mu \text{m}^{2}$ 6-T high-density SRAM bit cell with write-assist circuitries was successfully implemented by using 5-nm HK-metal gate FinFET with EUV and high-mobility channel (HMC) technology. This article proposes the metal capacitor coupling negative bitline (NBL) and the charge-sharing lower cell-VDD (CS-LCV) write-assist techniques to reduce the SRAM minimal supply voltage. Flying bitline (FBL) architecture is also implemented to improve the high-density SRAM macro-bit density by 5%. Silicon data show that both NBL and LCV write-assist techniques can improve the overall SRAM minimal supply voltage performance by more than 300 mV at the 95th percentile.

This work presents a low-jitter, low-reference-spur ring voltage-controlled oscillator (ring VCO)-based injection-locked clock multiplier (ILCM). Since the proposed triple-point frequency/phase/slope calibrator (TP-FPSC) can accurately remove the three root causes of the frequency errors of ILCMs (i.e., frequency drift, phase offset, and slope modulation), the ILCM of this work is able to achieve a low-level-reference spur. In addition, the calibrating loop for the frequency drift of the TP-FPSC offers an additional suppression to the in-band phase noise of the output signal. This capability of the TP-FPSC and the naturally wide bandwidth of the injection-locking mechanism allows the ILCM to achieve a very low-RMS jitter. The ILCM was fabricated in a 65-nm CMOS technology. The measured reference spur and RMS jitter of the 2.4-GHz output signal were −72 dBc and 140 fs, respectively, both of which are the best among the state-of-the-art ILCMs. The active silicon area was 0.055 mm2, and the power consumption was 11.0 mW.

As any analog-to-digital converter (ADC) with a front-end sample-and-hold (S/H) circuit, successive approximation register (SAR) ADC suffers from a fundamental signal-to-noise ratio (SNR) challenge: its sampling kT/C noise. To satisfy the SNR requirement, the input capacitor size has to be sufficiently large, leading to a great burden for the design of the ADC input driver and reference buffer. This article presents an SAR ADC with a kT/C noise-cancellation technique. It enables the substantial reduction of ADC input capacitor size but without the large kT/C noise penalty. It greatly relaxes the requirement for ADC input driver and reference buffer. Built in 40-nm CMOS, a prototype 13-bit ADC has only 240-fF input capacitance and occupies a small area of 0.005 mm2. Operating at 40 MS/s, it achieves a 69-dB signal-to-noise-and-distortion ratio (SNDR) across the Nyquist frequency band while consuming 591 $\mu \text{W}$ of power.

Fully integrated voltage regulation, while important for a number of applications, is challenging due to the limitations of on-chip passive components, particularly inductors. This work demonstrates a new direction in passive-component integration through the design and implementation of a silicon-integrated merged- $LC$ resonator, used in a resonant switched-capacitor voltage regulator. The merged- $LC$ resonator combines flying capacitance and inductance into a single structure to reduce ac resistive losses, achieving higher efficiency and power density. The voltage regulator is implemented in a 0.18- $\mu \text{m}$ CMOS process and achieves 85.5% efficiency at 0.47 W without off-chip passive components. Light-load efficiency is extended through the use of OFF-time modulation (OTM); the design achieves $\mu \text{s}$ load transients.

This article proposes an active-matrix organic light-emitting diode (AMOLED) pixel circuit for mobile displays with high resolution to improve the image quality of the display panel. The proposed pixel circuit, which consists of six low-temperature polycrystalline silicon thin-film transistors (TFTs) and two capacitors, compensates for variations in the threshold voltage (Vth) and subthreshold slope (SS) of driving TFTs at low gray levels. Such compensations are achieved by extending the compensation time in the diode-connection scheme, resulting in a reduction in the OLED current error (OCE) of the proposed pixel circuit. In addition, the proposed pixel circuit connects two capacitors in parallel to the gate node of the driving TFT, thus increasing the total storage capacitance value in a given capacitor area in the emission phase, resulting in a reduction in voltage distortion at the gate node. Moreover, the OCEs caused by the IR drop of ELVDD and the crosstalk due to parasitic capacitances are thoroughly investigated and analyzed. The measurement results of the proposed pixel circuit show that the OCEs at the 64th and 128th gray levels are reduced from ±3.5 and ±6.5 to ±2.0 and ±0.8 LSB, respectively, by extending the compensation time from 6.5 to 195 $\mu \text{s}$ . Therefore, the proposed pixel circuit is highly suitable for mobile AMOLED displays requiring high image quality.

A fully integrated DC–DC converter that uses isolated switched-capacitor (SC) cores in a stacked way is presented. The converter can transform a wide input voltage range from 7.5 up to 42 V by the multiple available voltage conversion ratios (VCRs), which are realized through reconfiguration of the stackable cores. In addition, stacking simplifies the design to the low-voltage isolated SC core. Level shifters are included to fulfill the high-voltage interfaces, while bulk biasing circuits ensure the correct driving of the switches in the cores. As such, the power converter is implemented in a 0.35- ${\mu }\text{m}$ CMOS technology and produces a stable 3-V output with less than 5% voltage ripple for a peak output power of 2.1 mW.

Tiny implantable medical devices in millimeter size demand advanced wireless power solutions that operate at hundreds of megahertz and mainly use passive rectifiers for ac–dc power conversion. A conventional cross-connected (CC) rectifier can operate with high frequency and low input voltage but only achieves good efficiencies in a very narrow input power range, due to the shoot-through and reverse currents. This work presents a CMOS passive rectifier with active bias tuning (ABT), allowing a widely extended input range with high power conversion efficiency (PCE). In addition, we compensate for the process, voltage, and temperature variations with the ABT scheme that leads to a robust design for very-high-frequency (VHF) operation. Meanwhile, we propose a peak $V_{\mathrm {OUT}}$ searching scheme to indicate the charging/discharging directions for the ABT. We obtain a bias-voltage balancing among stacked rectifier stages with a switched-capacitor network. The proposed rectifier is fabricated in a 65-nm CMOS process. Measurement results of three chips show that the proposed rectifier improves the PCE over a wide input range, with an average maximum PCE of 64.4%.

A fully integrated micro-electromechanical system (MEMS) accelerometer with extremely low noise level (22 ng/ $\surd $ Hz) and sufficiently low power consumption (17 mW) for emerging applications (such as infrastructure monitoring and next-generation oil and gas exploration) was developed. By applying concurrent operations of detection and control (enabled by a unique MEMS element) and reducing servo-signal leakage and noise caused by an interaction of 1-bit quantization and asymmetric mass deformation in the digital domain, a ninefold-lower noise level is achieved in comparison with state-of-the-art low-noise low-power MEMS accelerometers. The MEMS element was fabricated on 6-in Si/SOI/Si bonding wafers, while the detection and driver integrated circuits were fabricated as interface circuits with the standard 0.13- $\mu \text{m}$ complementary metal–oxide–semiconductor (CMOS) process and the high-voltage 0.35- $\mu \text{m}$ CMOS process, respectively. The power consumption of the developed MEMS accelerometer is 17 mW from 1.4-, 1.8-, and 12-V supplies, and it has an input range of ±0.55 g and bandwidth of 400 Hz.

The bandwidth-enhanced oversampling successive approximation (BE-OSA) readout technique is proposed in this article to reduce the noise floor of the readout circuit for micro-electromechanical systems (MEMS) capacitive accelerometer while achieving high power efficiency in terms of the figure of merit (FoM). The open-loop structure has been widely used in MEMS capacitive accelerometer for the Internet of Things (IoT) applications due to its low power consumption. However, in the open-loop accelerometer, the capacitance variation in the sensing element is limited to the femto-farad level to overcome nonlinearity. As a result, the thermal noise from the parasitic capacitance becomes significant. The ability of the readout circuit to deal with thermal noise is determined by the front-end switched-capacitor capacitance-to-voltage convertor (SC CVC) rather than the back-end analog-to-digital converter (ADC). To reduce the noise floor, the traditional oversampling method increases the sampling frequency of SC CVC by increasing the transconductance of the amplifier, but this leads to low power efficiency. In this work, the BE-OSA technique provides a high power efficiency method as it increases the sampling frequency of SC CVC without increasing the transconductance of the amplifier. The SC CVC based on the BE-OSA technique is demonstrated in a readout circuit fabricated by a commercial 0.18- $\mu \text{m}$ Bipolar-CMOS-DMOS (BCD) process and tested with a femto-farad MEMS accelerometer. The measurement results show that compared with the readout circuit without using the BE-OSA technique, the readout circuit using BE-OSA reduces the noise floor from 2.5 to 0.9 aF/ $\surd $ Hz. Compared with other similar works, the proposed readout circuit achieves the best power efficiency in terms of both the absolute power efficiency ( $FoM_{2} =243$ fJ) among the switched-capacitor readout circuits and the relative power efficiency ( $FoM_{3} = 0.14$ ).

Hybrid switched-capacitor (SC) converters have shown great promise in achieving high efficiency and power density for dc–dc conversion. By combining an SC stage with an inductor filter stage, benefits from both approaches can be realized. In this work, a hybrid Dickson SC converter with a 4:1 native conversion ratio and regulated output voltage range of 0.3–0.9 V from a 3.4 to 4.2-V lithium-ion battery and the effective switching frequency of 1 MHz was implemented in 65-nm bulk CMOS process. The converter achieves maximum output current of 1.5 A, the power density of 330 mW/mm2, and a peak efficiency of 92.6%. The converter is packaged using flip-chip technology with passive devices co-packaged through a high-density interposer to minimize the packaging parasitics and volume. A segmented gate driver is used to enhance the converter efficiency and reliability by maintaining low-voltage ringing across the power switches. The converter is integrated with closed-loop output voltage regulation, dead-time control, and active capacitor–voltage balancing to maximize the active and passive device utilizations.

This article reports an offset-canceled DRAM sense amplifier with coupling capacitors to store and cancel the offset arising from random variations of the threshold voltages of the amplifying transistors. Analytical calculations of the average and standard deviation of the decision threshold voltages, defined as the voltage in the cell capacitor that bifurcates into binary levels when activated, are performed on various DRAM sensing schemes and their comparison results are presented. Based on the analysis, the proposed sense amplifier scheme using coupling capacitors is shown to offer the least amount of variation in the decision threshold, thereby increasing the sensing margin of the overall DRAM design. The coupling capacitors not only compensate for the random offset of the sense amplifiers but also mitigate the effect of the mismatch of the bitline capacitances in the open bitline scheme. Measurement on the experimental chip fabricated in a 65-nm CMOS process validates the analysis and confirms the superior performance of the proposed DRAM sensing scheme.

This article proposes a split-phase flipping-capacitor rectifier (SPFCR) to resolve the hard tradeoff between the number of capacitors and the energy-extraction efficiency for capacitive piezoelectric energy-harvesting (PEH) interfaces. By splitting the capacitor usage into multiple phases, this article can achieve the most number of flipping phases using the same number of capacitors when compared with the state of the art. We also relaxed the implementation complexity by removing insignificant SFPCR flipping phases without sacrificing the energy-harvesting efficiency. To improve further the input power adaptation, the flipping capacitors are reconfigured as a multiple-voltage-conversion-ratio (MVCR) switched-capacitor dc–dc converter during the non-flipping period without using extra passives. Maximum-power-point tracking (MPPT) is also accomplished using the full-bridge rectifier (FBR) fractional open-circuit voltage ( $V_{{\text {OC}, \text {FBR}}}$ ) to relax the voltage-tolerance requirements. Fabricated in 0.18- $\mu \text{m}$ CMOS, the proposed 21-phase SPFCR PEH interface demonstrates a measured maximum output power improving rate (MOPIR) of up to 9.3 $\times $ with $V_{D}= 0.12$ V (6.5 $\times $ with $V_{D}= 0$ V) when compared with the conventional FBR interface over an equivalent FBR input power range ( $P_{{\text {in, FBR}}}$ ) from 0.15 to 5.57 $\mu \text{W}$ .

Pseudo-resistor circuits are used to mimic large value resistors and base their success on the reduction of occupied areas with respect to physical devices of equal value. This article presents an optimized architecture of pseudo-resistor, made in standard CMOS 0.35 $\mu \text{m}$ technology to bias a low-noise transimpedance amplifier for high-sensitivity applications in the frequency range 100 kHz–10 MHz. The architecture was selected after a critical review of the different topologies to implement high-value resistances with MOSFET transistors, considering their performance in terms of linearity of response, symmetric dynamic range, frequency behavior, and simplicity of realization. The resulting circuit consumes an area of 0.017 mm2 and features a tunable resistance from ${20\quad \text {M} \Omega }$ to ${20\quad \text {G} \Omega }$ , dynamic offset reduction due to a more than linear $I$ – $V$ curve, and a high-frequency noise well below the one of a physical resistor of equal value. This latter aspect highlights the larger perspective of pseudo-resistors as building blocks in very low-noise applications in addition to the advantage in occupied areas they provide.

This article presents a cryptographic key protection technique from physical security attacks through Si-backside of IC chip. Flip-chip packaging leads to a serious security hole that allows emerging backside physical security attacks. The proposed backside buried metal (BBM) structure forming a meander wire pattern on the Si-backside detects unexpected disconnection of the meander and warns the malicious attempts to expose a vulnerable Si substrate. Moreover, the BBM meander also shields key information of cryptographic circuit from both passive side-channel attacks and active laser fault injection as well. Unlike other conventional laminate-based protection, this backside monolithic approach does not require frontside wiring resources or additional packaging layers, resulting in only 0.0025% size-overhead. The BBM meander was formed on the backside of a 0.13- $\mu \text{m}$ CMOS cryptographic chip by wafer-level via-last BBM processing.

A “second-order” passive mixer-first receiver is proposed to improve channel selectivity, linearity, and noise figure (NF) in the presence of out-of-band blockers, by presenting an impedance that rolls off at 40 dB/decade as the load to an N-path filter. The synthesis of this impedance is described in a step-by-step manner starting from the required impedance transfer function to its actual circuit realization. Various tradeoffs and limitations of the architecture are described in detail, and layout-related techniques are also provided. Two integrated circuit prototypes were fabricated in 28-nm bulk CMOS as proof of concept for this circuit, including a low-power version. The receiver, capable of broadband operation from 0.2 to 2 GHz, achieves an out-of-band IIP3 of +33 dBm and a blocker P1dB of +12 dBm. Additionally, it achieves an NF of 4.4 dB with less than 2-dB degradation in NF for a 0-dBm blocker.

This article presents a phase-locked loop (PLL) design that overcomes design challenges imposed by FinFET CMOS nodes, notably high gate resistance and middle-end-of-line parasitics. We propose a track-and-hold charge pump (THCP) and an automatic loop gain control, which not only overcome these challenges but also improve the PLL jitter and reference spur performance. The proposed THCP achieves −115-dBc/Hz in-band phase noise while consuming only $53~\mu \text{W}$ , which is less than 1% of total PLL power consumption. The ring-based PLL achieves both 388-fsrms integrated jitter and reference spurs at −80 dBc. At 4.0 GHz, this PLL consumes 5.9 mW from a 0.9-V supply, translating to a figure of merit of −240.5 dB. The PLL is fabricated in the TSMC 7-nm FinFET CMOS technology.

This article presents a controller IC for smart contact lens (SCL). For wireless telemetry, we propose a transmitter supporting dual-mode operations with a single external loop antenna. In the wireless-powered backscattering load-shift keying (LSK) mode, the transmitter is configured to use the antenna as an ${L}$ for magnetic resonance coupling. The transmitter switches its configuration to be an active LC oscillator circuit in the RF-radiated transmission mode. To suppress the average power consumption, a 0.2% duty cycling is applied with a controlled timing schedule while minimizing static power consumption in the sleep mode. To reduce the effect of instantaneous discharging, the period of data transmission is shortened by transmitting data with a higher rate. The designed IC is fabricated using 0.18- $\mu \text{m}$ CMOS. For in vitro verifications in both modes, an SCL is implemented by integrating the IC, a glucose sensor, a thin-film battery, a loop antenna, and a supply-regulating capacitor. The IC achieves a power consumption of 143 nW with an input dynamic range of 89 dB.

This article presents a capacitively coupled voltage-controlled oscillator (VCO)-based sensor readout featuring a hybrid phase-locked loop (PLL)- $\Delta \Sigma $ modulator structure. It leverages phase-locking and phase-frequency detector (PFD) array to concurrently perform quantization and dynamic element matching (DEM), much-reducing hardware/power compared with the existing VCO-based readouts’ counting scheme. A low-cost in-cell data-weighted averaging (DWA) scheme is presented to enable a highly linear tri-level digital-to-analog converter (DAC). Fabricated in 40-nm CMOS, the prototype readout achieves 78-dB SNDR in 10-kHz bandwidth, consuming 4.68 $\mu \text{W}$ and 0.025-mm2 active area. With 172-dB Schreier figure of merit, its efficiency advances the state-of-the-art VCO-based readouts by $50\times $ .

Resilient circuits based on in situ timing monitoring adaptive voltage–frequency scaling (AVFS) eliminate excess time margins caused by process, voltage, and temperature (PVT) variations but suffer from 50% throughput loss during error recovery when operating at a half frequency. We propose a bi-directional adaptive clocking circuit to provide fine frequency tuning with zero latency for AVFS system. It can either stretch the clock cycle when there are timing errors to ensure correct function or compress the cycle when there are excess timing margins. To support a wide frequency range, we generate multiple phase clocks based on two delay lines and select one appropriate phase clock to obtain a stretched output clock, where balanced clock paths are obtained by a time-to-digital converter and dynamic-OR gates. Applied to a wide-operating-range AVFS system of an SHA-256 accelerator with transition detector (TD) latches, the whole AVFS system is able to respond to errors in one clock cycle, with dynamic-OR gates collecting all the errors in half a cycle and adaptive clocking circuit stretching at the current cycle. Fabricated in 28-nm CMOS, chip measurement shows that it achieves 38.6%–69.4% power gains at near threshold while reducing throughput loss during error recovery.

This article presents a 230-GHz wideband harmonic voltage-controlled oscillator (VCO) with large output power based on a compact and low-loss structure of coupled standing wave oscillators. In order to boost the output power, oscillators are coupled together without adding extra passive loss to the circuit. Transistors with inductive drain impedances provide the necessary negative resistance to the oscillators while simultaneously acting as active variable capacitors for frequency tuning and generate the desired second-harmonic power through their nonlinearities. Transmission lines at the drains are responsible for creating the inductive impedance as well as coupling adjacent oscillators and routing and combining the output power. Therefore, the circuit has a compact structure that minimizes passive losses. A varactor-less frequency tuning scheme is used and allows for wideband operation without sacrificing the output power. In addition to oscillator coupling and minimizing the losses, the output power has been boosted by engineering the harmonic impedance that is seen by the transistors in the circuit. The prototype chip was implemented in a 65-nm CMOS process. The output power of the VCO covers 219–238 GHz frequency band (8.35% tuning range) and delivers 3.4-dBm maximum output power. The minimum measured phase noise is −105.8 dBc/Hz (at 10-MHz offset) while consuming 195 mW from a 1.5-V supply.

This article presents a BJT-based temperature-to-digital-converter (TDC) that achieves ±0.25 °C 3 sigma -inaccuracy from -40 °C to +180 °C after a heater-assisted voltage calibration (HA-VCAL). Its switched-capacitor (SC) ADC employs two sampling capacitors and, thus, the minimum number of critical sampling switches, which minimizes the effects of switch leakage at high temperatures and improves accuracy. The TDC is also equipped with an on-chip heater, with which the sensing BJTs can be rapidly (2 and operates from 1.8 V.

This article presents a power-efficient purely voltage-controlled oscillator (VCO)-based second-order continuous-time (CT) $\Delta \Sigma $ analog-to-digital converter (ADC), featuring a modified digital phase-locked loop (DPLL) structure. The proposed ADC combines a VCO with a switched-ring oscillator (SRO)-based time-to-digital converter (TDC), which enables second-order noise shaping without any operational transconductance amplifiers (OTAs). The nonlinearity of the front-end VCO is mitigated by putting it inside a closed loop. An array of phase/frequency detectors (PFDs) is used to relax the requirement on the VCO center frequency and thus reduces the VCO power and noise. The proposed architecture also realizes an intrinsic tri-level data-weighted averaging (DWA). A prototype chip is fabricated in a 40-nm CMOS process. The proposed ADC achieves a peak signal-to-noise-and-distortion ratio (SNDR) of 69.4 dB over 5.2-MHz bandwidth, while operating at the 260 MS/s and consuming 0.86 mW from a 1.1-V supply.

Energy-optimal operation is one of the key requirements of the Internet-of-Things (IoT) applications to increase battery life. In this article, using a combination of dynamic voltage scaling (DVS) and adaptive body biasing (ABB), the energy-optimal operation is achieved with a given fixed operating frequency determined by application demands. Based on the observation that the ratio of leakage power to dynamic power can be an accurate indicator for the optimal operating point, the proposed method dynamically tracks the minimum energy operating points by adjusting supply voltage and body bias with very low hardware and power overhead. A custom dc–dc converter for supply voltage regulation and charge pumps for body bias generation were implemented with the proposed method in a Cortex-M0 processor. Since SRAM is included in the same energy optimization loop as the processor, a custom SRAM was designed to match the processor speed. The design is fabricated in an Mie Fujitsu Semiconductor (MIFS) 55-nm deeply depleted channel (DDC) CMOS and the proposed approach achieves energy consumption within 4.6% of optimal at 1 MHz across five process corners and temperatures from −20 °C to 125 °C. The fabricated processor achieves 6.4 pJ/cycle at 0.55-V and 500-kHz clock frequency.

A fully integrated wake-up receiver in 65-nm low-power (LP) CMOS technology is presented. The receiver’s RF front end consists of a 40-stage MOS self-mixer using gate biasing to optimize the sensitivity; the baseband circuits use time-encoded analog signals to efficiently implement a matched filter with a DC offset cancellation loop at minimal power consumption. When operating at 434 MHz, the receiver has a −79.1-dBm sensitivity with a 110-ms latency while consuming 420 pW from 0.4 V. When operating at 1.016 GHz with the same latency, the sensitivity is −74 dBm and power consumption is 470 pW.

This article presents a cascaded architecture of a frequency synthesizer to generate ultra-low-jitter output signals in a millimeter-wave (mmW) frequency band from 28 to 31 GHz. The mmW-band injection-locked frequency multiplier (ILFM) placed at the second stage has a wide bandwidth so that the performance of the jitter of this frequency synthesizer is determined by the GHz-band, digital subsampling phase-locked loop (SSPLL) at the first stage. To suppress the quantization noise of the digital SSPLL while using a small amount of power, the optimally spaced voltage comparators (OSVCs) are presented as a voltage quantizer. This article was designed and fabricated using 65-nm CMOS technology. In measurements, this prototype frequency synthesizer generated output signals in the range of 28–31 GHz, with an rms jitter of less than 80 fs and an integrated phase noise (IPN) of less than −40 dBc. The active silicon area was 0.32 mm2, and the total power consumption was 41.8 mW.

This article presents a methodology to design a circuit to compensate for process skew by exploiting an inherent dimension-dependent effect of process skew on change in the threshold voltage. We design a voltage reference circuit with a hybrid architecture of bandgap reference (BGR) and CMOS reference, which generates a nominal voltage level of (bandgap - threshold). By compensating the process skew of the threshold term with the proposed dimension-induced effect as well as the temperature dependence, the circuit achieves the simultaneous benefits of BGR and CMOS references. For verification, the circuit was fabricated in three wafers of a 0.18- $\mu \text{m}$ CMOS including extreme slow and fast corners. With an active area of 0.0045 mm2, it consumes 192 pW at room temperature. Measurement from 45 chips (15 chips per wafer) shows untrimmed process/voltage/temperature variations of 0.53%, 0.020%/V, and 33 ppm/°C, respectively.

A full-rate clock and data recovery loop employs a three-stage ring voltage-controlled oscillator, a master–slave passive sampler as both a phase detector and a filter, and a new flip-flop to achieve a loop bandwidth of 170 MHz. Implemented in 45-nm CMOS technology, the circuit occupies an area of 14 $\mu \text{m}\,\,\times $ 26 $\mu \text{m}$ and exhibits a jitter tolerance of 2 UI at 5 MHz and a recovered clock jitter of 459 fs with 231 – 1 pseudorandom bit sequence.

This paper presents the analysis and design of wideband I/Q CMOS modulators and transmitters. Non-idealities and performance limitations of Cartesian transmitter and modulator systems are discussed, and circuit design techniques and analyses are shown. A DC-60 GHz I/Q modulator/transmitter chip in 45-nm SOI CMOS is presented as a critical building block for next-generation multi-standard and high-capacity wireless backhaul links. The modulator consists of a wideband quadrature signal generator, wideband buffers, and two current-combined DC-100 GHz low-noise double-balanced mixers driven in quadrature. The 1.4 mm2 modulator chip achieves 60 dB of dynamic range in a 1-GHz bandwidth, with an OP1dB of ~ −10 dBm, thus enabling spectrally efficient high-order modulation schemes such as 256-QAM. The I/Q modulator achieves 200 Gb/s in 16-QAM (50 Gbaud/s) while consuming 200 mW, resulting in record 1-pJ/bit modulation efficiency. In addition to backhaul links, the modulator is an attractive and cost-effective alternative to short-range optical links for data center interconnects (DCI) and for chip-to-chip communications.