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This paper analyzes the thermal and reference noises of two types of successive-approximation-register (SAR) analog-to-digital converters (ADCs): the time-interleaving (TI) and the partial-interleaving (PI) Pipelined. The thermal noise is investigated with accurate estimation by deriving closed-form expressions according to the noise equivalent models on different phases. Additionally, the design trade-off between power and noise for two ADC architectures is discussed in detail. On the other hand, the reference noise due to the large switching transient, which significantly degrades the conversion accuracy, is analyzed and verified through behavioral and circuit level simulations of two ADC architectures operating at 500 MS/s for 10-bit resolution. The simulated results show the supremacy of the PI Pipelined-SAR (PS) architecture over the TI-SAR because it exhibits less reference noise sensitivity. [ABSTRACT FROM AUTHOR]

A systematic design approach using signal flow graph (SFG) is presented in this paper, tailored for integrated reconfigurable switched-capacitor (SC) power converters. To achieve an optimal power stage, an unified signal flow graph (USFG) model is developed. System transfer function and I/O impedance can be evaluated based on it. To verify the design approach, the paper demonstrates a step-up/down reconfigurable SC power converter with five optional gain ratios. A dual-loop control scheme is employed to reconfigure the converter according to the instantaneous line/load conditions. A low-power, digital controller is designed in the subthreshold region for the feedback control loop. The converter was fabricated with a 130-nm CMOS process. Experimental results show that its output can be continuously regulated from 0.4 to 2.2 V, while allowing the input voltage to randomly vary between 0.9 and 1.5 V. The line regulation is maintained below 1.4%, with a lowest value of 0.07%. The maximum efficiency of 90.22% is measured at 0.55-V output voltage and 20-mW load. [ABSTRACT FROM PUBLISHER]

This paper presents expressions for the waveforms and design equations to satisfy the ZVS/ZDS conditions in the class-E power amplifier, taking into account the MOSFET gate-to-drain linear parasitic capacitance and the drain-to-source nonlinear parasitic capacitance. Expressions are given for power output capability and power conversion efficiency. Design examples are presented along with the PSpice-simulation and experimental waveforms at 2.3 W output power and 4 MHz operating frequency. It is shown from the expressions that the slope of the voltage across the MOSFET gate-to-drain parasitic capacitance during the switch-off state affects the switch-voltage waveform. Therefore, it is necessary to consider the MOSFET gate-to-drain capacitance for achieving the class-E ZVS/ZDS conditions. As a result, the power output capability and the power conversion efficiency are also affected by the MOSFET gate-to-drain capacitance. The waveforms obtained from PSpice simulations and circuit experiments showed the quantitative agreements with the theoretical predictions, which verify the expressions given in this paper. [ABSTRACT FROM PUBLISHER]

This paper proves a novel sampling theorem with constant amplitude and variable width pulses. The theorem states that any bandlimited baseband signal within \pm0.637 can be represented by a pulsewidth modulation (PWM) waveform with unit amplitude. The number of pulses in the waveform is equal to the number of Nyquist samples and the peak constraint is independent of whether the waveform is two-level or three-level. The proof of the sampling theorem uses a simple iterative technique that is guaranteed to converge to the exact PWM representation whenever it exists. The paper goes on to develop a practical matrix based iterative technique to generate the PWM waveform that is guaranteed to converge exponentially. The peak constraint in the theorem is only a sufficient condition. In fact, many signals with higher peaks, e.g., lower than Nyquist frequency sinusoids, can be accurately represented by a PWM waveform. [ABSTRACT FROM PUBLISHER]

Motivated by different applications in circuits, electromagnetics, and optics, this paper is concerned with the synthesis of a particular type of linear circuit, where the circuit is associated with a control unit. The objective is to design a controller for this control unit such that certain specifications on the parameters of the circuit are satisfied. It is shown that designing a control unit in the form of a switching network is an NP-complete problem that can be formulated as a rank-minimization problem. It is then proven that the underlying design problem can be cast as a semidefinite optimization if a passive network is designed instead of a switching network. Since the implementation of a passive network may need too many components, the design of a decoupled (sparse) passive network is subsequently studied. This paper introduces a tradeoff between design simplicity and implementation complexity for an important class of linear circuits. The superiority of the developed techniques is demonstrated by different simulations. In particular, for the first time in the literature, a wavelength-size passive antenna is designed, which has an excellent beamforming capability and which can concurrently make a null in at least eight directions. [ABSTRACT FROM PUBLISHER]

This paper studies linear passive electrical networks with ideal switches. We employ the so-called linear switched systems framework in which these circuits can be analyzed for any given switch configuration. After providing a complete characterization of admissible inputs and consistent initial states with respect to a switch configuration, the paper introduces a new state reinitialization rule that is based on energy minimization at the time of switching. This new rule is proven to be equivalent to the classical methods of Laplace transform and charge/flux conservation principle. Also we illustrate the new rule on typical examples that have been treated in the literature. [ABSTRACT FROM PUBLISHER]

In this paper, a low-voltage fourth-order 2-2 cascade delta–sigma (\Delta\Sigma) modulator using the proposed double-sampling switched-operational-amplifier (SOP)-based integrator is presented. In the analog part of the \Delta\Sigma modulator, most of the power consumption comes from the SOP used in the integrator. Hence, the requirement of the SOP must effectively be relaxed to reduce the power consumption of the modulator. In each cascade stage, the second-order \Delta\Sigma modulator with a cascade-of-integrators input feedforward structure is used to reduce the output swing. The second integrator output of the first stage is directly connected to the second stage to simplify circuit design on the analog part. Furthermore, the double-sampling SOP-based integrator is also adopted to reduce the applied clock frequency by half. In this paper, systematic means of designing the presented modulator and searching the minimum current of the SOP in a specified supply voltage are also developed. The presented \Delta\Sigma modulator is fabricated in a 0.18-\mu\m 1P6M CMOS technology. The chip core area without PADs is 1.57 \mm^2. The modulator achieves an 84-dB peak signal-to-noise plus distortion ratio and an 88-dB dynamic range in 20-kHz signal bandwidth with a clock frequency of 2 MHz. The power consumption of the presented modulator core is 0.66 mW at a supply voltage of 1 V. The presented modulator can also be operated in a wide range of supply voltages from 1.8 V down to 0.9 V without seriously degrading the performance. [ABSTRACT FROM PUBLISHER]

We present a compact, continuous, and numerically stable version of a tantalum oxide (TaOx) memristor model which can be employed for robust and reliable simulations of large scale memristor based circuits. The original model contains a piecewise differentiable function in the memductance expression and discontinuous step functions in the state equation. Additionally, the original model does not set a proper upper bound for the state variable and may admit blowing up solutions due to an exponential power term, preventing the use of it for numerically reliable simulations. Considering these drawbacks, we modify the original model so as to i) simplify the memductance function while removing its piecewise differentiable nonlinearity, ii) include a proper window function for the ON state dynamics, which is missing in the original model, iii) modify and bound the exponential power term to prevent an uncontrollable blow-up of the solutions, and iv) apply a process called unification, allowing us to remove the step functions inherent in the model, which is a novelty in state-limited memristor models. We validate the accuracy of the proposed model via DC and transient simulations, dynamic route map analysis and a Spice implementation of an anti-series configuration, showing the applicability of the model. [ABSTRACT FROM AUTHOR]

This work investigates the problems of decentralized fault estimation within a finite-time interval (FTI) and fault-tolerant control for nonlinear interconnected distributed parameter systems under the situation of unpredictable faults. First, the fault estimator using interconnected information is designed to estimate the occurred faults over an FTI. Second, the designed fault-tolerant controller has a non-fragile characteristic and can make the considered system satisfy the prescribed performance index. Additionally, this article considers a real scenario where multiple switching channels exist in the network and supposes that the channel switching follows a Markovian switching law with discrete state. Furthermore, by establishing a global Lyapunov functional based on graph theory and employing the canonical Bessel–Legendre inequality method, the final results that are less conservative can be obtained reasonably. Finally, the feasibility, practicability and superiority of the main results are illustrated through three simulations. [ABSTRACT FROM AUTHOR]

The continuous-time pipelined (CTP) ADC is a promising emerging high-speed analog-to-digital conversion technique that achieves anti-alias filtering and analog-to-digital conversion in one step. Driving such a converter is easy, thanks to its resistive input impedance. RC time-constant shifts, which will occur in practice due to a change in ambient temperature, degrade the performance of such converters. The aim of this work is to understand this phenomenon, quantify the resulting SNDR degradation, and thereby derive design tradeoffs. The theory is compared with measurements from a three-stage CTP that targets 70dB SNDR in a 100MHz bandwidth while sampling at 800MS/s. [ABSTRACT FROM AUTHOR]

An ultra-low power, energy efficient, and versatile resistive sensor interface for energy constrained internet-of-things applications is presented. The sensor interface includes an efficiently duty-cycled current digital-to-analog converter (I-DAC) and an asynchronous successive approximation register (SAR) analog-to-digital converter (ADC), which enables a fully-dynamic operation. A fast start-up circuit is used in the duty-cycled I-DAC to speed up the start-up procedure and to minimize the energy consumption. A system-level correlated double sampling (CDS) technique is employed to suppress ADC offset and 1/ $f$ noise. To tackle the limited robustness against supply and temperature variations observed in a previous implementation of the sensor interface, a system-level ratiometric measurement (SRM) approach is employed in an updated design, which is described here in detail. The chip is fabricated in 65nm CMOS technology. Thanks to the all-dynamic nature, measurement rates from 0.1S/s to 12.5kS/s can be supported with an inherent scaling of power over 3 orders of magnitude. A reported lowest power consumption of 0.32nW is achieved at 0.1S/s. Adaptable resolution with efficient scaling of power can also be achieved by adjusting sensor interface settings and/or using oversampling and averaging. The achieved figure-of-merit (FoM), which ranges from 98 to 552fJ/conv-step is also the lowest among prior designs. Thanks to the SRM approach, only 3.6%/V and 21ppm/ $^\circ \text{C}$ supply and temperature sensitivity are obtained, respectively. [ABSTRACT FROM AUTHOR]

Element matching approaches based on Optimal Combination Algorithms (OCAs) are methods that try to calibrate element mismatches in data converters by rearranging the mapping relations between circuit elements and control logics. This work for the first time proposes a universal method and its corresponding Figure-of-Merit to evaluate the performance of various OCA approaches. It adopts the quantile of integral nonlinearity as the criterion and is consequently compatible with most of matching OCAs. Dynamic performance and the corresponding effective-number-of-bits (ENOB) limited by mismatches are also investigated. A critical feature of the proposed method is its robustness to the disturbance of element standard deviation as long as the standard deviation is in a reasonable region. Merits of our method have been explained and proved mathematically, and also been verified numerically by data extracted from previously reported works and their reproduction by authors, which together make this proposal more convincing and rigorous. Due to those merits, our proposed method could also help designers to specify a feasible standard deviation for circuit elements when they are designing data converters with OCAs. [ABSTRACT FROM AUTHOR]

With the continuous shrinking of technology node, conventional CMOS logic circuits suffer from high power issues due to both increasing leakage current and long traffic delay. Hybrid non-volatile (NV) logic-in-memory architecture, where emerging NV memories are distributed over a logic-circuit plane, has been widely investigated to overcome these limitations. Magnetic tunnel junction (MTJ) is considered as one of the most promising NV candidates thanks to its non-volatility, fast access speed, infinite endurance and easy 3-D integration with CMOS technology. Recently, several 1-bit NV full-adder (FA) structures using MTJ have been proposed to build low-power high-density arithmetic/logic unit for processors. However, one of their major disadvantages is partial non-volatility since they only use MTJs as one of their operands. For the purpose of extending 1-bit NV-FA to multi-bit structure and realizing full non-volatility, synchronous 8-bit NV-FA architecture is presented in this paper, where all the input signals are stored in MTJs instead of CMOS registers. Three possible structures are proposed with respect to different locations of NV data. By using an industrial CMOS 28 nm design kit and a MTJ compact model, we validated their functionalities and compared their performances in terms of power consumption and area, etc. [ABSTRACT FROM AUTHOR]

This paper analyzes the effect of operational amplifier (OPAMP) input offset on continuous-time (CT) delta-sigma (\Delta\Sigma) modulators with current-mode feedback digital-to-analog converters (DAC). Our analysis shows that the input offset leads to either increased harmonics or increased noise floor of the modulator, depending on whether a DAC shuffling scheme, such as data-weighted averaging (DWA), is applied or not. Analysis and mathematical derivation are given and verified by transistor-level simulations. An input-offset cancellation scheme is proposed and demonstrated by simulation results. [ABSTRACT FROM AUTHOR]

Recently, it has been demonstrated that memristors can be utilized as logic gates, control switches as well as memory elements. In this paper, we analyze the different AND, OR, and NOT logic gates which are based on memristors. In addition, a novel design for a memristor-based switch is presented, which can be used in the peripheral read/write circuits of the memristor-based memory. Moreover, methods of consecutive read with long refresh intervals and fast write for the proposed design are also discussed. Another highlight of this work is the analysis of the proposed memristor-based crossbar architecture which has a series of excellent features, such as good-compatibility, high-density, non-volatility, low-power, and good-scalability. Simulation results also show that the proposed memory array has superior performances compared to other memristor-based arrays proposed in the existing technical literature. [ABSTRACT FROM AUTHOR]

This paper proposes a new timing storage circuit based on memristors. Its ability to store and reproduce timing information in an analog manner without performing quantization can be useful for a wide range of applications. For continuous-time (CT) digital filters, the power and area costly analog delay blocks, which are usually implemented as inverter chains or their variants, can be replaced by the proposed timing storage circuits to delay CT digital signals in a more efficient way, especially for low-frequency biomedical applications that require very long tap delays. In addition, the same timing storage circuits also enable the storage of CT digital signals, extending the benefits of CT digital signal processing (DSP) to applications that require signal storage. As an example, a 15-tap CT finite impulse response (FIR) Savitzky-Golay (S-G) filter was designed with memristor-based delay blocks to smoothen electrocardiographic (ECG) signals accompanied with high-frequency noise. The simulated power consumption under a 3.3-volt supply was 6.63 \muw. [ABSTRACT FROM AUTHOR]

Traps that are located in the gate oxide of MOSFETs have been established as a cause of low-frequency noise phenomena. Analysis of such noise is usually based on frequency domain, stationary models. It has been shown that such simplistic models produce erroneous results for circuits with time-varying bias conditions. Tian proposed an idealized trap model with the goal of capturing the nonstationary behavior of oxide traps, and were able to elucidate the experimentally observed large noise power reduction in switched MOSFET circuits which eluded any explanation obtainable with legacy stationary models. In this paper, we build on their seminal work and first identify an oversight in their model derivation which had produced an incorrect expression for the single trap noise spectrum. We next derive the correct spectrum expression, verify it against detailed idealized trap simulations and discuss its implications. The idealized trap model is amenable to analytical derivations and useful as a first stage in understanding nonstationary trap noise. We then demonstrate that noise simulations based on a detailed trap description implemented in a compact MOSFET model in a circuit simulator are needed for an accurate characterization of low-frequency noise in switched MOSFET circuits that matches experimental results. [ABSTRACT FROM AUTHOR]

This paper presents a novel ultra-low voltage level shifter for fast and energy-efficient wide-range voltage conversion from sub-threshold to I/O voltage. By addressing the voltage drop and non-optimal feedback control in a state-of-the-art level shifter based on Wilson current mirror, the proposed level shifter with revised Wilson current mirror significantly improves the delay and power consumption while achieving a wide voltage conversion range. It also employs mixed-Vt device and device sizing aware of inverse narrow width effect to further improve the delay and power consumption. Measurement results at 0.18 \mum show that compared with the Wilson current mirror based level shifter, the proposed level shifter improves the delay, switching energy and leakage power by up to 3\times, 19\times, 29\times respectively, when converting 0.3 V to a voltage between 0.6 V and 3.3 V. More specifically, it achieves 1.03 (or 1.15) FO4 delay, 39 (or 954) fJ/transition and 160 (or 970) pW leakage power, when converting 0.3 V to 1.8 V (or 3.3 V), which is better than several state-of-the-art level shifters for similar range voltage conversion. The measurement results also show that the proposed level shifter has good delay scalability with supply voltage scaling and low sensitivity to process and temperature variations. [ABSTRACT FROM AUTHOR]

This paper presents a new energy efficient successive approximation analog-to-digital converter (ADC) using a charge recycling and LSB-down switching scheme for the capacitive digital-to-analog converter (CDAC). Compared to the conventional binary weighed CDAC, the proposed technique exhibits a 95% reduction in switching energy, a 50% reduction in capacitor area, and with 30% reduction in nonlinearity under the same unit capacitor size and matching condition. The improvement on the switching energy consumption is the best among reported CDAC switching techniques. To validate the technique, a prototype of 10-bit ADC is fabricated in a 0.13 \mum CMOS technology using standard capacitors. With a unit capacitor size of 30 fF, the ADC consumes 15.6 \muW from a 0.5 V digital supply and a 1 V analog supply. The measured signal-to-noise-plus- distortion ratio is 54.6 dB (ENOB=8.8) at 1.1 MS/s. The FOM is 31.8 fJ/conv.-step, which is among the best when normalized to the same unit capacitor size. [ABSTRACT FROM AUTHOR]

Energy harvesting is an emerging technology for powering wireless sensor nodes, enabling battery-free operation of these devices. In an energy harvesting sensor, a power management circuit is required to regulate the variable harvested voltage to provide a constant supply rail for the sensor circuits. The power management circuit needs to be compact, efficient, and robust to the variations of the input voltage and load current. A closed-form power expression and custom control algorithm for regulation of a switched-capacitor DC-DC converter with optimal conversion efficiency are proposed in this paper. The proposed regulation algorithm automatically adjusts both the voltage gain and switching frequency of a switched-capacitor DC-DC converter based on its input voltage and load current, increasing the power efficiency across a wide input voltage range. The design and simulation of a fully integrated circuit based on the proposed power managing approach is presented. This power management circuit has been simulated in a 0.25 \mum standard CMOS process and simulation results confirm that with an input voltage ranging from 0.5 V to 2.5 V, the converter can generate a regulated 1.2 V output rail and deliver a maximum load current of 100 \muA. The power conversion efficiency is higher than 74% across a wide range of the input voltage with a maximum efficiency of 83%. [ABSTRACT FROM AUTHOR]

The impedance of an antenna changes heavily with changing EM environments, while RF power amplifiers (PAs) are optimized for driving a well-defined load impedance. As a solution, switchable matching networks are used in automatic antenna tuners to match the antenna impedance to (about) the desired PA load impedance. This paper presents a theoretical treaty of the minimum number of required states for switchable matching networks to achieve sufficient matching from a certain load VSWR to a sufficiently low input VSWR. First for an arbitrary passive lossless switchable matching network, the mathematical minimum required number of states as a function of the required input VSWR and of the required load VSWR is derived. Several variants are analyzed and benchmarked: single-stage one-ring configuration, single-stage two-ring configuration, two-stage one-ring configuration and three-stage one-ring configuration showing that single-ring configurations are optimum. An extension towards the required number of states for lossy matching networks is also provided. [ABSTRACT FROM AUTHOR]

This paper proposes a complete transmitter prototype for wireless applications using envelope tracked pulsed gate modulated power amplifier (PA). The proposed transmitter architecture is developed using two high power 10 W gate modulated PAs combined in a fashion to operate as a switched voltage source for the range of duty cycles of pulses driving the gates of power amplifiers. These PAs are designed and implemented using packaged GaN HEMT transistors from CREE to operate at the carrier frequency of 2.35 GHz. For a 5 MHz bandwidth WiMAX 802.16e down-link signal with the PAPR of 7.9 dB and the oversampling ratio of 100, the average drain efficiency of 46.2% is achieved at the average output power of 35.8 dBm. Using a 5 MHz bandwidth LTE down-link signal with 11 dB PAPR and centered at 2.35 GHz, the power amplifier delivers the average output power of 33.2 dBm with the average drain efficiency of 46%. The adjacent channel leakage ratio (ACLR) measured for this signal is less than -36.85 dBc at 10 MHz offset from the center frequency of 2.35 GHz. [ABSTRACT FROM AUTHOR]

This paper presents a 10-bit single-ended SAR ADC suitable for multi-channel neural recording. The proposed ADC introduces several power saving techniques to boost the energy efficiency. The ADC is built with on-chip common-mode buffer for input tracking, which is reused as the pre-amplifier of a current-mode comparator during conversion. A small capacitor is inserted between the amplifier and the capacitive DAC array in order to reduce the capacitive load on the amplifier. A split capacitor array with dual thermometer decoders is proposed to reduce the switching energy. Implemented in 0.13-\mum CMOS technology, the ADC achieved a maximum differential nonlinearity (DNL) of -0.33/+0.56 LSB, maximum integral nonlinearity (INL) of -0.61/+0.55 LSB, effective number-of-bits (ENOB) of 8.8, and a power consumption of 9-\muW. [ABSTRACT FROM AUTHOR]

This paper presents a 10-bit ultra-low voltage energy-efficient SAR ADC. The proposed merge-and-split (MS) switching effectively reduces DAC switching energy by 83% compared with conventional one without the need of extra reference voltage (Vcm) and the issue of common-mode voltage variation. To maintain good input linearity, a new double-bootstrapped sample-and-hold (S/H) circuit is proposed under an ultra-low voltage of 0.3 V. In addition, by employing asymmetric logic in SAR control, the leakage power is reduced with the penalty of slight conversion speed degradation. The test chip fabricated in 90 nm CMOS occupied a core area of 0.03 mm^2. With a single 0.3 V supply and a Nyquist rate input, the prototype consumes 35 nW at 90 kS/s and achieves an ENOB of 8.38 bit and a SFDR of 78.2 dB, respectively. The operation frequency is scalable up to 2 MS/s and power supply range from 0.3 V to 0.5 V. The resultant FOMs are 1.17-to-1.78 fJ/conv.-step. [ABSTRACT FROM AUTHOR]

N-path filters exploiting switched-series-R-C networks can realize high-Q blocking-tolerant band-pass filters. Moreover, their center frequency is flexibly programmable by a digital clock. Unfortunately, the time variant nature of these circuits also results in unwanted signal folding. This paper proves analytically that folding can be reduced and band pass filtering can be improved by adding an inductance in series with the switched-R-C network. In contrast, a shunt capacitor degrades band-pass filter performance. The interaction between the reactive series impedance and the switched capacitors of an N-path filter complicates analysis due to memory effects associated with reactive components. Assuming N identical signal paths with 1/N duty cycle, we show it is possible to solve the set of differential equations, by assuming that the signals in each path only differ in delay. Analytical equations are verified versus simulations, and the benefits in filter properties and reduction in signal folding are demonstrated. [ABSTRACT FROM AUTHOR]

This paper presents a 12-bit energy-efficient successive approximation register analog-to-digital converter (ADC). By incorporating the proposed capacitor-swapping technique, which eliminates the problematic MSB mismatch transition of a binary-weighted capacitor digital-to-analog converter, the 12-bit linearity of the ADC is achieved without increasing the capacitor size for improved matching. The small capacitor size results in low power consumption. In addition, an on-the-fly programmable dynamic comparator is used for quick comparisons with low noise contributions within the limited power budget. The ADC is fabricated using a 110-nm CMOS process. It consumes 16.47 \muW from a 0.9-V supply at a conversion-rate of 1 MS/s. The measured DNL and INL are within 0.3 LSB and 0.56 LSB, respectively. The measured SNDR and SFDR are at 67.3 dB and 87 dB, respectively. The ENOB performance is 10.92 b, which is equivalent to a figure-of-merit of 8.47 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

This paper introduces a discrete wheel-switching chaotic system (DWSCS). Changing the controlling sequence of the wheel switch allows DWSCS to generate a large number of new chaotic sequences from a set of existing chaotic maps (seed maps). Simulations and analysis demonstrate the DWSCS's characteristics and chaotic behaviors. An FPGA design of DWSCS shows its effectiveness in hardware implementation. We also propose a pseudo-random number generator using DWSCS whose excellent performance has been shown in experiments and comparisons. [ABSTRACT FROM AUTHOR]

This paper describes the first purely digital approach to reduce the receive band noise in digitally-intensive RF transmitters. The proposed solution applies bandpass delta-sigma modulation and dynamic element matching (DEM) to the receive band (RX-band) instead of the transmit band. This enables selective attenuation of the noise originating from amplitude quantization and static mismatches of the digital-to-analog converter (DAC), which would otherwise reach the transmitter output almost unattenuated. A highly configurable 4th-order noise transfer function is designed to achieve optimum attenuation in the programmable RX-band, while ensuring negligible degradation of the transmitted signal quality as well as stable operation of the tree structure DEM encoder. A general validation of DEM, independent from the duration of the DAC impulse response, is also presented. The proposed solution is verified through system-level simulations with LTE signals. In the presence of typical amplitude and timing mismatches, the RX-band noise can be reduced below -160 dBc/Hz without filtering after the DAC, thus potentially enabling SAW-less operation of all-digital transmitters. [ABSTRACT FROM PUBLISHER]

Multiple-supply are required to minimize the power consumptions in bio-implant systems. A single-inductor multiple-output (SIMO) switching converter is one of the solutions. But it has inherent problems which block the applications in the embedded biomedical systems. In this paper, a circuit arrangement for providing multiple outputs based on low-dropout (LDO) regulator is proposed. The regulating transistor of LDO is time-shared by N output legs. Two error amplifiers (EAs) are utilized in the topology, irrespective of number of the output legs. The corresponding switching strategy alleviates the difficulties associated with controlling multiple switching functions for conventional time-sharing methods, and thus, permits multiple outputs to be generated easily. A prototype multiple-output LDO (MOLDO) regulator with four output legs was fabricated with a standard 0.35 \mu\ m CMOS process. The measurement results verify the good performance of this design such as no cross regulation (CR), small ripples, and less power consumption. Moreover, it does not require inductor and presents low total harmonic distortion, which is very suitable for bio-implant fields. [ABSTRACT FROM PUBLISHER]

A 9 b Successive-Approximation-Register (SAR) Anglog-to-Digital Converter (ADC) with pilot-Digital-to-Analog Converter (pDAC) technique for image sensor applications is described in this paper}. Its Forward Error Correction (FEC) improves its robustness against device mismatch. It performs mixed-signal Correlated-Double-Sampling (CDS) using only the ADC's built-in capacitor array without any additional amplifier or memory. The ADC measures 490\mum\times 7.4\mum and is demonstrated in a low-power CMOS image sensors with column parallel ADCs. Measurement results from the prototype image sensor in 0.18\mum technology shows that the ADC's Differential Non-Linearity (DNL) is reduced from 3.5 LSB to 1.2 LSB by its mixed-signal FEC algorithm, making its Figure-of-Merit (FoM) 64 fJ/step. Furthermore, when combined with the ADC's mixed-signal Correlated-Double-Sampling, the column FPN is reduced from 3.2% to 0.5% without any additional circuit. [ABSTRACT FROM PUBLISHER]

This paper presents a time domain generalized semi-analytical solution for the class-E outphasing power amplifier (OPA). Instead of assuming ideal voltage sources for active devices, the proposed class-E OPA model obtains the circuit elements by analytically solving the class-E equations for two mutually loaded active devices and numerical optimization. The analysis takes into account the dc-feed inductor, duty-cycle, switch resistances and the class-E conditions at certain outphasing angle. Three different topologies are deduced from the proposed generalized model. The design equations for the circuit elements are derived analytically using the given class-E conditions. The overall outphasing performance is obtained numerically, and the optimum design settings are determined by the desired output power and efficiency characteristics. It will be shown that the proposed class-E OPAs can ideally maintain high efficiency (>80%) at 12-dB power back-off with a static square-wave drive signal. With 5-MHz UMTS downlink signal, the ideal average efficiency is more than 80%. The spectral and modulation requirements are satisfied when the predistortion is applied to the class-E OPA. [ABSTRACT FROM AUTHOR]

This paper presents a bit reversal circuit for continuous-flow parallel pipelined FFT processors. In addition to two flexible commutators, the circuit consists of two memory groups, where each group has P memory banks. For the consideration of achieving both low delay time and area complexity, a novel write/read scheduling mechanism is devised, so that FFT outputs can be stored in those memory banks in an optimized way. The proposed scheduling mechanism can write the current successively generated FFT output data samples to the locations without any delay right after they are successively released by the previous symbol. Therefore, total memory space of only N data samples is enough for continuous-flow FFT operations. Since read operation is not overlapped with write operation during the entire period, only single-port memory is required, which leads to great area reduction. The proposed bit-reversal circuit architecture can generate natural-order FFT output and support variable power-of-2 FFT lengths. [ABSTRACT FROM AUTHOR]

This paper presents a numerical locking-range prediction for the injection-locked class-E oscillator using the phase reduction theory (PRT). By applying this method to the injection-locked class-E oscillator designs, which is in the field of electrical engineering, the locking ranges of the oscillator on any injection-signal waveform can be efficiently obtained. The locking ranges obtained from the proposed method quantitatively agreed with those obtained from the simulations and circuit experiments, showing the validity and effectiveness of the locking-range derivation method based on PRT. [ABSTRACT FROM AUTHOR]

Power management of mobile digital systems-on-chip necessitates large voltage regulation performances. DC/DC converters used to supply digital cores are facing stringent constraints with respect to load transients, reference tracking and accuracy. The fast transient response offered by sliding-mode control is well suited to DC/DC converters with fast varying load. Fixed switching-frequency is also mandatory for EMI and noise related issues. Fixed-switching frequency sliding-mode control has been experimented as a multi-loop system. There is a necessity to investigate the stability when multi-loops interact and the parameter set for each loop is quite large. The paper details a methodology for the stability analysis of a frequency-controlled sliding-mode DC/DC converter. The proposed stability analysis takes the possible cross-interactions into account and can be used to optimise the DC/DC controller without the limitations of a non-interaction criterion. As a verification a DC/DC converter is implemented in CMOS 130 nm. Experimental results agree with the analysis main recommendations. [ABSTRACT FROM AUTHOR]

Accurate modeling of magnetic tunnel junction (MTJ) is critical for design of memories such as spin-transfer-torque magnetoresistive random access memory (STT-MRAM) and spin logic circuits such as spin flip flops. This paper reviews several static and dynamic models for the MTJ and compares them for their capabilities and limitations. Furthermore, a Verilog-A model is developed to predict dynamic characteristics of the MTJ. These models are used in simulating a prototype circuit to illustrate their strengths and weaknesses. [ABSTRACT FROM AUTHOR]

It has been studied that, an N-path switched-capacitor (SC) branch driven by an N-phase non-overlapped local oscillator (LO), is equivalent to a tunable parallel-RLC tank suitable for radio-frequency (RF) filtering. This paper proposes a gain-boosted N-path SC bandpass filter (GB-BPF) with a number of sought features. It is based on a transconductance amplifier (Gm) with an N-path SC branch as its feedback network, offering: 1) double RF filtering at the input and output of the Gm in one step; 2) customized passband gain and bandwidth with input-impedance match; and 3) reduced physical capacitance thanks to the loop gain offered by Gm. All have been examined using a RLC model of the SC branch before applying the linear periodically time-variant (LPTV) analysis to derive the R, L, and C expressions and analytically study the harmonic selectivity, harmonic folding, and noise. The latter reveals that: 1) the noise due to the switches is notched at the output, allowing smaller switches to save the LO power and 2) the noises due to the source resistance and Gm are narrowband at the output, reducing the folded noise during harmonic mixing. To study the influence of circuit non-idealities, an intuitive equivalent circuit model is also proposed and verified. The design example is a four-path 0.5–2-GHz GB-BPF simulated with the 65-nm CMOS. It exhibits >11 dB gain, <2.3 dB NF, and +21-dBm out-of-band IIP3 at 150-MHz offset, while consuming just 7 mW of power. [ABSTRACT FROM PUBLISHER]

Even though small metal fringe capacitors are important for the realization of a variety of circuits, including low-energy analog-to-digital converters and digitally controlled oscillators, the present literature is lacking experimental data on their mismatch characteristics. This paper describes a test structure and measurement results pertaining to the characterization of single-layer, lateral-field, 0.45-fF and 1.2-fF unit metal capacitors in a 32-nm SOI CMOS process. The measurement-inferred average standard deviations for these capacitances are 1.2% and 0.8%, respectively, confirming area scaling according to Pelgrom's matching formula. [ABSTRACT FROM AUTHOR]

A 14 bit 500 MS/s current-steering digital-to-analog converter (DAC) was designed and fabricated in 0.13 \mum CMOS process. For traditional wide-band current-steering DACs, the spurious-free dynamic range (SFDR) is limited by nonlinear distortions from the code-dependent load variations and the code-dependent switching glitches. They are analyzed in this paper and mitigated by the proposed complementary switched current sources (CSCS) and time-relaxed interleaving digital- random-return-to-zero (TRI-DRRZ), respectively. The proposed techniques are fabricated and measured, with an SFDR of 84.8 dB at 11 MHz signal frequency and 73.5 dB at 244 MHz. The DAC consumes 299 mW from a mixed power supply of 1.2 V and 2.5 V with an active area of 1.85\times 0.65\ mm^2. [ABSTRACT FROM AUTHOR]

This paper proposes a high-efficiency zero-voltage- switching (ZVS) AC-DC light-emitting-diode (LED) driver. The structure of the proposed converter is based on a buck-boost power-factor-correction (PFC) converter. Through replacement of an output diode with a self-driven synchronous rectifier (SR), the conduction loss decreases significantly, and there is no switching loss because of the ZVS operation of the switching devices. In addition, no additional control circuit is required and cost reduction is achieved because the SR is self-driven. The efficiency of the proposed converter is higher than that of the conventional critical-conduction-mode (CRM) buck-boost PFC converter, owing to the reduced conduction loss of the high-side output rectifier and no switching loss of either of the switches. For verifying the ZVS operation and efficiency improvement of the proposed AC-DC LED driver, theoretical analysis and experimental results of a 48-[V] and 1.4-[A] prototype for LED driver are discussed. [ABSTRACT FROM AUTHOR]

Memristive technology has experienced explosive growth in the last decade, with multiple device structures being developed for a wide range of applications. However, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain. In this work, we demonstrate the behaviour of our in-house fabricated custom memristor model and its integration into the Cadence Electronic Design Automation (EDA) tools for verification. Various input stimuli were given to record the memristive device characteristics both at the device level as well as the schematic level for verification of the memristor model. This design flow from device to industrial level EDA tools is the first step before the model can be used and integrated with Complementary Metal-Oxide Semiconductor (CMOS) in applications for hybrid memristor/CMOS system design. [ABSTRACT FROM AUTHOR]

This article shows a focus on the positivity and stability of Cohen-Grossberg-type time-delay memristor neural networks. We start by providing the existence and unique theorem of solutions for time-delay memristor neural networks to the case of unbounded delays. It is clear to find that the discriminate criterion of the existence and uniqueness of solutions about the argumented system with unbounded delays plays an important role in other related unbounded time-delay systems. Leveraging the Lyapunov method along with memristor nonlinearity, sufficient and necessary conditions for positivity and stability of Cohen-Grossberg-type memristor neural networks under unbounded delays are gained. Our proposed criteria don’t need any strictly restrictive conditions. These theoretical results derived here will be helpful to understand the convergence performance of memristor electrical systems. [ABSTRACT FROM AUTHOR]

The millimeter-wave (mm-wave) single-pole double-throw (SPDT) switch designed in bulk CMOS technology has limited power-handling capability in terms of 1-dB compression point (P1dB) inherently. This is mainly due to the low threshold voltage of the switching transistors used for shunt-connected configuration. To solve this issue, an innovative approach is presented in this work, which utilizes a unique passive ring structure. It allows a relatively strong RF signal passing through the TX branch, while the switching transistors are turned on. Thus, the fundamental limitation for P1dB due to reduced threshold voltage is overcome. To prove the presented approach is feasible in practice, a 90-GHz asymmetrical SPDT switch is designed in a standard 55-nm bulk CMOS technology. The design has achieved an insertion loss of 3.2 dB and 3.6 dB in TX and RX mode, respectively. Moreover, more than 20 dB isolation is obtained in both modes. Because of using the proposed passive ring structure, a remarkable P1dB is achieved. No gain compression is observed at all, while a 19.5 dBm input power is injected into the TX branch of the designed SPDT switch. The die area of this design is only 0.26 mm2. [ABSTRACT FROM AUTHOR]

In this paper we investigate the sine qua non condition of existence of equilibria for electrical systems with external (AC or DC) sources furnishing constant power to the loads, which is a scenario encountered in modern applications. Two general cases are considered, when the system is i) linear time-invariant or ii) nonlinear, with dynamic behavior described by a port-Hamiltonian model with constant dissipation and switching interconnection matrix. The latter class includes the practically important case of power converters. For both cases necessary and sufficient conditions for existence of equilibria are given, which give an upper bound on the power dissipated in steady-state that should exceed the extracted constant power. The existence of the equilibrium is ensured if and only if the inequality is satisfied. [ABSTRACT FROM AUTHOR]

The paper is concerned with the problem of input-to-state stability (ISS) for nonlinear delay systems with large delay periods (LDP). The concepts of the length rate of LDP and the frequency of LDP are introduced. First the considered system is converted into a switched delay system which may include an unstable subsystem. Then based on a piecewise Lyapunov functional, the ISS properties of the systems are developed under the constraints of the length rate and the frequency of LDP. ISS for a special kind of nonlinear delay systems is also considered and the conditions of nonlinear matrix inequalities (NLMIs) are proposed to guarantee the ISS properties of such a system. A numerical example and an example of a series DC motor are given to show the effectiveness of the proposed methods. [ABSTRACT FROM AUTHOR]

Advanced computing systems suffer from high static power due to the rapidly rising leakage currents in deep sub-micron MOS technologies. Fast access non-volatile memories (NVM) are under intense investigation to be integrated in Flip-Flops or computing memories to allow system power-off in standby state and save power. Spin Transfer Torque MRAM (STT-MRAM) is considered the most promising NVM to address this issue thanks to its high speed, low power, and infinite endurance. However, one of the disadvantages of STT-MRAM for the computing purpose is its relatively high write energy to build up Magnetic Flip-Flop (MFF). In this paper, we propose a power-efficient MFF design architecture to address this challenge based on the combination of checkpointing operation, power gating and self-enable mechanisms. Multi non-volatile storages can be integrated locally in a conventional FF without significant area overhead benefiting from the 3-D implementation of STT-MRAM. We performed electrical simulations (i.e. transient and statistical) to validate its functional behaviors and evaluate its performance by using an accurate spice model of STT-MRAM and an industrial 40 nm CMOS design kit. The simulation results confirm its lower power consumption compared to conventional CMOS FF and the other structures. [ABSTRACT FROM AUTHOR]

Dynamic average-value models (AVMs) for AC-DC rectifier circuits are generally formulated in state-space form and hence are straightforward to implement in state-variable-based simulation languages. In the nodal analysis-based approach used in electromagnetic transient (EMTP-type) simulation packages, the development of AVMs requires additional effort to reformulate and interface the models with the external ac and dc networks. This paper proposes a new averaged-circuit model for three-phase line-commutated rectifiers which is directly interfaced with the ac and dc networks, thereby achieving a simultaneous solution of the respective variables in EMTP-type solution. The proposed model is verified against conventionally interfaced model, as well as detailed switching model of the original rectifier circuit. A significant improvement of numerical accuracy and stability of the solution is demonstrated even at fairly large time steps. [ABSTRACT FROM AUTHOR]

The unprecedented interest in high bandwidth applications in the mm-wave range has set off a wave of research exploring techniques that enable wide tuning range voltage-controlled oscillators (VCOs). Low frequency CMOS LC-VCOs (< 10 GHz) have been well studied in the literature and several approaches have been developed to optimize their performance. However, there lie several interesting challenges in the mm-wave space, specifically close to the f_T/f\max, that motivate the need for analyzing the tuning range and phase noise in mm-wave VCOs. This paper presents a detailed analysis of the ultimate performance bound in simultaneously achieving low phase noise and wide tuning range in CMOS VCOs. The analysis is conducted on a 130 nm CMOS process, and confirmed by measurement results on three VCOs at 26 GHz, 34 GHz and 40 GHz. Finally, the impact of CMOS technology scaling (from 130 nm down to 45 nm), on the achievable performance bounds is analyzed and presented. [ABSTRACT FROM PUBLISHER]

A soft-switching bidirectional dc-dc converter using a lossless active snubber is proposed in this paper. In the proposed converter, zero-voltage-switching (ZVS) of main switches is achieved by utilizing an active snubber which consists of auxiliary switches, diodes, an inductor, and a capacitor. Although conduction losses associated with additional components increase, switching losses are significantly reduced due to the ZVS operation of main switches. Therefore, total efficiency is improved. Moreover, there is no reverse-recovery problem of the intrinsic body diodes of the switches. To verify the ZVS of the main switches and efficiency improvement of the proposed bidirectional dc-dc converter, theoretical analysis and experimental results from a 200 W prototype are discussed. [ABSTRACT FROM AUTHOR]

Clock gating is very useful for reducing the power consumed by digital systems. Three gating methods are known. The most popular is synthesis-based, deriving clock enabling signals based on the logic of the underlying system. It unfortunately leaves the majority of the clock pulses driving the flip-flops (FFs) redundant. A data-driven method stops most of those and yields higher power savings, but its implementation is complex and application dependent. A third method called auto-gated FFs (AGFF) is simple but yields relatively small power savings. This paper presents a novel method called Look-Ahead Clock Gating (LACG), which combines all the three. LACG computes the clock enabling signals of each FF one cycle ahead of time, based on the present cycle data of those FFs on which it depends. It avoids the tight timing constraints of AGFF and data-driven by allotting a full clock cycle for the computation of the enabling signals and their propagation. A closed-form model characterizing the power saving per FF is presented. It is based on data-to-clock toggling probabilities, capacitance parameters and FFs' fan-in. The model implies a breakeven curve, dividing the FFs space into two regions of positive and negative gating return on investment. While the majority of the FFs fall in the positive region and hence should be gated, those falling in the negative region should not. Experimentation on industry-scale data showed 22.6% reduction of the clock power, translated to 12.5% power reduction of the entire system. [ABSTRACT FROM AUTHOR]

This paper presents new design procedure for a general class-E power amplifier, here referred to as quasi-class-E, with finite dc-feed inductance and switch on-resistance and variable duty cycle under variable voltage switching (VVS), and variable derivative voltage switching (VDS), taking into account the switch breakdown voltage. It is shown that for non-zero switch on-resistance in class-E power amplifier, zero voltage switching (ZVS) and zero derivative switching (ZDS) conditions do not necessarily result in maximum efficiency. Hence, by assuming VVS and VDS, new design equations are derived. The new equations can be solved with a simple and fast numerical method in MATLAB. The theoretical results show efficiency improvement for quasi-class-E power amplifier compared to conventional designs. Circuit simulations confirm the validity of the theoretical results. [ABSTRACT FROM AUTHOR]