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In this paper, a novel constrained switching rule, called “time-triggered logical switching” (TTLS) is considered for switched logical dynamic systems (SLDSs). Compared with the general time-triggered switching, the activation mode of TTLS cannot be arbitrary and is pre-allocated according to the logic operation, which is more practical. The TTLS is described as an LDS, and according to the characteristics of LDS, the stability analysis of SLDSs with TTLS is converted into the stability analysis of SLDSs under the logical switching cycle sequences. Firstly, based on the equivalent algebraic form of SLDSs with TTLS, combining the Lyapunov theory of LDS with average dwell-time method, several sufficient conditions are put forward for ensuring the point stability of the considered SLDSs. Then, by defining the switching cycle invariant subset and constructing a new system, the set stability analysis of the original system is transformed into the point stability analysis of the new system, and further, the obtained results for the point stability analysis are applied to the set stability analysis. At last, the validity of obtained results is illustrated by simulation on gene and protein signaling activity patterns. [ABSTRACT FROM AUTHOR]

This paper considers weakly and strongly input-to-state stability (ISS) of a discrete-time time-varying delayed system with synchronous impulses and switches. By employing the uniformly asymptotically stable function and mode-dependent dwell time conditions, ISS criteria are derived using the Krasovskii and Razumikhin techniques. The time differences of the Krasovskii functionals or the Razumikhin functions can be mode-dependent and time-varying, which release constraints of some existing results. As subsequent results, we apply the derived ISS criteria to the multi-agent systems (MASs). Finally, two examples considering the quasi-consensus of MASs are given to verify the established results. [ABSTRACT FROM AUTHOR]

The stability criteria based on the Rollett parameter ($K$) plus one auxiliary condition is yet the most popular method used by designers to evaluate the stability of a two-port network although other criteria are available. In this paper, novel analytical proofs of the criteria utilizing $K$ and a new geometrical proof of the relationship between the stability of the ports of a circuit are proposed. They are obtained by making use of relationships between the reflection coefficients at the ports of the network and novel expressions that bind stability circles and unit mapping circles. The developed relations make the proposed proofs easier and more immediate than the traditional ones. Moreover, a new auxiliary condition having the same complexity and a greater geometrical insight with respect to the traditional ones is used. [ABSTRACT FROM AUTHOR]

Although the cyber-physical system stability is widely studied, scholars focus more on system stability with communication time delay. Therein, grid-connected inverters with the digital control system are regarded as one simplest and typical cyber-physical system. Meanwhile, the switching/sampling frequency of the inverter is always selected as low as possible from an efficiency viewpoint, resulting in unavoidable delay time. This delay time is apt to cause the system instability, which is more prone to severity under weak grid. To this end, this paper provides a minimum switching/sampling frequency for grid-connected inverters. Firstly, the system impedance model with equivalent delay time is constructed, which is based on padé approximate approach. This equivalent delay time consists of three parts, i.e., sampling delay time in cyber/physical level, calculation delay time in cyber level and pulsewidth modulation delay time in physical level, which reflects the cyber-physical interaction impact. Furthermore, the stability forbidden criterion is applied to make the switching/sampling frequency solving process become Hurwitz matrix identification problem through space mappings. Based on these space mappings, an adaptive step search approach is adopted to obtain the minimum switching/sampling frequency. Finally, the proposed approach can well evaluate the system stability under different frequencies through simulation and experiment. [ABSTRACT FROM AUTHOR]

As is known to all that the Lyapunov-Krasovskii functional (LKF) has played a vital role in studying the fixed-time (FXT) stability of the time-delayed Filippov discontinuous systems. When investigating the FXT stability of the time-delayed discontinuous systems, the interesting topic is to provide the more relaxed conditions imposed on the LKF and obtain the more accurate settling-time (ST). This paper aims to investigate the new FXT stability lemma with more relaxed conditions for the time-delayed Filippov discontinuous systems. By using some novel inequality techniques and analytical methods, the new FXT stability lemma is established and more accurate ST is estimated. The traditional discussion about $0 < V < 1$ and $V \geq 1$ is not required. For the purpose of validation, FXT stabilization of discontinuous inertial networks with mixed time delays is considered. By using differential inclusions theory and the new FXT stability lemma, the delay-dependent FXT stabilization criteria are derived. It is the first time to derive the delay-dependent FXT stabilization criteria for the discontinuous inertial networks. Finally, examples are given to show the effectiveness of the established results. [ABSTRACT FROM AUTHOR]

This paper presents a novel physically unclonable function (PUF) for security authentication. Instead of using the variation of transistors or PDK provided passive components as entropy source, the parasitic resistance created between metal and via layers is used as the static entropy source. A symmetric bridge configuration consisted with the parasitic resistance creates the necessary voltage difference for comparison. An accurate backend incremental analog-to-digital converter (IADC) is implemented to convert the voltage difference into a digitized value. The operation of the IADC allows to achieve a good native instability. Two different types of layout structures are implemented to create the necessary parasitic resistance and compared. Fabricated in a 65nm process, the prototype PUF achieves a native instability and bit error rate of less than 1.45% and 0.12% with 5000 repeated evaluations. The proposed design shows 0.58%/0.1V and 0.53%/10°C bit error across the voltage and temperature range of 0.9 to 1.4V and 0°C to 85°C, respectively without any stabilization techniques. The distance ratio between intra-die and inter-die Hamming Distance is above $305\times $. [ABSTRACT FROM AUTHOR]

In this paper a fairly complete mathematical model of CP-PLL, which reliable enough to serve as a tool for credible analysis of dynamical properties of these circuits, is studied. We refine relevant mathematical definitions of the hold-in and pull-in ranges related to the local and global stability. Stability analysis of the steady state for the charge-pump phase locked loop is non-trivial: straight-forward linearization of available CP-PLL models may lead to incorrect conclusions, because the system is not smooth near the steady state and may experience overload. In this work necessary details for local stability analysis are presented and the hold-in range is computed. An upper estimate of the pull-in range is obtained via the analysis of limit cycles. The study provided an answer to Gardner’s conjecture on the similarity of transient responses of CP-PLL and equivalent classical PLL and to conjectures on the infinite pull-in range of CP-PLL with proportionally-integrating filter. [ABSTRACT FROM AUTHOR]

This paper studies stability for a class of switched descriptor systems with state bumpless transfer performance and input bumpless transfer performance. Since the state jump is inevitable for switched descriptor systems when a switching occurs, to restrain the amplitude of the state jump induced by switchings, for the first time, the state bumpless transfer performance of switched descriptor systems is defined. Moreover, when switching occurs, to avoid the abrupt and large control input signals change damaging the system, we are the first to introduce the input bumpless transfer control scheme for switched descriptor systems. Furthermore, by using multiple Lyapunov functions, a sufficient condition is put forward to make sure the state bumpless transfer performance, input bumpless transfer performance and asymptotical stability for the closed-loop systems. Meanwhile, the switching rule and the state feedback controller are co-designed. In the end, a multiple inputs numerical example and an application on the DC motor model are used to exhibit the merit and validity of the presented control scheme. [ABSTRACT FROM AUTHOR]

A fast-transient, current-efficient low-dropout regulator (LDO) with super transconductance cell (STC) is proposed in this paper. By adopting advanced current amplifier (CA) and dynamic biasing (DB) techniques for the error amplifier (EA), the feedback loop bandwidth can be significantly extended without increasing much quiescent power, which reduces output voltage spikes and response time greatly. Moreover, dynamic reference control (DRC) with robust loop stability is embedded in the LDO to adaptively adjust voltage reference during transient so as to further enhance the slew rate of EA, realizing significant enhancement for the transient performances. This circuit has been implemented in a 0.35 μm CMOS process and occupies an active chip area of 456 × 278 μm2. Experimental results show that it is able to provide 100mA load current at 200mV dropout voltage, with current efficiency of 99.88%. The output voltage spike under maximum load current change in 20ns edge time is less than 11.2mV with a 0.054 μs response time. The power-supply rejection (PSR) at 100kHz is −75.6dB. [ABSTRACT FROM AUTHOR]

This paper presents two efficient algorithms to determine whether a bivariate polynomial, possibly with complex coefficients, does not vanish in the cross product of two closed right-half planes (is “2-C stable”). A 2-C stable polynomial in the denominator of a two-dimensional analog filter has been proved (not long ago) to imply bounded-input bounded-output (BIBO) stability. The two algorithms are entirely different but both rely on a recently proposed fraction-free (FF) Routh test for complex polynomials in this transaction. The first algorithm tests the 2-C stability of a bivariate polynomial of degree (n1,n2) in order n6 of elementary operations (when n1 = n2 = n). It is a “tabular type” two-dimensional stability test that can be regarded as a “Routh table” whose scalar entries were replaced by univariate polynomials. The second 2-C stability test is obtained from the first by its telepolation. It carries out the 2-C stability test by a finite collection of FF Routh tests and requires only order n4 elementary operations. Both algorithms possess an integer-preserving property that enhances them with additional merits including numerical error-free decision on 2-C stability. [ABSTRACT FROM AUTHOR]

Under process, voltage, and temperature variations, SRAM cell stability largely fluctuates from the nominal value. In the design step, SRAM cell optimization while ignoring the fluctuation induces the yield loss for the stability. Variation-aware optimization of an SRAM cell can prevent the yield loss problem by considering the mean and variance of SRAM cell stability when finding optimal design parameters. This paper proposes a novel SRAM optimization method that uses a deep neural network (DNN). Multiple DNNs from ensemble techniques represent the mean and variance of SRAM cell stability for the nominal design parameters. Subsequent sensitivity analysis of DNN extracts the ${K}$ design parameters that have the most dominant effects on the mean and variance of SRAM cell stability. Then multidimensional optimization is used to find the optimal values of these ${K}$ parameters to maximize the mean stability while minimizing its variance. The proposed method achieved an average of 2% error compared to MC simulation. The proposed optimization method takes only 561 s to provide the most optimal design parameter values of an SRAM cell. [ABSTRACT FROM AUTHOR]

Robust stability problem of discrete-time fractional-order systems (DTFOSs) with interval uncertainties is investigated in this paper. Firstly, a new theorem for matrix root-clustering in union-region is established. Based on this theorem, the stability regions of DTFOSs are described as the union-region of closed sub-regions, and sufficient conditions for stability of DTFOSs are presented. Then, new sufficient conditions for robust stability of DTFOSs with interval uncertainties are derived. All the results are obtained in terms of linear matrix inequalities (LMIs) which are more tractable than the existing ones. Finally, numerical examples are given to show that our results are valid and less conservative than the existing ones. [ABSTRACT FROM AUTHOR]

The issue of finite-time stabilization (FTS) for the memristor-based inertial neural networks (MINNs) with mixed time-varying delays (MTVDs) is researched by virtue of a new analytical method in this brief. First, an appropriate reliable control strategy is proposed for MINNs, which takes the influence of actuator failures into account. Second, by combining Lyapunov functional theory with new analysis techniques, novel theoretical results to guarantee the FTS for the concerned MINNs are acquired, and the desired reliable controller gains are obtained simultaneously. In additions, compared with the previous research works, the FTS results obtained in this paper are established directly from the MINNs themselves without using variable transformation method. In the end, two simulations are exploited to show the correctness and practicability of the acquired theoretical results. [ABSTRACT FROM AUTHOR]

Disturbances, uncertainties, noises and device faults commonly exist in microgrids and often undermine the system stability. To meet these challenges, robust control methods have been recently employed in microgrids systems. In this paper, an active fault-tolerant control scheme is proposed for DC islanded microgrids subjected to sensor fault and external disturbance. Firstly, a distributed ${H_\infty }$ observer is designed to estimate the uncorrupted voltage and current with high accuracy. Then, an observer based state feedback controller is proposed to ensure stability of voltage regulation for the system. A consensus based control layer in the secondary level is provided to realize current sharing. For the plug-and-play operation of DC microgrids, decentralized parameters design approaches for the observer and controller are both discussed. Finally, simulation studies and experiments are carried out on a DC microgrid system to evaluate the effectiveness of the proposed fault-tolerant control scheme. The simulation and experiment results show that compared with previous works, the proposed observer based control strategy can significantly improve the reliability and resilience of DC microgrid systems. [ABSTRACT FROM AUTHOR]

This paper investigates the regularity, non-impulsiveness, stability and admissibility of the singular fractional-order systems with the fractional-order $\alpha \in (0,1)$. Firstly, the structure, existence and uniqueness of the time domain solutions of singular fractional-order systems are analyzed based on the Kronecker equivalent standard form. The necessary and sufficient condition for the regularity of singular fractional-order systems is proposed on the basis of the above analysis. Secondly, the necessary and sufficient conditions of non-impulsiveness as well as stability are obtained based on the proposed time domain solutions of singular fractional-order systems, respectively. Thirdly, two novel sufficient and necessary conditions for the admissibility of singular fractional-order systems are derived including the non-strict linear matrix inequality form and the linear matrix inequality form with equality constraints. Finally, two numerical examples are given to show the effectiveness of the proposed results. [ABSTRACT FROM AUTHOR]

To effectively use the network resources, a suitable event-driven communication scheme is proposed for the networked switched systems in this paper. Under the EDCS, a finite-time filter is designed for switched systems, which does not synchronize with the switched systems. Different from the existing finite-time problems, finite-time boundedness (FTBs) and input–output finite-time stability (IO-FTSy) are simultaneously considered in this paper. Some sufficient conditions are established to check the properties of the FTBs and the IO-FTSy of the event-driven asynchronous filtering error system by constructing a reasonable Lyapunov–Krasovskii functional and using the average dwell time approach. All the matrix inequalities can be converted to linear matrix inequalities so as to design the event-driven asynchronous filter. The applicability of the proposed filtering scheme is demonstrated via a mass-spring system model. [ABSTRACT FROM AUTHOR]

This paper presents a 28-nm 32kb 6T static random access memory (SRAM) operating down to the sub-threshold regime. This design employs a dual-phase VDD (DPVDD) control technique in a row-based manner to reduce the minimum functional voltage (Vmin) below the threshold voltage of the transistor (Vth). With the proposed DPVDD technique, during the read operation, the ratio of the read current to the leakage current caused by the unselected bit-cells on the same bit-line is increased by a temporally boosted cell VDD, which increases the signal swing on the bit-line and minimizes the stability degradation caused by the leakage current. In addition, the proposed DPVDD can enhance the stability of the half-selected cells to mitigate the half-select disturbance. A 32-kb 6T SRAM test chip was implemented in 28-nm CMOS technology with a macro area of 0.028 mm2. Measurement results show that the SRAM with the proposed DPVDD achieves Vmin of 0.27 V and the minimum energy of 0.041 fJ/bit. [ABSTRACT FROM AUTHOR]

Rich non-linear phenomena, such as Neimark-Sacker bifurcation and chaos and so on, are proven to exist and cause instability in one-cycle controlled (OCC) buck-boost converters. This paper presents a composite function embedded method based one-cycle control (CFOCC) to resolve such problems. By modifying the conventional OCC through embedding a composite function, the non-linear stability performances of the system are considerably improved to avoid bifurcation phenomena and the stable region is enlarged. Further, various commonly used functions, such as the logarithmic function, the arc-tangent function, etc., can be used as the embedded composite functions. The effectiveness of the proposed control method is verified by simulation and experiment. [ABSTRACT FROM AUTHOR]

This paper applies new analytical techniques to evaluate the stability and mean-square error (MSE) convergence of a multi-loop LMS pseudo-random noise canceller which applies to a variety of known mixed-signal circuit calibration techniques. To the authors’ knowledge, it is the first published MSE analysis of any multi-loop LMS system, and, unlike most published MSE analyses of single-loop LMS systems, it does not make any simplifying assumptions. The analysis proves that the noise canceler can be made unconditionally stable by design, and provides guidance on how to choose design parameters to achieve a desired level of noise cancellation. [ABSTRACT FROM AUTHOR]

This paper investigates the problem of noise-to-state practical stability in mean (NSpS-M) (which is a natural generalization of noise-to-state stability in mean) and the problem of almost sure global asymptotic stability (GAS a.s.) for a class of random nonlinear time-varying impulsive switched systems. By using the notions of average impulsive switched interval and Poisson process, unified sufficient stability criteria on NSpS-M and GAS a.s. are derived. Two remarkable distinctions from the existing results lie in that: (1) stabilizing, inactive and destabilizing impulses are simultaneously considered; (2) the coefficient of the derivative of a Lyapunov function is allowed to be a time-varying function which can be both positive and negative and may even be unbounded. As an accompaniment, a less conservative unified criterion on NSpS-M for a special case is also presented by taking into account the stabilization role of the gain constant of the time-varying coefficient. Two examples are provided to illustrate the effectiveness of our derived criteria. [ABSTRACT FROM AUTHOR]

This paper presents a wakeup timer in 40-nm CMOS for Internet-of-Things (IoT) applications based on a bang-bang Digital-intensive Frequency-Locked Loop (DFLL). A self-biased $\Sigma \Delta $ Digitally Controlled Oscillator (DCO) is locked to an RC time constant via a feedback loop consisting of a single-bit chopped comparator and a digital loop filter, thus maximizing the use of digital circuits while keeping only the RC network and the comparator as the sole analog blocks. Analysis and behavior level simulations of the DFLL have been carried out to guide the optimization of the long-term stability and frequency accuracy of the timer. High frequency accuracy and a $10\times $ enhancement of long-term stability is achieved by the adoption of chopping to reduce the effect of comparator offset and 1/f noise and by the use of $\Sigma \Delta $ modulation to improve the DCO resolution. Such highly digitized architecture fully exploits the advantages of advanced CMOS processes, thus enabling operation down to 0.7 V and a small area (0.07 mm2). The proposed timer achieves the excellent energy efficiency (0.57 pJ/cycle at 417 kHz at 0.8-V supply) over prior art while keeping excellent on-par long-term stability (Allan deviation floor < 20 ppm) and temperature stability (33 ppm°Cat 0.8-V supply). [ABSTRACT FROM AUTHOR]

This paper presents a one-sided Schmitt-trigger-based 9T static random access memory cell with low energy consumption and high read stability, write ability, and hold stability yields in a bit-interleaving structure without write-back scheme. The proposed Schmitt-trigger-based 9T static random access memory cell obtains a high read stability yield by using a one-sided Schmitt-trigger inverter with a single bit-line structure. In addition, the write ability yield is improved by applying selective power gating and a Schmitt-trigger inverter write assist technique that controls the trip voltage of the Schmitt-trigger inverter. The proposed Schmitt-trigger-based 9T static random access memory cell has 0.79, 0.77, and 0.79 times the area, and consumes 0.31, 0.68, and 0.90 times the energy of Chang’s 10T, the Schmitt-trigger-based 10T, and MH’s 9T static random access memory cells, respectively, based on 22-nm FinFET technology. [ABSTRACT FROM AUTHOR]

This paper studies the impacts of stochastic load fluctuations, namely the fluctuation intensity and the load power variation speed, on power system dynamic voltage stability. Additionally, the trade-off relationship between the two parameters is revealed, which provides important insights regarding the potential of using energy storage to maintain voltage stability under high uncertainty. To this end, Stochastic Differential-Algebraic Equations (SDAEs) are used to model the stochastic load variation; bifurcation analysis is carried out to explain the influence of stochasticity. Numerical study and Monte Carlo simulations on the IEEE 14-bus system demonstrate that a larger fluctuation intensity or a slower load power variation speed may lead to a smaller voltage stability margin. To the best of authors’ knowledge, this work uncovers the impacts of the time evolution property of the driving parameters, i.e., the load power variation speed and its trade off effect with the fluctuation intensity on the size of the dynamic voltage stability margin. [ABSTRACT FROM AUTHOR]

This paper is concerned with the attack-resilient event-triggered controller design problem of a DC microgrid with multiple nonlinear constant power loads and intermittent denial-of-service (DoS) attacks. First, for a resource efficiency purpose, an event-triggering communication scheme is delicately devised in such a way to only invoke the data transmission over the communication line when the DoS attack is inactive. Second, via characterizing the DoS active and inactive time intervals, a new switching piecewise system model for the nonlinear DC microgrid system is presented. Third, a numerically efficient design criterion on the existence of the desired attack-resilient event-triggered controller is established. It is further shown that various performance indices including resource efficiency, attack resilience, robustness against disturbance, sampling performance of the DC microgrid system can be evaluated in a unified framework. Finally, an illustrative example is given to verify the effectiveness of the proposed control design method for the DC microgrid. [ABSTRACT FROM AUTHOR]

This paper presents a complex frequency domain approach to investigate the cluster tracking performance of linear heterogeneous multi-agent networks. Firstly, a designed graph matrix is given to eliminate the interaction influence between coupled subnetworks with different tracking signals. On this basis, the cluster tracking performance analysis problem is decomposed into two parts, i.e., stability analysis and steady-state performance analysis of multi-agent networks. Secondly, based on the network structure, a minimum separable subgraph set is proposed to transform the stability of the multi-agent network into the stability of the separable subnetworks. Further, a signal flow diagram is introduced to solve the stability of the separable subnetworks. Thirdly, in view of Final-value theorem, a necessary and sufficient condition is proposed for achieving the cluster tracking control for the closed-loop stable multi-agent network. This result provides a strong theoretical basis for the flexible design of controllers due to that it quantitatively reveals the inherent law of steady-state performance for multi-agent networks. Finally, an algorithm is established to calculate the steady-state error of a general directed multi-agent network. Some simulations are provided to demonstrate the effectiveness of the theoretical results. [ABSTRACT FROM AUTHOR]

In this paper we explore the effects of pole-zero compensation in the settling performance of operational transconductance amplifiers (OTAs). We carry out the analysis by exploiting a proficient technique that provides an in-depth comprehension of the time domain behavior from the contour plots of the Normalized Settling Time. Starting from the case of a single-pole amplifier, we show the conditions upon which the settling time is degraded by the slow time constant set by the pole-zero doublet. Then, we extend these results to two-pole amplifiers and provide a useful design equation. Design examples of a two-stage and a single-Miller three-stage OTAs confirm the validity of the proposed theoretical models. [ABSTRACT FROM AUTHOR]

This paper endeavors to investigate the output-feedback sliding mode control (SMC) issue of the networked singularly perturbed systems (SPSs) under fast sampling. In order to improve the reliability of network communication, a redundant channel transmission protocol is introduced in the SMC design. Based on the measurement outputs, a sliding function is constructed with the consideration of the transmission protocol. With the aid of some appropriate Lyapunov functions, the sufficient conditions are derived to ensure the mean-square exponentially ultimately boundedness of the sliding mode dynamics and the reachability of the specified sliding surface. Moreover, a convex optimization algorithm is formulated to solve the output-feedback SMC law by searching the available upper bound of the singularly perturbed parameter. Finally, an operational amplifier circuit is exploited to explore the influences from the redundant channel transmission protocol to the output-feedback SMC performance and the estimated $\varepsilon$ -bound. [ABSTRACT FROM AUTHOR]

This paper extends the definitions of effective resistance and effective conductance to characterize the overall relation (positive coupling or antagonism) between any two disjoint sets of nodes in a signed graph. It generalizes the traditional definitions that only apply to a pair of nodes. The monotonicity and convexity properties are preserved by the extended definitions. The extended definitions provide new insights into graph Laplacian definiteness and power network stability. It is proved that the Laplacian matrix of a signed graph is positive semi-definite with only one zero eigenvalue if and only if the effective conductances between some specific pairs of node sets are positive. Also, the number of Laplacian negative eigenvalues is upper bounded by the number of negative weighted edges. In addition, new conditions for the small-disturbance angle stability, hyperbolicity, and type of power system equilibria are established, which intuitively interpret angle instability as the electrical antagonism between certain two sets of nodes in the defined active power flow graph. Moreover, a novel optimal power flow (OPF) model with effective conductance constraints is formulated, which significantly enhances power system transient stability. By the properties of extended effective conductance, the proposed OPF model admits a convex relaxation representation that achieves global optimality. [ABSTRACT FROM AUTHOR]

Cartesian feedback (CF) linearization for radio amplifiers is appealingly simple, but it imposes a trade-off between signal bandwidth and feedback delay. In almost all of the CF literature, it is a first-order circuit. In this paper, we examine two second-order CF linearizers and show that they can provide deeper suppression of intermodulation distortion or greater signal bandwidth at a given loop delay. Twin-loop CF with damping factor 0.707, for example, can provide 20 dB lower intermodulation distortion and half the error vector magnitude (EVM), relative to first-order CF. For twin-loop CF and proportional-integrator CF, we provide the first analyses of their behavior, stability limits, and linearization performance. Comparison with simulations using nonlinear amplifier models shows both the value and the shortcomings of linear analysis. Our new spectral separation approach leads to insights about linearization and EVM. [ABSTRACT FROM AUTHOR]

It is well known that the frequency synchronization of complex power networks is a prerequisite for stable operation. This paper investigates the global frequency synchronization in power networks via coordinating novel controllers on both the generator-side and the load-side. The designed controllers compute the monitored information from the generator-side and load-side simultaneously, and transmit the processed signals to steer the generators and load buses for maintaining frequency stability. In particular, the generator (load)-side buses can communicate with the load (generator)-side buses, not limited to the same side. Furthermore, nonlinear switching control protocols are proposed to analyze the frequency stability for overcoming the deficiency that the conventional linearized methods can only guarantee the local stability in or near an equilibrium state. The global stability region is rigorously proven, in which the sufficient conditions are derived for achieving global frequency synchronization of power systems. Finally, a prevailing modified Western System Coordinating Council (WSCC) 9-bus system and the widely-used IEEE 39-bus system are selected to validate the effectiveness and feasibility of the theoretical results. [ABSTRACT FROM AUTHOR]

This paper presents a low power and low noise quadrature RC oscillator based on a frequency locked loop. Voltage swing control of each of the two sub-oscillators reduces the effect of 1/f noise on the accumulated jitter. In addition, the use of quadrature phases greatly relieves timing constraints of sampling operations and helps the reduction of power consumption. With a discrete-time modeling of the quadrature oscillator, noise analysis is also provided for quantitative estimation of the circuit-driven effects on the phase noise. The proposed oscillator is fabricated using 180-nm CMOS process in an active area of 0.058mm2. The measurement shows a period jitter of 0.047% and a standard deviation of 0.94% in untrimmed frequency (444.9kHz) in a wafer. The oscillator achieves a figure-of-merit of 155 dBc/Hz at 100 Hz offset frequency. [ABSTRACT FROM AUTHOR]

This paper studies stability of stochastic impulsive switched systems. Different from exponential Lyapunov function and average dwell-time in the previous works, general Lyapunov function and fixed dwell-time are implemented in this paper to analyze input-to-state stability and global stability of stochastic impulsive switched systems. Two cases are investigated, that is, the case that the continuous dynamics is stable and the case that the discrete dynamics is stable. To implement multiple Lyapunov functions, there are two subcases considered in this paper: the subcase that the estimates on the derivatives of the multiple Lyapunov functions are the same and the subcase that the growths of the multiple Lyapunov functions by the jumps are the same. For aforementioned different cases, sufficient stability conditions are established for stochastic impulsive switched systems. Finally, the developed theory is illustrated through examples from networked control systems and synchronization problem of 3-D novel chaotic circuit systems. [ABSTRACT FROM PUBLISHER]

In this paper, relationships between conditional stability at the input and at the output of a linear non-unilateral 2-port are analyzed for the first time. For this purpose, the existence of a duality mapping between the two ports is shown and, by using the main properties of Möbius transforms, new mutual relationships between conditional stability configurations at input and output ports are demonstrated. Such new relationships add to the case of unconditional stability for which it is well known that unconditional stability at the input implies unconditional stability at the output (and vice versa). To this end, all the possible cases of reciprocal position between the stability area and the Smith circle have been analyzed showing that, for a given situation at the input, only one corresponding situation can be observed at the output (and vice versa). Limit cases are further considered. [ABSTRACT FROM AUTHOR]

This paper addresses the problem of establishing whether a matrix with rational dependence on a complex parameter and its conjugate is Hurwitz (i.e., has all eigenvalues with negative real part) over the complex unit circumference. A necessary and sufficient condition is proposed, which requires testing stability of a constant matrix and feasibility of a linear matrix inequality (LMI). Moreover, the numerical complexity of the proposed approach is investigated in terms of size and number of free scalar variables of the LMI by deriving their formulas as functions of the problem data. Also, it is shown that the numerical complexity may be significantly reduced without introducing approximations or conservatism whenever some symmetry properties are satisfied. Lastly, the extension of the proposed approach to the case of Schur stability (i.e., eigenvalues with magnitude smaller than one) and D-stability (i.e., eigenvalues on special regions of the complex plane) are presented. The proposed approach is illustrated by some numerical examples that also show its application to stability analysis of 2D systems with mixed signals. [ABSTRACT FROM AUTHOR]

This paper presents a programmable single-chip sustaining amplifier for MEMS-referenced oscillators. The chip integrates a low-noise amplifier, variable-gain amplifiers (VGAs), band-pass filters (BPFs), all-pass filters (APFs), automatic level control, and output buffers. It also contains a second signal path for background cancellation, i.e., eliminating the effect of electrical feedthrough capacitance of the MEMS resonator. Important parameters of each circuit block (e.g., VGA gain, BPF center frequency and quality factor ($Q$), APF phase shift, and so on.) can be set using bias currents, thus enabling fine-grained control over the overall transfer function. The amplifier was designed and fabricated in $0.5~\mu \text{m}$ CMOS. The chip was integrated with board-level current DACs (programmable via an I2C bus) and tested inside a vacuum chamber with various polysilicon (poly-Si) and single crystal (SC-Si) silicon comb-drive MEMS devices with resonant frequencies in the 10–90 kHz range. Oscillators referenced to a high- $Q$ (~13 000) SC-Si device had 20 dBc/Hz lower close-in phase noise (at 10 Hz) than those referenced to the low- $Q$ (~320) poly-Si device. Experimental results highlight advantages of the design, including automatic mode selection, background cancellation, control of feedback phase to optimize phase noise, and frequency locking to an external reference. [ABSTRACT FROM AUTHOR]

In this paper, the event-triggered robust filtering problem is investigated for a class of network-based state-dependent uncertain systems in the sense of finite-time boundedness, considering network transmission delay. By resorting to a generalized performance index, the $H_\infty $ and $L_{2}-L_\infty $ filtering problems can be solved in a unified framework. An event-triggered scheme is also utilized to sift out the sampled signals so that both the communication resources and the network bandwidth can be saved as much as possible. By means of an appropriate Lyapunov–Krasovskii functional and the delay system approach, sufficient conditions guaranteeing the filtering error system being finite-time bounded with extended dissipativity are deduced. Based on the convex optimization, an explicit expression of the desired finite-time robust filter is derived. Finally, two numerical examples are provided to illustrate the effectiveness of the developed methods. [ABSTRACT FROM AUTHOR]

The conventional six-transistor static random access memory (SRAM) cell allows high density and fast differential sensing but suffers from half-select and read-disturb issues. Although the conventional eight-transistor SRAM cell solves the read-disturb issue, it still suffers from low array efficiency due to deterioration of read bit-line (RBL) swing and $\text{I}_{\mathbf {on}}/\text{I}_{\mathbf {off}}$ ratio with increase in the number of cells per column. Previous approaches to solve these issues have been afflicted by low performance, data-dependent leakage, large area, and high energy per access. Therefore, in this paper, we present three iterations of SRAM bit cells with nMOS-only based read ports aimed to greatly reduce data-dependent read port leakage to enable 1k cells/RBL, improve read performance, and reduce area and power over conventional and 10T cell-based works. We compare the proposed work with other works by recording metrics from the simulation of a 128-kb SRAM constructed with divided-wordline-decoding architecture and a 32-bit word size. Apart from large improvements observed over conventional cells, up to 100-mV improvement in read-access performance, up to 19.8% saving in energy per access, and up to 19.5% saving in the area are also observed over other 10T cells, thereby enlarging the design and application gamut for memory designers in low-power sensors and battery-enabled devices. [ABSTRACT FROM AUTHOR]

Although the multiband-structured subband adaptive filter (MSAF) and its convergence analysis have been widely studied, the existing analyses are carried out only in the decimated time domain. In this paper, we present a new theoretical mean-square analysis of the multi-sampled MSAF (MS-MSAF) algorithm in the original time domain, whereas the MS-MSAF algorithm extends the original sub-sampled number to a general value. Both the transient and steady-state performances are investigated, which provides a guideline for increasing the convergence rate of the MSAF. Then, the tracking ability is studied in a non-stationary environment. Moreover, the approximative analytical minimum mean-square deviation and optimum step size are derived. Simulation results illustrate the derived performance expressions, which show that there is a relatively good match between theory and practice. [ABSTRACT FROM AUTHOR]

A performance-boosting frequency-compensation technique, called feed-forward Gm-stage and regular Miller plus indirect compensation (FGRMIC), is presented in this paper. The proposed structure consists of three parts that ensure the stability and significantly improve the performance, such as gain–bandwidth product (GBW), slew rate, and sensitivity. The first part is a feed-forward transconductance stage, and the second part is a Miller capacitor in series with one resistor. The third part is an indirect compensation capacitor combined with a resistor. Detailed theoretical analysis and design considerations are provided to demonstrate the stability of the compensation scheme. Measurement results show that the implemented amplifier, driving a 2-pF load capacitance, achieves a GBW of 2.41 GHz with a phase margin of 82.6° while consuming 12.6 mW with a 1.2-V supply voltage in a TSMC 65-nm CMOS technology. Large-signal step response indicates that the implemented three-stage FGRMIC amplifier settles with 1% settling error within 1.41 ns. [ABSTRACT FROM AUTHOR]

Despite their inherent stability, area-efficient loop filters, and insensitivity to phase-frequency detector nonlinearity and dead-zone, type-I phase-locked loops (PLLs) are used infrequently because of two major limitations—limited lock-range and large reference spurs. This paper introduces a type-I PLL that takes advantage of the inherent benefits of the architecture, while tackling its limitations by means of gain boosting in the forward path for lock-range improvement and synchronous peak tracking of the voltage-controlled oscillator control voltage for reference spur reduction. Sampling in the loop filter changes the loop dynamics, and methods to accurately predict the closed-loop response, starting from state-space equations, are provided. A digital-friendly, voltage-mode topology is proposed that does not need charge pumps or opamps. A prototype 2.2–2.8-GHz PLL occupies a core area of 0.12 mm2 in 0.13- $\mu \text{m}$ CMOS and achieves −103.4 dBc/Hz in-band phase noise, −65-dBc reference spur, and 2.5- $\mu \text{s}$ worst-case lock-time while consuming 6.8 mW from a 1.2-V supply. [ABSTRACT FROM AUTHOR]

This paper presents two output-capacitor-free low-dropout regulators (LDOs) with nA quiescent current for Internet-of-Things (IoT) applications. The proposed LDO1 combines the dynamic current biasing and the adaptive current biasing techniques for drastically reducing the quiescent current to the nA level while achieving fast transient response. Based on LDO1, the proposed LDO2 adds an inverter-based dynamic loop to further improve the transient response. The prototypes are fabricated in a 65-nm low-leakage CMOS process, with active areas of 0.0042 and 0.0048 m2, respectively. Measurement results show that LDO1 and LDO2 consume 30 and 100 nA quiescent current, respectively, with 1 V input, 0.8 V output, and 100 nA load current. Stability analysis shows that both LDOs achieve good stability with load current ranging from 100 nA to 10 mA. With the load current steps from 100 nA to 10 mA in 1- $\mu \text{s}$ transition time, the measured voltage undershoots are 336.8 mV for LDO1 and 196 mV for LDO2. Therefore, we reach a figure-of-merit of 0.00159 ps. [ABSTRACT FROM AUTHOR]

Due to the emerging systems with constraints in terms of power and costs, such as smart sensor interfaces for the Internet-of-Things, the design of the ADCs becomes very challenging. In this paper, energy and area efficient techniques for continuous-time (CT) delta-sigma modulators ($\Delta \Sigma $ Ms) are discussed. These techniques are based on increasing the contribution of the 1-bit comparator to the loop gain by using passive RC integrators together with low gain amplifiers in the $\Delta \Sigma \text{M}$ loop filter. A third-order CT $\Delta \Sigma \text{M}$ is designed using these techniques to demonstrate their validity, and it achieves 27.5 fJ/conv.-step of energy efficiency. Due to the many design issues, such as the tradeoff between RC variations and loop stability, the design of this modulator has been optimized using a genetic algorithm. The 65-nm CMOS $\Delta \Sigma \text{M}$ occupies only $0.013~\mathrm {mm^{2}}$ , dissipates 256 $\mu \text{W}$ from a 0.7-V supply and it achieves a peak SNDR of 69.1 dB in a 2-MHz bandwidth. The dynamic range reaches 76.2 dB, which corresponds to a $\mathrm {FoM_{Schreier}}$ of 175.1 dB. [ABSTRACT FROM AUTHOR]

This paper presents an application of a fractional-order control in an on-chip follower-type 1.8 V/100 mA voltage regulator to achieve a good stability with any load capacitance. The controller approximates an integrator with the fractional order of 0.5, whose phase lag is not more than 45°. The fractional order is set by the fractional-order impedance of the resistive p-type MOS capacitor (R-PMOScap). With an n-type MOS source follower stage adding the phase lag of at most 90°, the remaining phase margin is always at least 45°. The R-PMOScap is a novel integrated distributed-element RC network, realized as a resistive polysilicon strip on a gate oxide, and is compatible with an analog CMOS process. The voltage regulator has been manufactured in a 350-nm CMOS process and occupies a small chip area of 0.038 mm2. It operates in a harsh automotive environment with a temperature from −50 °C to 200 °C and shows a tight DC regulation, while being stable over the full range of the load current (from 0 to 100 mA) and with any load capacitance (allowing to use none or any external capacitor). [ABSTRACT FROM AUTHOR]

This paper focuses on the small-signal stability analysis of systems modelled as differential-algebraic equations and with inclusions of delays in both differential equations and algebraic constraints. The paper considers the general case for which the characteristic equation of the system is a series of infinite terms corresponding to an infinite number of delays. The expression of such a series and the conditions for its convergence are first derived analytically. Then, the effect on small-signal stability analysis is evaluated numerically through a Chebyshev discretization of the characteristic equations. Numerical appraisals focus on hybrid control systems recast into delay algebraic-differential equations as well as a benchmark dynamic power system model with inclusion of long transmission lines. [ABSTRACT FROM AUTHOR]

This paper mainly studies the stability and Hopf bifurcation criteria of hub-based genetic regulatory networks with multiple delays and bidirectional couplings. The hub-structured network is an important motif in complex networks, which provides a new view angle on structure to describe the regulation mechanism between genes (including both mRNAs and proteins). It is well known that hubs play a leading role in characterizing the network dynamical behaviors. However, the dynamics of hubs or star-coupled systems is not well understood. In this paper, we first examine the existence of the positive equilibria in this type of genetic networks. By analyzing the associated characteristic equation, we present sufficient conditions of biochemical parameters for delay-independent local stability in hub-coupled genetic regulatory networks. Then we investigate their Hopf bifurcation when such networks lose their stability. Specific conditions for delay-dependent stability and Hopf bifurcations in genetic networks with hub structure are derived. It is found that the dynamics of hub-structured genetic regulatory networks has no direct relationship with single time delay or individual connection, but instead depends on the sum of all delays among all genes and the product of the connection strengths between all genes. Finally, some simulation examples are provided to substantiate our analysis. [ABSTRACT FROM PUBLISHER]

The problem of existence and stability of equilibria of linear systems with constant power loads is addressed in this paper. First, we correct an unfortunate mistake in our recent paper refid="ref10"/ pertaining to the sufficiency of the condition for existence of equilibria in multiport systems given there. Second, we give two necessary conditions for existence of equilibria. The first one is a simple linear matrix inequality hence it can be easily verified with existing software. Third, we prove that the latter condition is also sufficient if a set defined by the problem data is convex, which is the case for single and two-port systems. Finally, sufficient conditions for stability and instability for a given equilibrium point are given. The results are illustrated with two benchmark examples. [ABSTRACT FROM PUBLISHER]

In this paper, a combined analytical-numerical methodology is developed for detecting subharmonic oscillation in H-bridge inverters with an LC filter and under double edge modulation. The prediction of this phenomenon is accomplished accurately by combining analytical expressions and computational procedures to determine the switching instants and the corresponding periodic orbits. Different approximate closed-form expressions for the stability boundary are derived revealing the effect of the parameters of the system on its dynamical behavior and showing that the stability boundary is different from the ones corresponding to single edge modulation strategies such as trailing edge and leading edge modulations. The theoretical results are validated by numerical simulations using a system-level switched model. Also, a prototype is implemented to validate he theoretical derivations and the numerical simulations getting a good matching. [ABSTRACT FROM AUTHOR]

In this paper, a pre-charged local bit-line sharing (PCLBS) static random access memory (SRAM) for near-threshold operation is proposed. In previous local bit-line sharing SRAMs, such as average-8T and full-swing local bit-line (FSLB) SRAMs, multiple bit-cells share a local bit-line pair with a small capacitance for high read stability. However, the average-8T SRAM has a considerably large delay because the full development of the local bit-line cannot be achieved. On the other hand, the FSLB SRAM reduces the delay but requires a timing constraint of control signals to achieve sufficient read sensing margin. The proposed PCLBS SRAM achieves high read speed by fully developing local bit-line pair without a timing constraint. Furthermore, the proposed PCLBS SRAM enhances the read stability and the write ability by, respectively, applying a pre-charged local bit-line scheme and transmission gates in write paths. Based on a 22-nm FinFET technology, the FSLB and proposed PCLBS SRAM have the minimum operating voltages of 0.44 and 0.4 V, respectively, while achieving the $5\sigma$ target read stability and write ability yields. Compared with the FSLB SRAM, the proposed PCLBS SRAM consumes 21% less energy at each minimum operating voltage and has 57% smaller read delay at the operating voltage of 0.4 V. [ABSTRACT FROM PUBLISHER]

In energy-constrained applications, SRAM systems operating in the subthreshold region are often deployed to reduce power consumption. Subthreshold SRAM designs, however, confront numerous challenges, such as susceptibility to process variation and reduced ON–OFF current ratio. Statistical modeling of the variation in cell stability is critical in SRAM design, especially, for designs operating in the subthreshold region, where the process and temperature variations are the most pronounced. In this paper, statistical models for estimating the static noise margins (SNMs) of SRAM cells are built from the perspective of a shifted voltage transfer characteristic. Read (hold) SNM of a subthreshold 8T cell is analyzed. It is shown that the distribution of a single-sided read SNM is a weighted sum of several normal distributions instead of a regular Gaussian distribution. The proposed statistical model is verified with simulation results in 65-nm technology. Furthermore, to mitigate performance and yield degradation, an adaptive body biasing circuit is developed. It is demonstrated through simulation that, with a negligible area and power overhead, the proposed circuit achieves a 15% improvement in the worst case read SNM. [ABSTRACT FROM PUBLISHER]

This paper addresses the stability issue of dc distributed power systems (DPS). Impedance-based methods are effective for stability assessment of voltage-source systems and current-source systems. However, these methods may not be suitable for applications involving variation of practical parameters, loading conditions, system's structures, and operating modes. Thus, for systems that do not resemble simple voltage-source systems or current-source systems, stability assessment is much less readily performed. This paper proposes an impedance-based criterion for stability assessment of dc DPS. We first classify any converter in a dc DPS as either a bus voltage controlled converter (BVCC) or a bus current controlled converter (BCCC). As a result, a dc DPS can be represented in a general form regardless of its structure and operating mode. Then, the minor loop gain of the standard dc DPS is derived precisely using a two-port small signal model. Application of the Nyquist criterion on the derived minor loop gain gives the stability requirement for the dc DPS. This proposed criterion is applicable to dc DPSs, regardless of the control method and the connection configuration. Finally, a 480 W photovoltaic (PV) system with battery energy storage and a 200 W dc DPS, in which the source converter employs a droop control, are fabricated to validate the effectiveness of the proposed criterion. [ABSTRACT FROM AUTHOR]