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This paper presents an on-chip digitally programmable thermal coupling emulation framework, referred to as the field-programmable thermal emulator (FPTE), for online characterization of power pattern, time-varying thermal field, and associated changes in the electrical characteristics of the transistors. A test chip was designed in 130-nm CMOS to validate the test structure. The measurement results demonstrated the ability of FPTE to emulate various power patterns and capture the effects on temperature and circuit performance. The test chip is used to explore and identify thermal coupling. The potential application of FPTE moves beyond thermal package tests and is capable of being used as chip-level thermal condition prediction and management infrastructure. [ABSTRACT FROM PUBLISHER]

With continued technology scaling and increased power and thermal densities, processor operation and performance are increasingly dominated by physical phenomena. Microarchitectural approaches to mitigate these effects must be based on a profound understanding of how the physics is manifested in microarchitectural executions and system-level properties, such as performance, energy efficiency, or lifetime reliability. This requires a modeling and simulation environment that incorporates multiple physical phenomena and their concurrent interactions with microarchitecture. In this paper, we introduce an integrated power, thermal, and reliability modeling framework, KitFox. The goal of KitFox framework is to facilitate research explorations at the intersection of applications, microarchitectures, and various physical phenomena, including energy, power, thermal, cooling, and reliability. The KitFox framework implements a standard interface to bridge multiple physical models, where individual models are encapsulated into libraries and are interchangeable. This paper describes the design methodology of the library framework that orchestrates various implementations of physical models and standardized interface to cycle-level microarchitecture simulators. Several use cases are presented to demonstrate the range of modeling capabilities of KitFox. [ABSTRACT FROM PUBLISHER]

In this paper, we present analytical models for fast estimation of coupling capacitance of square-shaped through-silicon vias (TSVs) in three-dimensional integrated circuits (3D ICs). Errors between our model and Synopsys Raphael simulation on regular TSV structures remain less than 6.03% while the computation time of our model for capacitance estimation is negligible. We also develop a simple capacitance estimation technique to extract TSV-to-TSV coupling capacitance in general layouts. Average errors between our model and Raphael simulation on random TSV structures is 5.06%–8.24%, and maximum errors remain less than 18.91% which is tolerable for fast capacitance estimation in computer-aided design area. [ABSTRACT FROM PUBLISHER]

This paper investigates the design of logarithmic CMOS image sensor with 3-D integrated image compression unit. The image sensor consists of a pixel array, column circuits, an array of analog-to-digital converters, a frame memory (image buffer) array, and a signal processing unit for image compression. This paper analyzes the correlation between the power dissipation in the image compression unit and the spatial noise characteristics of the photodiode array in the 3-D image sensor. The coupled power, performance, thermal, and noise analysis is performed considering 180-nm CMOS technology. The coupled analysis shows that, due to die-to-die thermal coupling, 3-D stacking of the image compression unit, although provides for better energy efficiency, results in a strong interaction between image quality, desired image throughput, and environmental factors, such as lighting conditions or available channel bandwidth. [ABSTRACT FROM AUTHOR]

In this article, we present an effective methodology for co-design, co-analysis, and the system-level optimization of chiplet/interposer power delivery network (PDN) in 2.5-D integrated chip (IC) designs. In our methodology, we first generate a commercial-grade heterogeneous 2.5-D IC designs including full signal routing and power delivery. We then perform our PDN co-analysis in frequency and time domains on the entire PDN to evaluate various mechanisms added to our PDN designs. Based on our co-analysis results, we perform the system-level optimization on both interposer and chiplet PDNs with the stable performance of power delivery. Finally, we perform power, performance, and area (PPA) analysis and power integrity (PI) on our 2.5-D designs and discuss tradeoffs in chiplet and interposer levels due to PDN optimization. Our experiments show 27.17% improvement in the overall IR-drop in the optimized 2.5-D IC design by increasing the interposer PDN occupancy by 5.52% and inserting the additional PDN grids in chiplet designs. However, we also observe tradeoffs in terms of PPA and PI. By PDN optimization, the optimized design has an 11.6% increase of the total power, while the area of 2.5-D design remains the same. Moreover, from the perspective of PI, the tradeoffs are shown by 0.6% reduction of power efficiency, 32.6% higher output ripple, and 31.5% higher initial ringing because of an inductive behavior of interposer PDN in the optimized design. [ABSTRACT FROM AUTHOR]

The efficient usage of thermoelectric (TE) devices for microelectronics cooling application requires investigation and remedy of various obstacles such as integration of these devices with electronic package, parasitic contact resistances, and utilization of appropriate current pulses. We develop a computational model to investigate the effect of steady state and transient mode of operation of ultrathin thermoelectric cooler (TEC) devices on hot-spot cooling considering the effect of crucial thermal and electrical contact resistances. Our analysis shows that the transient pulses can be very effective in reducing the hot-spot temperature by 6–7^\circC in addition to the cooling achieved by the steady state current through the TEC device. We correlate the important characteristics of the transient temperature behavior of hot-spot under the TEC operation such as the maximum temperature drop (\Delta T\max), time taken to achieve \Delta T\max and temperature overshoot after turning off pulse current with the electrical and thermal contact resistances and Seebeck coefficient of the TE material. It has been observed that thermal and electrical contact resistances play a very crucial role in the performance of TEC devices as high values of these resistances can significantly diminish the effect of Peltier cooling during steady state operation. The effect of these parasitic resistances is even higher for the transient cooling of hot-spots by the pulsed current through the TEC device. High Seebeck coefficient of TE materials is desirable as it increases the figure of merit of TE devices. However, cooling capabilities of heat sink may become bottleneck to realize the benefits of very high Seebeck coefficient as the back heat flow from the hot side to cold side of TEC device diminishes the degree of cooling achieved by these ultrathin TECs. [ABSTRACT FROM PUBLISHER]

System-in-package (SiP) integration of multiple dies in a single package can achieve much higher performance than onboard integration of integrated circuits (ICs) while reducing the design cost/effort compared to a large system on chips (SoCs). However, a major challenge in the design of SiPs with many dies is automated design and insertion of input/output (I/O) cells to minimize energy and delay of the wire traces. This article presents an automated cell library generation flow for all-digital I/O circuits for SiP integration. Given parameterized models of SiP wire traces, our method automatically designs, optimizes, and generates layouts of I/O cells for delay/energy minimization. The proposed flow is demonstrated on interposer-based SiP integration considering 28-nm CMOS technology and 65-nm BEOL technology. Given a multidie SiP design and associated interposer wire traces, this article demonstrates that automated I/O library cell generation can reduce the maximum die-to-die communication delay or energy. We demonstrate the proposed flow for various interposer parameters and SiP designs to show the feasibility of chip-interposer codesign. [ABSTRACT FROM AUTHOR]

This paper presents design, experimental characterization, and feasibility analysis of integrated in-package fluidic cooling for mobile systems-on-chips (SoCs). A pin fin interposer for fluidic cooling is designed and integrated with a commercial SoC. The demonstrated system integrates an active low-power piezoelectric pump controlled by the SoC itself and a metal/acrylic-based board-scale heat spreader and exchanger. Different software-based policies in the SoC for controlling the fluid flow based on SoC’s temperature and performance are implemented and compared. The measurement results demonstrate that the in-package fluidic cooling improves the SoC’s energy efficiency and reduces design footprint compared to external passive cooling. [ABSTRACT FROM AUTHOR]

This paper experimentally demonstrates a methodology for proactive estimation of spatiotemporal variations in junction temperature of a silicon chip using multi-input multi-output (MIMO) thermal filters. The presented approach performs on-chip measurements to estimate the relations between power and temperature variations in the frequency domain to construct a MIMO thermal filter. The extracted filter is then used to predict spatiotemporal temperature variations from a known power pattern, even for locations without temperature sensors. The accuracy of the proposed approach is verified through a thermal emulator designed in 130-nm CMOS technology with on-chip digitally controllable power (heat) generators and temperature sensors. Using the proposed MIMO thermal filter, spatiotemporal temperature variations are accurately estimated with small error bound even at locations with no temperature sensors. [ABSTRACT FROM PUBLISHER]

Thermal system identification (TSI) is presented as a methodology to characterize and estimate the transient thermal field of a packaged IC for various workloads considering chip-to-chip variations in electrical and thermal properties. The time–frequency duality is used to identify the thermal system as a low-pass filter in frequency domain through on-line power/thermal measurements on a packaged IC. The identified characteristic system for an individual IC is used for on-line prediction of the transient thermal field of that specific IC for a power pattern. A test-chip, fabricated in 130-nm CMOS, demonstrates the effectiveness of TSI in post-silicon characterization and prediction of transient thermal field. The application TSI in thermal analysis of multicore processors is presented. [ABSTRACT FROM PUBLISHER]

In this paper, we analyze the variability in a 3-D clock network designed with single and multiple through-silicon vias and present a post-silicon tuning methodology, called tier adaptive body biasing (TABB), to reduce skew and data path variability in 3-D clock trees. TABB uses specialized on-die sensors to independently detect the process corners of n-channel metal–oxide–semiconductor (nMOS) and p-channel metal–oxide–semiconductor (pMOS) devices and accordingly tune the body biases of nMOS/pMOS devices to reduce the clock skew variability. We also present the system architecture of TABB and circuit techniques for the on-die sensors. Circuit-level simulation and statistical analysis of the TABB architecture in a predictive 45-nm technology demonstrate the effectiveness of TABB in reducing the clock skew variability considering the data path variability in 3-D ICs. [ABSTRACT FROM AUTHOR]

This paper analyzes the effect of tier-to-tier thermal and supply crosstalk on the performance and robustness of the static random access memory (SRAM) within a 3-D stack under crosstalk influence of the logic cores. Our framework integrates distributed process variation aware circuit analysis, RC-based thermal simulation, and distributed RLC-based power delivery network simulation. The analysis shows when the logic cores and SRAMs are integrated in 3-D stack, the thermal and supply crosstalk degrade the SRAM performance and noise margin during read and write operations. [ABSTRACT FROM AUTHOR]

3-D technologies with stacked chips have the potential to provide new chip architecture, and improved device density, performance, efficiency, and bandwidth. The increased power density in 3-D technologies can become a daunting challenge for heat removal. Furthermore, power density can be highly nonuniform, leading to time- and space-varying hotspots, which can severely affect performance and reliability of integrated circuits. It is important to mitigate on-chip thermal gradients while considering the associated cooling costs. One efficient method of hotspot thermal management is to use superlattice thermoelectric coolers (TECs), which can provide on demand and localized cooling. In this paper, a detailed 3-D thermal model of a stacked electronic package with two dies and four ultrathin integrated TECs is developed to investigate the efficacy of TECs in hotspot cooling for 3-D technology. A strong vertical coupling has been observed between TECs located in top and bottom dies. Bottom TECs can significantly heat the top hotspots in both steady-state and transient operation. TECs need to be carefully placed inside the package to avoid such undesired heating. Thermal contact resistances between dies, inside the TEC module, and between TEC and heat spreader are shown to have a crucial effect on the TEC performance. We observe up to 5.6^\circC of active hotspot cooling in steady state and 7.4^\circC of active hotspot cooling using a square root current pulse. [ABSTRACT FROM PUBLISHER]

This paper presents the effect of proactive spatiotemporal power multiplexing on the thermal field in many-core processors. Power multiplexing migrates the locations of active cores within a chip after each fixed time interval, referred to as the migration interval, to redistribute the generated heat and thereby reduce the peak temperature and spatial and temporal nonuniformity in the thermal field. Clock and supply gating is used to minimize the power of the deactivated cores. The control of the migration interval is studied considering a 256-core processor at the predictive 16-nm node to evaluate the conflicting impact of the migration interval on thermal field and system performance. [ABSTRACT FROM PUBLISHER]

In this paper, we present a methodology for characterization and repair of signal degradation in through-silicon-vias (TSVs) in 3-D integrated circuits (ICs). The proposed structure can detect the signal degradation through TSVs due to resistive shorts in liner oxide and variations in resistance of TSV due to weak open and/or bonding resistance. For TSVs with moderate signal degradations, the proposed structure reconfigures itself as signal recovery circuit to maintain signal fidelity. This allows electrical repair of TSVs with moderate defects leading to better design yield and system functionality. This paper presents the design of the test and recovery structure and demonstrates their effectiveness through stand alone simulations as well as in a full-chip physical design of a 3-D IC. [ABSTRACT FROM PUBLISHER]