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This paper presents two main contributions toward efficient very large scale integration circuits mapped with simple cells: 1) a complete synthesis flow to provide good-quality circuits mapped only with simple cells; and 2) an area-oriented, level-aware buffering algorithm based on inverter trees to fix cell fanout violations. An effective pattern-based algorithm to identify XORs/XNORs on and-inverter graphs is also presented. We show that efficient implementations in terms of inverter count, transistor count, area, power, and delay can be generated from circuits with a reduced number of both simple cells and inverters, combined with XOR/XNOR-based optimizations. The proposed buffering algorithm can handle all unfeasible fanout occurrences, while: 1) optimizing the number of added inverters and 2) assigning cells to the inverter tree based on their level criticality. When comparing with academic and commercial approaches, we are able to simultaneously reduce the average number of inverters, transistors, area, power dissipation, and delay up to 48%, 4%, 8%, 14%, and 16%, respectively. [ABSTRACT FROM AUTHOR]

We present an algorithm for passivity verification and enforcement of multivariate macromodels whose state-space matrices depend in closed form on a set of external or design parameters. Uniform passivity throughout the parameter space is a fundamental requirement of parameterized macromodels of physically passive structures, that must be guaranteed during model generation. Otherwise, numerical instabilities may occur, due to the ability of nonpassive models to generate energy. In this paper, we propose the first available algorithm that, starting from a generic parameter-dependent state-space model, identifies the regions in the frequency-parameter space where the model behaves locally as a nonpassive system. The approach we pursue is based on an adaptive sampling scheme in the parameter space, which iteratively constructs and perturbs the eigenvalue spectrum of suitable skew-Hamiltonian/Hamiltonian pencils, with the objective of identifying the regions where some of these eigenvalues become purely imaginary, thus pinpointing local passivity violations. The proposed scheme is able to detect all relevant violations. An outer iterative perturbation method is then applied to the model coefficients in order to remove such violations and achieve uniform passivity. Although a formal proof of global convergence is not available, the effectiveness of the proposed implementation of the passivity verification and enforcement schemes is demonstrated on several examples. [ABSTRACT FROM AUTHOR]

Self-aligned double patterning (SADP) is one of the most promising techniques for sub-20 nm technology. Spacer-is-dielectric SADP using a cut process is getting popular because of its higher design flexibility; for example, it can decompose odd cycles without the need of inserting any stitch. This paper presents the first work that applies the cut process for decomposing odd cycles during routing. For SADP, further, overlay control is a critical issue for yield improvement; while published routers can handle only partial overlay scenarios, this paper identifies all the scenarios that induce overlays and proposes a novel constraint graph to model all overlays. With the developed techniques, our router can achieve high-quality routing results with significantly fewer overlays (and thus better yields). Compared with three state-of-the-art studies, our algorithm can achieve the best quality and efficiency, with zero cut conflicts, smallest overlay length, highest routability, and fastest running time. [ABSTRACT FROM PUBLISHER]

At the end of digital integrated circuit (IC) design flow, some nets may still be left open due to engineering change order (ECO). Resolving these opens could be quite challenging for some huge nets such as power ground nets because of a large number of obstacles and greatly distributed net components. Existing studies on multilayer obstacle-avoiding rectilinear Steiner trees may not be applicable to solve this problem because they assume the pins of an input net is a set of points, while the discrete net components in this problem can be regarded as a set of rectilinear pins. In this paper, we develop an efficient open-net connector that can deal with rectilinear pins. The proposed algorithm flow minimizes the total connection cost based on precise estimation of the shortest distance between each pair of rectilinear net components with the presence of complex obstacles. The experimental results show that the proposed flow can outperform the top-three teams of 2017 CAD contest at ICCAD and a state-of-the-art work in terms of total connection cost or runtime efficiency. [ABSTRACT FROM AUTHOR]

In this paper, a significantly efficient time-domain algorithm is presented to analyze a transmission line, loaded by a nonlinear component and driven by an arbitrary modulated signal. The proposed method provides the envelope of the solution and removes the redundancy of the calculations. The efficiency of this method is achieved in two major steps. First, an unconditionally stable algorithm for the nonlinear circuit is introduced; The derived equations are generated based on the finite-difference time-domain technique and the results are confirmed by those of the Leapfrog method. As the circuit is excited by a modulated signal, decreasing the computational time by using the unconditionally stable algorithm alone, is not practical. Therefore, in the second step, a new time-domain approach is presented and utilized simultaneously, based on separating the high and low frequency behavior of the modulated signal, which enables the advantage of unconditionally stable algorithm effectively. The accuracy of the presented method is confirmed by the Leapfrog algorithm. The comparisons from the given examples indicate that almost 99.97% of the CPU time is decreased by using the proposed method. [ABSTRACT FROM AUTHOR]

This paper presents fuzzy ${c}$ -means-based yield estimation (FUZYE), a methodology that reduces the time impact caused by Monte Carlo (MC) simulations in the context of analog integrated circuits (ICs) yield estimation, enabling it for yield optimization with population-based algorithms, e.g., the genetic algorithm (GA). MC analysis is the most general and reliable technique for yield estimation, yet the considerable amount of time it requires has discouraged its adoption in population-based optimization tools. The proposed methodology reduces the total number of MC simulations that are required, since, at each GA generation, the population is clustered using a fuzzy ${c}$ -means (FCMs) technique, and, only the representative individual (RI) from each cluster is subject to MC simulations. This paper shows that the yield for the rest of the population can be estimated based on the membership degree of FCM and RIs yield values alone. This new method was applied on two real circuit-sizing optimization problems and the obtained results were compared to the exhaustive approach, where all individuals of the population are subject to MC analysis. The FCM approach presents a reduction of 89% in the total number of MC simulations, when compared to the exhaustive MC analysis over the full population. Moreover, a ${k}$ -means-based clustering algorithm was also tested and compared with the proposed FUZYE, with the latest showing an improvement up to 13% in yield estimation accuracy. [ABSTRACT FROM AUTHOR]

Field programmable gate array (FPGA) packing and placement without routability consideration could lead to unroutable results for high-utilization designs. Conventional FPGA packing and placement approaches are shown to have severe difficulties to yield good routability. In this paper, we propose an FPGA packing and placement engine called UTPlaceF that simultaneously optimizes wirelength and routability. A novel physical and congestion aware packing algorithm and a hierarchical detailed placement technique are proposed. UTPlaceF outperforms state-of-the-art FPGA placers simultaneously in runtime and solution quality on International Symposium on Physical Design (ISPD) 2016 benchmark suite. Compared with the top three winners of ISPD’16 FPGA placement contest, UTPlaceF can deliver 6.2%, 11.6%, and 29.1% better routed wirelength with shorter runtime. [ABSTRACT FROM AUTHOR]

Clock trees are commonly used to deliver clock signals to sequential elements in circuits. However, by construction, tree structures are inherently prone to failure caused by variations. The robustness of a clock tree can be improved by inserting redundancy in the form of cross links or multilevel fusion trees. Such near-tree structures can provide robustness at low cost. In this paper, we establish that the locations of the inserted redundancy are crucial in providing cost-effective robustness. We present two methods to systematically insert redundancy. The redundancy is realized by either inserting cross links or performing local merges. Moreover, we present a vertex reduction method that reduces the amount of redundancy that needs to be inserted in our near-tree structures. Empirical results show that our structures are more robust to variations and have lower power consumption compared to the state-of-the-art clock networks. Furthermore, our near-tree structures provide smooth trade-offs between cost and robustness, reducing clock skews by 11%–39% at an expense of 3%–68% higher power consumption. [ABSTRACT FROM PUBLISHER]

Explaining the mismatch between predicted timing behavior from modeling and simulation, and the observed timing behavior measured on silicon chips can be very challenging. Given a list of potential sources, the mismatch can be the aggregate result caused by some of them both individually and collectively, resulting in a very large search space. Furthermore, observed data are always corrupted by some unknown statistical random noises. In this paper, we examine how trying to explain the mismatch observed on silicon can be classified as an ill-posed problem, where ill posed means that the solution may not be unique or stable. Thus, a small change in the observed response can have a large change in the predicted solution. To solve ill-posed problems, a statistical learning theory uses a principle called regularization. This paper proposes using a statistical learning method called support vector (SV) analysis to statistically analyze all known sources of uncertainty with the objective to rank which sources contribute the most to the observed mismatch. Experimental results are presented under different error assumption models to compare two kinds of SV ranking approaches to four other ranking approaches, where some use the idea of regularization and others do not. This paper is concluded by showing a self cross-validation approach to validate the ranking results when there is no true ranking available, as the case with actual silicon. [ABSTRACT FROM AUTHOR]

This paper proposes a framework for the incorporation of formal methods in the design flow of digital signal processing (DSP) systems in a rigorous way. In the proposed approach, DSP descriptions were modeled and verified at different abstraction levels using higher order logic based on the higher order logic (HOL) theorem prover. This framework enables the formal verification of DSP designs that in the past could only be done partially using conventional simulation techniques. To this end, a shallow embedding of DSP descriptions in HOL at the floating-point (FP), fixed-point (FXP), behavioral, register transfer level (RTL), and netlist gate levels is provided. The paper made use of existing formalization of FP theory in HOL and a parallel one developed for FXP arithmetic. The high ability of abstraction in HOL allows a seamless hierarchical verification encompassing the whole DSP design path, starting from top-level FP and FXP algorithmic descriptions down to RTL, and gate level implementations. The paper illustrates the new verification framework on the fast Fourier transform (FFT) algorithm as a case study. [ABSTRACT FROM AUTHOR]

Flow-based microfluidic biochips are attracting increasing attention with successful applications in biochemical experiments, point-of-care diagnosis, etc. Existing works in design automation consider the flow-layer design and control-layer design separately, lacking a global optimization and hence resulting in degraded routability and reliability. This paper presents a novel integrated physical co-design methodology, which seamlessly integrates the flow-layer and control-layer design stages. In the flow-layer design stage, a sequence-pair-based placement method is presented, which allows for an iterative placement refinement based on routing feedbacks. In the control-layer design stage, the minimum cost flow formulation is adopted to further improve the routability. Besides that, effective placement adjustment strategies are proposed to iteratively enhance the solution quality of the overall control-layer design. Experimental results show that compared with the existing work, the proposed design flow obtains an average reduction of 40.44% in flow-channel crossings, 31.95% in total chip area, and 22.02% in total flow-channel length. Moreover, all the valves are successfully routed in the control-layer design stage. [ABSTRACT FROM PUBLISHER]

Analog CMOS integrated circuits (ICs) designs depend typically on designer knowledge and experience, as such problems are multivariate and multiobjective, presenting many combinations of input variables to be investigated in order to meet the required specifications. Nowadays, the a posteriori approach is widely used to perform the optimization processes of analog CMOS ICs using evolutionary algorithms. However, these techniques are not totally able to explore potential solutions in specific regions of the Pareto front. Designers then have difficulty in choosing the best solution capable of achieving all desired specifications simultaneously among all the ones found. In this context, the a priori approach using fitness functions has become an important alternative method to overcome these issues of the a posteriori methodology. This paper aims to compare different fitness function profiles used in the a priori optimization processes to boost the effectiveness of the search processes in relation to robustness, accuracy, and yield in analog CMOS ICs designs. We show that the Gaussian profile, proposed here, applied to the lower limit, center value, and upper limit fitness functions is able to improve all the a priori optimization evolutionary techniques investigated, including the genetic, imperialist competitive, and shuffled frog leaping algorithms. [ABSTRACT FROM PUBLISHER]

Multiple e-beam lithography (MEBL) is one of the most promising next generation lithography technologies for high volume manufacturing, which improves the most critical issue of conventional single e-beam lithography, throughput, by simultaneously using thousands or millions of e-beams. For parallel writing in MEBL, a layout is split into stripes and patterns are cut by stripe boundaries, which are defined as stitching lines. Critical patterns cut by stitching lines could suffer from severe pattern distortion or even yield loss. Therefore, considering the positions of stitching lines and avoiding stitching line-induced bad patterns are required during layout design. In this paper, we propose the first work of stitch-aware routing framework for MEBL based on a two-pass bottom-up multilevel router. We first identify three types of stitching line-induced bad patterns which should not exist in an MEBL-friendly routing solution. Then, stitch-aware routing algorithms are, respectively, developed for global routing, layer/track assignment, and detailed routing. Experimental results show that our stitch-aware routing framework can effectively reduce stitching line-induced bad patterns and thus may not only improve the manufacturability but also facilitate the development of MEBL. [ABSTRACT FROM PUBLISHER]

Controller area network (CAN) is a widely used protocol that allows communication among electronic control units (ECUs) in automotive electronics. It was extended to CAN with flexible data-rate (CAN-FD) to meet the increasing demand for bandwidth generated by the growing number of features in modern automobiles. The signal-to-frame packing problem has been studied in the literature for both CAN and CAN-FD. In this paper, we propose and formulate the signal offset assignment problem (SOAP) in CAN-FD to improve the bus utilization during frame packing. We propose two algorithmic themes to solve SOAP and establish their worst case performance guarantees. The first is a general approximation framework (GAF) which can use any approximation algorithm for the makespan minimization problem (MMP) in multiprocessor systems. Its performance guarantee is the product of the performance guarantee of the MMP algorithm and the number of distinct periods in the frame. The second is a 2-D strip packing-based framework (2DSPF) which uses the bottom left fill algorithm for 2-D strip packing. The performance guarantee is $2{G}$ , where ${G}$ is the minimum number of groups into which the set of signals can be partitioned so that the periods of the signals in the same group form a geometric series. The experimental results for GAF and 2DSPF indicate that by carefully assigning offsets for signals in frame packing schemes, one can achieve about 10.83% improvement in bus utilization in CAN-FD systems. [ABSTRACT FROM AUTHOR]

Lab-on-chip (LoC) technology has emerged as one of the major driving forces behind the recent surge in biochemical protocol automation. Dilution and mixture preparation with fluids in a desired ratio, constitute basic steps in sample preparation for which several LoC-based architectures and algorithms are known. The optimization of cost and time for such protocols requires proper sequencing of fluidic mix-and-split steps, and storage-units for holding intermediate-fluids to be reused in the later steps. However, practical design constraints often limit the amount of on-chip storage in microfluidic LoC architectures and thus can badly affect the performance of the algorithms. Consequently, results generated by previous work may not be useful (in the case they require more storage-units than available) or more expensive than necessary (in the case when storage-units are available but not used, e.g., to further reduce the number of mix/split operations or reactant-cost). In this paper, we propose new algorithms for dilution and mixing with continuous-flow-based LoCs that explicitly take care of storage constraints while optimizing reactant-cost and time of sample preparation. We present a symbolic formulation of the problem that captures the degree of freedom in algorithmic steps satisfying the specified storage constraints. Solvers based on Boolean satisfiability are used to achieve the optimization goals. The experimental results show the efficiency and effectiveness of the solution as well as a variety of applications where the proposed methods would prove beneficial. [ABSTRACT FROM AUTHOR]

In this paper, we investigated the technique for improving the reliability of 3-D processor with faults by reconfiguring a 3-D fault-free subarray utilizing as many nonfaulty process elements (PEs) as possible. A novel flexible rerouting scheme is proposed, which makes the PEs can be rerouted or bypassed in three dimensions, hence increasing the number of neighbors of each element to construct a logical array. Under this scheme, an efficient heuristic algorithm is presented to construct a logical array. The experimental results show that the proposed algorithm under flexible rerouting scheme can produce logical arrays with higher harvest from the host arrays with faults for the random fault scenarios, the improvement is by up to 46.47% compared to the state-of-the-arts. [ABSTRACT FROM AUTHOR]

This paper studies the application of fixed-parameter tractable (FPT) algorithms to solve computer-aided design (CAD) problems. Specifically, we focus on layout decomposition problems for four lithography technologies: 1) double patterning lithography (DPL); 2) DPL with e-beam lithography; 3) DPL with directed self-assembly; and 4) DPL with directed self-assembly and e-beam lithography. Layout decomposition for the first three technologies are long-standing open problems without efficient optimal solutions, and the fourth technology is very promising in the future. The proposed approaches use ideas drastically different from all the previous works and can normally get optimal solutions in a short time. We show the great potential of applying FPT algorithms to solve more NP-hard problems efficiently in CAD. [ABSTRACT FROM AUTHOR]

As technology scales and frequencies increase, a new hybrid design style emerges, wherein designs contain a mixture of random logic and datapath standard-cell components. This paper demonstrates that conventional half-perimeter wirelength driven placers underperform in terms of regularity and Steiner wirelength (StWL) for such hybrid designs. In addition, the quality gap between manual and automatic placement is more pronounced as the designs become more datapath oriented. To effectively handle hybrid designs, this paper proposes a new unified placement flow that simultaneously places random logic and datapath cells. This flow is built on the top of a leading academic force-directed placer and significantly improves the quality of datapath placement while leveraging the speed and flexibility of existing random-logic placement algorithms. It consists of a suite of novel global and detailed placement techniques, collectively called structure-aware placement techniques (SAPT). These techniques effectively integrate alignment constraints into placement, thereby overcoming the deficiencies of existing random-logic placers when handling designs with embedded datapaths. Compared to other state-of-the-art placers, SAPT improves total StWL by more than 28% and total routing overflow by over six times on the ISPD 2011 datapath benchmark suite. In addition, it improves total StWL by 5.8% on industrial hybrid designs. [ABSTRACT FROM AUTHOR]

Clock trees can be constructed based on static arrival time constraints or dynamic implied skew constraints. Dynamic implied skew constraints allow the full timing margins to be utilized. However, the dynamic skew constraints require a high run-time complexity to be evaluated. In contrast, static arrival time constraints are more restrictive but can be evaluated in constant time. Consequently, there is a tradeoff between timing margin utilization and run-time. In this paper, a scalable clock tree synthesis (CTS) framework is proposed for the construction of low-cost useful skew trees (USTs) with high timing quality. The scalability is based on combining the use of arrival time constraints with virtual minimum and maximum delay offsets, which facilitates that a pair of smaller subtrees can be joined into a larger subtree in constant time. The ability to quickly join subtrees is leveraged to perform a high degree of solution space exploration, which translates into the construction of USTs with low-cost. In particular, clock trees with various routing tree topologies, buffer tree topologies, buffer sizes, and stem wire lengths are explored. Moreover, the arrival time constraints are specified with the objective of being the least restrictive to reduce cost. Furthermore, the constraints are respecified throughout the tree construction process using a slack graph (SG) to expose additional timing margins. The high timing quality is obtained by seamlessly integrating arbitrary timing models using the SG. Finally, the proposed CTS framework is integrated with a clock tree optimization framework to demonstrate that the constructed USTs are capable of meeting timing constraints under the influence of on-chip variations. [ABSTRACT FROM AUTHOR]

It is necessary for cost consideration to minimize the number of the used layers in a high-speed printed circuit board (PCB) design. In this paper, any independent net cannot be treated as a bus-oriented net in a high-speed PCB design because of no timing-matching constraint on an independent net. Any independent net in a high-speed PCB design can be modeled to obey the via-count constraint as the maximum number of the permitted vias for signal integrity. Clearly, the introduction of the permitted vias onto the independent nets can lead to the reduction on the number of the used layers in a high-speed PCB design. Given a set of bus-oriented nets and a set of independent nets with a via-count constraint in a high-speed PCB design, by introducing virtual vias onto independent nets and eliminating redundant vias on any used layer, a generalized algorithm can be proposed to minimize the number of the used layers with satisfying the via-count constraint on any independent net and assign the given bus-oriented nets and the separated segments inside the given independent nets onto the used layers. Compared with Yan’s algorithm with no via introduction on independent nets, the experimental results show that our proposed algorithm with ${c_{\max } = 1}$ , ${c_{\max } = 2}$ , ${c_{\max } = 3}$ , ${c_{\max } = 4}$ , and ${c_{\max } = 5}$ use reasonable CPU time to insert permitted vias to reduce 2.1, 2.8, 3.8, 4.4, and 4.6 used layers on the average for ten tested examples, respectively. Compared with a two-phase algorithm with via introduction on independent nets, the experimental results show that our proposed algorithm with ${c_{\max } = 1}$ , ${c_{\max } = 2}$ , ${c_{\max } = 3}$ , ${c_{\max } = 4}$ , and ${c_{\max } = 5}$ use less CPU time to reduce 1.6, 1.7, 1.7, 1.6, and 1.5 used layers on the average with increasing 13.3%, 16.3%, 10.6%, 4.2%, and 2.6% of the total used vias on the independent nets for ten tested examples, respectively. [ABSTRACT FROM AUTHOR]

Neuro-inspired architectures based on synaptic memory arrays have been proposed for on-chip acceleration of weighted sum and weight update in machine/deep learning algorithms. In this paper, we developed NeuroSim, a circuit-level macro model that estimates the area, latency, dynamic energy, and leakage power to facilitate the design space exploration of neuro-inspired architectures with mainstream and emerging device technologies. NeuroSim provides flexible interface and a wide variety of design options at the circuit and device level. Therefore, NeuroSim can be used by neural networks (NNs) as a supporting tool to provide circuit-level performance evaluation. With NeuroSim, an integrated framework can be built with hierarchical organization from the device level (synaptic device properties) to the circuit level (array architectures) and then to the algorithm level (NN topology), enabling instruction-accurate evaluation on the learning accuracy as well as the circuit-level performance metrics at the run-time of online learning. Using multilayer perceptron as a case-study algorithm, we investigated the impact of the “analog” emerging nonvolatile memory (eNVM)’s “nonideal” device properties and benchmarked the tradeoffs between SRAM, digital, and analog eNVM-based architectures for online learning and offline classification. [ABSTRACT FROM AUTHOR]

Current trends in high performance and embedded computing include design of increasingly complex hardware architectures with high parallelism, heterogeneous processing elements, and nonuniform communication resources. In order to take hardware and software design decisions, early evaluations of the system nonfunctional properties are needed. These evaluations of system efficiency require electronic system-level information on both algorithms and architecture. Contrary to algorithm models for which a major body of work has been conducted on defining formal models of computation (MoCs), architecture models from the literature are mostly empirical models from which reproducible experimentation requires the accompanying software. In this paper, a precise definition of a model of architecture (MoA) is proposed that focuses on reproducibility and abstraction and removes the overlap previously existing between the notions of MoA and MoC. A first MoA, called the linear system-level architecture model (LSLA), is presented. To demonstrate the generic nature of the proposed new architecture modeling concepts, we show that the LSLA model can be integrated flexibly with different MoCs. LSLA is then used to model the energy consumption of a state-of-the-art multiprocessor system-on-chip (MPSoC) when running an application described using the synchronous dataflow MoC. A method to automatically learn LSLA model parameters from platform measurements is introduced. Despite the high complexity of the underlying hardware and software, a simple LSLA model is demonstrated to estimate the energy consumption of the MPSoC with a fidelity of 86%. [ABSTRACT FROM AUTHOR]

This paper presents an incremental timing-driven placement tool, named OWARU. It optimizes timing critical paths through a free space-aware path smoothing: the gates on such paths are relocated to free spaces around the smoothed paths, while incremental static timing analysis is involved to accurately assess timing changes due to the relocation. OWARU is extended to accommodate gate sizing and layer assignment to demonstrate the effectiveness of unified physical synthesis optimizations and incremental placement. The goal is to show that OWARU is an ideal platform for timing closure at later stages of a physical design flow. OWARU is applied on a set of test circuits from 14-nm high-performance commercial microprocessors, which originally failed in timing closure. On average, the worst slack is improved by 63.6%, which corresponds to 5.0% of the clock period; total negative slack is improved by 69.1%. [ABSTRACT FROM AUTHOR]

This paper develops a dynamically adaptive stochastic tunneling (DAST) algorithm to avoid the “freezing” problem commonly found when using simulated annealing for circuit placement on field-programmable gate arrays (FPGAs). The main objective is to reduce the placement runtime and improve the quality of final placement. We achieve this by allowing the DAST placer to tunnel energetically inaccessible regions of the potential solution space, adjusting the stochastic tunneling schedule adaptively by performing detrended fluctuation analysis, and selecting move types dynamically by a multi-modal scheme based on Gibbs sampling. A prototype annealing-based placer, called DAST, was developed as part of this paper. It targets the same computer-aided design flow as the standard versatile placement and routing (VPR) but replaces its original annealer with the DAST algorithm. Our experimental results using the benchmark suite and FPGA architecture file which comes with the Toronto VPR5 software package have shown a 18.3% reduction in runtime and a 7.2% improvement in critical-path delay over that of conventional VPR. [ABSTRACT FROM AUTHOR]

Embedded memories are increasingly identified as having potential for introducing new yield loss mechanisms at a rate, magnitude, and complexity large enough to demand major changes in fault diagnosis techniques. In particular, time-related or complex read faults that originate in the highest density areas of semiconductor designs require new methods to diagnose more complex faults affecting large groups of memory cells. This paper presents a built-in self-test (BIST)-based fault diagnosis scheme that can be used to identify a variety of failures in embedded random-access memory arrays. The proposed solution employs flexible test logic to record test responses at the system speed with no interruptions of a BIST session. It offers a simple test flow and enables detection of time-related faults. Furthermore, the way test responses are processed allows accurate and time-efficient reconstruction of error bitmaps. The proposed diagnostic algorithms use a number of techniques, including discrete logarithm-based counting with ring generators acting as very fast event counters and signature analyzers. Experimental results confirm high diagnostic accuracy of the proposed scheme and its time efficiency. [ABSTRACT FROM AUTHOR]

Capacitor mismatch can generally result from two sources of error: random mismatch and systematic mismatch. Random mismatch is caused by process variation, while systematic mismatch is mainly due to an asymmetrical layout and processing gradients. A common centroid structure may be used to reduce systematic mismatch errors, but not random mismatch errors. Based on the spatial correlation model, this paper formulates the placement optimization problem of analog circuits using switched-capacitor techniques. A placement with higher correlation coefficients of the unit capacitors results in a higher acceptance rate, or chip yield. This paper proposes a heuristic algorithm that quickly and automatically derives the placement of the unit capacitors with the highest, or near-highest, correlation coefficients for yield improvement. Results show that the resultant placement derived from the proposed algorithm achieves better yield improvement than that from a common centroid approach. The proposed heuristic algorithm can be applied for any arbitrary capacitor ratios, i.e., more than two capacitors. [ABSTRACT FROM AUTHOR]

This paper presents two symbolic model checking algorithms for the verification of analog/mixed-signal circuits. The first model checker utilizes binary decision diagrams while the second is a bounded model checker that uses a satisfiability modulo theory solver. Both methods have been implemented, and preliminary results are promising. [ABSTRACT FROM AUTHOR]

In this paper, we propose the first metal-density-driven (MDD) placement algorithm to reduce chemical-mechanical planarization/polishing (CMP) variation and achieve higher routability. To efficiently estimate metal density and thickness, we first apply a probabilistic routing model and then a predictive CMP model to obtain the metal-density map. Based on the metal-density map, we use an analytical placement framework to spread blocks to reduce metal-density variation. Experimental results based on BoxRouter and NTUgr show that our method can effectively reduce the CMP variation. By using our MDD placement, for example, the topography variation can be reduced by up to 38% (23%) and the number of dummy fills can be reduced by up to 14% (8%), compared with those using wirelength-driven (cell-density-driven) placement. The results of our MDD placement can also lead to better routability. [ABSTRACT FROM AUTHOR]

This paper presents a new low-power test scheme integrated with the embedded deterministic test environment. The key contribution of this paper is a flexible test cube encoding scheme, which, in conjunction with a continuous flow decompressor, allows one to significantly reduce toggling rates when test patterns are fed into scan chains. The proposed solution requires neither additional design for testability logic nor modifications to the circuit under test. Experimental results obtained for industrial designs indicate that using this nonintrusive technique reduces switching activity to such extent that the resultant scan-in power consumption is similar to that of the functional mode, thus alleviating problems that are related to average and peak power dissipation, overheating, and risk of reliability degradation. Our approach seamlessly integrates with test logic synthesis flow, and it does not compromise compression ratios. Moreover, it fits well into various design paradigms, including modular design flow where modules come with individual decompressors and compactors. [ABSTRACT FROM AUTHOR]

This paper solves the variation-aware decoupling capacitance (decap) budgeting problem. Unlike previous works which only consider worst case design, for the first time, we consider the input of both process variation and operation variation for decap budgeting. A novel stochastic current model is proposed that efficiently and accurately captures temporal correlation between clock cycles, logic-induced correlation between ports, and current variation due to process variation with spatial correlation. An iterative alternative programming algorithm that is applicable to a variety of current models is then developed. Compared with the baseline model which assumes maximum current peaks at all ports, the model considering temporal correlation reduces noise by up to 5×, and the model considering both temporal and logic-induced correlations reduces noise by up to 17×. Compared with using deterministic process parameters, considering process variation (in particular Leff variation) reduces the mean noise by up to 4× and 3σ noise by up to 13× when both applying the current model with temporal and logic-induced correlations. Note that stochastic optimization has been used mainly for process variation in the literature, but this paper convincingly demonstrate that stochastic optimization considering operation variation is effective to reduce overdesign introduced by worst case design for power integrity. Such stochastic optimization has a wide scope of applications to design problems. To the best of our knowledge, this is the first in-depth study on decap insertion for power network design considering current correlations including process variation. [ABSTRACT FROM AUTHOR]

This paper presents X-Press—a new two-stage test-response compactor that can be easily integrated with a multiple scan-chain environment. This compactor preserves all benefits of spatial compaction and offers, due to its overdrive sequential section, compression much higher than the ratio. of scan chains to compactor outputs. X-Press is also capable of handling a wide range of unknown (X) state profiles by deploying a two-level scan-chain-selection mechanism. In addition to a new compactor architecture, original contributions of this paper include a detailed analysis of two-level error masking caused by X states and a new algorithm to both rank scan chains and then to determine, in per-pattern mode, scan-chain-selection rules used to suppress X states. Experimental results obtained for a variety of designs show feasibility and efficiency of the proposed compaction scheme, altogether with actual impact of X states on a test-pattern count. Finally, diagnostic capabilities of the proposed scheme accompanied by further experimental results are also analyzed. [ABSTRACT FROM AUTHOR]

This paper addresses the equivalence verification problem of register-transfer level (RTL) descriptions that implement arithmetic computations (such as ADD, MULT) over bit vectors with finite widths. A bit vector of size m represents integer values from 0 to 2m – 1, implying that the corresponding integer values are reduced modulo 2m (%2m). This suggests that bit-vector arithmetic can be efficiently modeled as algebra over finite integer rings, where the bit-vector size (m) dictates the cardinality of the ring (Z2m). This paper models the arithmetic datapath verification problem as the equivalence testing of polynomial functions from Z2n1 × Z2n2 x ··· × Z2nd → Z2m. We formulate the equivalence problem f ≈ g into that of proving whether f – g ≈ 0%2m. Fundamental concepts and results from ‘number,’ ‘ring,’ and ‘ideal theory’ are subsequently employed to develop systematic complete algorithmic procedures to solve the problem. We demonstrate the application of the proposed theoretical concepts to high-level (behavioral/RTL) verification of bit-vector arithmetic within practical computer-aided design settings. Using our approach, we verify a set of arithmetic datapaths at RTL, where contemporary verification approaches prove to be infeasible. [ABSTRACT FROM AUTHOR]

Continual scaling of transistors and interconnects has exacerbated the power and thermal management problems in the design of ultralarge-scale integrated (ULSI) circuits. This pa- per presents an efficient thermal-analysis method of O(N lg N) complexity, where N is the number of blocks that discretize the heat-source or temperature-observation regions. The method is named LOTAGre and formulated using the Green's function for heat conduction through multiple-layer materials, which account for the structure of ULSI chips and the accompanying heat sinks and mounting accessories. In addition to analyzing the thermal effects of the distributive heat sources, LOTAGre also considers the ambient temperature effects that are generally excluded in conventional Green's function-based thermal-analysis tools in order to avoid the concomitant analytical complexity. By employing the well-known eigen-expansion technique and classical transmission-line theory, fully analytical and explicit formulas are derived in thus paper for the multilayer Green's function with the inclusion of the s-domain version, the homogeneous and inhomogeneous solutions to the heat-conduction equation. Then, the discrete cosine transform and its inversion are employed to accelerate the numerical computation of the homogeneous and inhomogeneous solutions. This paper includes extensive experimental results to demonstrate that LOTAGre can be as accurate as FLUENT, a sophisticated computational fluid dynamics tool, while speeding up the simulation run time by two to three orders of magnitude in comparison to FLUENT as well as conventional Green's function-based thermal-analysis methods. This paper also discusses the limitations of using the traditional single-layer thermal model in thermal analysis for approximating a multilayer chip structure. [ABSTRACT FROM AUTHOR]

This paper presents a new high-level synthesis methodology to generate optimized register-transfer level (RTL) implementations for multiprocess behavioral descriptions. The concurrent communicating processes specification paradigm is widely used in digital circuit and system design, and is employed in all popular hardware description languages. It has been shown that interprocess communication and synchronization can result in complex timing interdependencies, which significantly affect the performance of a multiprocess system. In this paper, we demonstrate that state-of-the-art high-level synthesis tools can generate significantly suboptimal implementations for behaviors that contain concurrent communicating processes. We present an analysis of how interprocess communication Impacts high-level synthesis steps, and describe a new methodology to adapt existing high-level synthesis tools to optimize multiprocess descriptions. Our methodology is based on executing multiprocess perfonnance analysis and process-by-process scheduling in an iterative manner. We present algorithms for key steps in the proposed methodology. We have performed extensive experiments in the context of a commercial high-level design flow to evaluate the proposed techniques. The results clearly demonstrate the utility of our techniques in synthesizing implementations with superior area, performance, and energy consumption. For example, up to 40.0% performance Improvement (average of 35.6%) was achieved with little or no area overhead (average of 4.8%). In effect, the proposed techniques lead to a shift of the entire area-delay tradeoff curve for a design, to include superior designs that were hitherto infeasible. Our techniques also simultaneously result in up to 50.0% (average of 33.5%) improvement in energy and up to 69.0% (average of 58.3%) improvement in the energy-delay product. [ABSTRACT FROM AUTHOR]

Timing performance and routability are two main goals of global muting. These two targets are mutually conflicting if we view and handle their effects independently. In this paper, we adopt a shadow price mechanism to incorporate the two issues into one unified objective function. We formulate global routing as a multicommodity flow problem. The objective function is the slack of congestion with the clock period as the delay limit from registers and inputs to registers and outputs. The multicommodity flow is expressed by a linear-programming formulation as a primal problem. We then convert the primal problem Into a dual formulation using the shadow price as the variables. The shadow price of a net is the sum of its congestion price and timing price. The primal and dual formulation offers theoretical upper and lower bounds of the routing solution. Throughout the optimization process, the difference of the two bounds reduces, which provides the user's insight into the quality of the solutions. Based on the new formulation, this paper presents the UTACO algorithm for standard cell global routing. [ABSTRACT FROM AUTHOR]

Although self-aligned double and quadruple patterning (SADP, SAQP) have promising processes for sub-20 nm node advanced technologies and beyond, not all layouts are compatible with them. In advanced technologies, feasible wafer image should be generated effectively by utilizing SADP and SAQP where a wafer image is determined by a selected mandrel pattern. However, predicting a mandrel pattern is not easy since it is different from the wafer image (or target pattern). In this paper, we propose new routing methods for spacer-is-dielectric (SID)-type SADP, SID-type SAQP, and spacer-is-metal (SIM)-type SADP to generate a feasible layout satisfying the connection requirements. Routing algorithms comprising simple connecting and cutting rules are performed on a new grid structure where two (SID-type SADP) or three colors (SID-type SAQP and SIM-type SADP) are assigned alternately to grid-nodes. Then a mandrel pattern is selected without complex coloring or decomposition methods. Also, we try to reduce hotspots (potentially defective regions) by the proposed dummy pattern flipping for SID-type SADP. In experiments, feasible layouts meeting the connection requirements are generated and the effectiveness of the proposed framework is confirmed. [ABSTRACT FROM PUBLISHER]

In this paper, we propose Lagrangian relaxation (LR)-based algorithms to optimize both circuit performance and total wirelength at the global placement stage. We introduce a general timing-driven global placement problem formulation that is applicable to three different circuit design styles: 1) synchronous circuits; 2) synchronous circuits with sequential optimization techniques; and 3) asynchronous circuits. LR is applied to handle the timing constraints of the formulated problem. Based on how the cell spreading constraints are handled, two different approaches are proposed: one approach handles the spreading constraints inside the LR framework and transforms the timing-driven placement (TDP) problem into a series of weighted wirelength minimization problems, which can be solved by directly leveraging existing wirelength-driven placers. The other approach handles the spreading constraints outside the LR framework. Thus, only timing constraints need to be taken care of in the LR framework and better solutions can be expected. In both approaches, we simplified the LR subproblem using Karush–Kuhn–Tucker conditions. Our algorithms are implemented based on a state-of-the-art wirelength-driven quadratic placer. The experiments demonstrate that the proposed algorithms are able to achieve significant improvements on circuit performance compared with a commercial wirelength-driven placement flow and a commercial asynchronous TDP flow. [ABSTRACT FROM PUBLISHER]

Layout-level gate or routing camouflaging techniques have attracted interest as countermeasures against reverse engineering of combinational logic. In order to minimize area overhead, typically only a subset of gate or routing components are camouflaged, and each camouflaged component layout can implement one of a few different functions or connections. The security of camouflaging relies on the difficulty of learning the overall combinational logic function without knowing the functions implemented by the individual camouflaged components of the circuit. In this paper, we expand our previous work on using incremental SAT solving to reconstruct the logical function of a circuit with camouflaged components. Our algorithm uses the standard attacker model in which an adversary knows only the noncamouflaged component functions, and has the ability to query the circuit to learn the correct output vector for any input vector. Our results demonstrate a $10.5\times$ speedup in average runtime over the best known existing deobfuscation algorithm prior to this technique. The results presented go beyond our previous work by showing that this technique, previously applied only to a particular style of gate camouflaging, is general and can be used to deobfuscate three different proposed styles of camouflaging. We give results to quantify the effectiveness of camouflaging techniques on a variety of ISCAS-85 benchmark circuits. [ABSTRACT FROM PUBLISHER]

The article discusses various reports from the 2009 Association for Computing Machinery International Symposium on Physical Design (ISPD) held in San Diego, California published within the issue, including one about combinatorial algorithm applicable for simultaneous gate sizing, one about design-for-manufacturability (DFM) and another about solving physical design problems.

This paper explores the use of discrete optimization techniques for variability-aware analog circuit synthesis, with an observation that the continuous design space can be effectively covered by a finite number of discrete points when parameter variation is present. Three algorithms are described that can leverage a discretized design space yet mitigate its dimensionality scaling problem: an isotropic discretization scheme, which can fill the neighborhood of any given point with only quadratically-increasing number of nearest neighbors placed at equal distances as the space dimension increases, a stochastic hill-climbing algorithm, which evaluates only a partial set of nearest neighbors yet finds the local optimum at the reduced cost, and an incremental Monte Carlo sampling algorithm, which draws the minimal number of Monte Carlo samples just enough to determine the superior design point during the local search process. These algorithms help in finding the optimal design of analog circuits efficiently. For instance, for a digitally-controlled oscillator example, its discretized design space consists of 5 565 907 points but the optimal point was found by evaluating only 40 design points and running only 21 Monte Carlo simulations per point in average (824 in total). [ABSTRACT FROM PUBLISHER]

SPICE offers an accurate method of simulating defect behavior. However, as demonstrated by recent research, it requires long computation time to simulate defect behavior, when considering process variation. To the best of our knowledge, there is no efficient variation-aware delay fault simulation methodology for resistive opens and resistive bridges. This paper presents a fast and accurate delay fault simulation methodology for these two defects. It is fast because it speeds up delay fault computation time by employing two efficient algorithms. The first algorithm is used to calculate transient gate output voltage, which is a key variable needed to compute delay faults. It employs a three step strategy to accelerate the computation of transient gate output voltage without compromising accuracy. The second algorithm uses bisection method to efficiently compute delay fault behavior of a fault-site. The proposed methodology (PM) has been incorporated in an open-source SPICE (NGSPICE) with BSIM4.7 transistor model. The methodology has been validated by comparing results with HSPICE using industrial designs from IWLS 2005 benchmarks and realistic fault-sites have been extracted from synthesized designs. Simulations are carried out using a 65-nm gate library (for illustration). When compared with HSPICE, results show that the PM is on average up to 52-times faster with \leq4.2\% error in accuracy for resistive open and 39-times faster with \leq5.2\% error in accuracy for resistive bridge defects. [ABSTRACT FROM PUBLISHER]

The flip-chip packaging is introduced for modern IC designs with higher integration density and larger I/O counts. It is necessary to consider routing obstacles for modern flip-chip designs, where the obstacles could be regions blocked for signal integrity protection (especially for analog/mixed-signal modules), prerouted or power/ground nets, and even for through-silicon vias for 3-D IC designs. However, no existing published works consider obstacles. To remedy this insufficiency, this paper presents the first work to solve the free-assignment flip-chip routing problem considering obstacles. For the free-assignment routing problem, most existing works apply the network-flow formulation. Nevertheless, we observe that no existing network-flow model can exactly capture the routability of a local routing region (tile) in presence of obstacles. This paper presents the first work that can precisely model the routability of a tile, even with obstacles. Based on this new model, a two-stage approach of global routing followed by detailed routing is proposed. The global routing computes a routing topology by the minimum-cost maximum-flow algorithm, and the detailed routing determines the precise wire positions. Dynamic programming is applied to further merge tiles to reduce the problem size. Compared to a state-of-the-art flow model with obstacle handling extensions, experimental results show that our algorithm can achieve 100% routability for all circuits while the extensions of the previous work cannot complete routing for any benchmark circuit with obstacles. [ABSTRACT FROM PUBLISHER]

Bit-width allocation has a crucial impact on hardware efficiency and accuracy of fixed-point arithmetic circuits. This paper introduces a new accuracy-guaranteed word-length optimization approach for feed-forward fixed-point designs. This method uses affine arithmetic, which is a well-known analytical technique, for both range and precision analyses. This paper introduces an acceleration technique and two new semianalytical algorithms for precision analysis. While the first algorithm follows a progressive search strategy, the second one uses a tree-shaped search method for fractional width optimization. The algorithms offer two different time-complexity/cost efficiency tradeoffs. The first algorithm has polynomial complexity and achieves comparable results with existing heuristic approaches. The second algorithm has exponential complexity, but it achieves near-optimal results compared to the exhaustive search method. A commonly used set of case studies is used to evaluate the efficiency of the proposed techniques and algorithms in terms of optimization time and hardware cost. The first and second algorithms achieve 10.9% and 13.1% improvements in area, respectively, over uniform fractional width allocation. The proposed acceleration technique reduces the complexity of the fractional width selection problem by an average of 20.3%. [ABSTRACT FROM PUBLISHER]

Monolithic 3-D ICs (M3-D ICs) offer extremely high vertical interconnection density, significantly improving the power-performance envelope when compared to conventional 2-D ICs. However, process limitations lead to one tier having either degraded transistors or interconnects. This paper models the amount of degradation that can be expected at current and future nodes (45, 22, and 10 nm), develops a process development kit using these models to enable evaluation, and presents a block-level M3-D IC RTL-to-GDSII flow that is capable of mitigating some of this degradation. Experimental results indicate that at lower technology nodes, M3-D ICs offer more benefits. Results also indicate that the impact of transistor degradation is diminished at lower technology nodes while the impact of interconnect degradation becomes worse. Overall, perfect M3-D ICs close more than half the gap in the power-performance envelope between 2-D ICs and the “ideal” block-level design. While degraded tiers reduce the benefit of M3-D ICs, our degradation-aware floorplanner gives back up to 17% of the loss, and helps to obtain significant overall benefits compared to 2-D ICs. [ABSTRACT FROM AUTHOR]

In 3-D integrated circuits (3-D ICs), through silicon via (TSV) is a critical technique to provide vertical connections. However, the yield and reliability challenge of TSV in industry is one of key obstacles to adopt the 3-D ICs technology. Various fault-tolerance structures by using additional spare TSVs (s-TSVs) to repair faulty functional TSVs (f-TSVs) have been proposed in literature for yield and reliability enhancement. However, these structures are formed in standard cell placement stage where all the f-TSVs are already placed. In reality, since the s-TSVs can be only inserted into the whitespace, the quality of the generated repair solution is strongly dependent on the whitespace distribution. In this paper, we propose an efficient TSV planning and repair framework in floorplanning stage, which takes nonuniform TSV distribution and clustered TSV defect-distribution into account. The proposed framework mainly consists of four stages: 1) a whitespace redistribution algorithm that uses a probability-based strategy to make the whitespace distribution more reasonable for the f-TSV planning. Subsequently, a convex-cost flow-based model for f-TSV allocation considering the fault clustering; 2) a top-down globally partitioning combined with a bottom-up locally merging to partition f-TSVs into groups with minimum hardware cost; 3) the min-cost max-flow algorithm for s-TSV allocation with minimum wirelength overhead; and 4) an integer linear programming-based model to form a fault-tolerance structure with minimum multiplexer delay overhead. The experimental results demonstrate that the proposed repair framework can improve the yield with minimum hardware cost and multiplexer delay overhead. [ABSTRACT FROM AUTHOR]

In this paper, we propose novel algorithms for pattern matching which dissects patterns into rectangles based on polygon edges. Unlike other design rule check (DRC)-based pattern matching algorithms, our solution utilizes simple DRC edge length rules to create rectangles for hotspot pattern descriptions. This approach has at least three advantages over other solutions. First, it is faster than other state-of-the-art pattern matching tools. Second, it is intuitive and simple for pattern matching engineers to understand and describe patterns. Third, it scales well for parallel computation. We also show how to improve pattern matching run time using vector space created by an origin rectangle and other reference rectangles inside a pattern bounding box. By adopting the vector concept, we iterate only once or twice when detecting different pattern orientations. Other pattern matching techniques usually iterate eight times (4 rotations $ \times \,\, 2$ mirrored images) to detect all of the eight different orientations. Our method eliminates these unnecessary iterations. [ABSTRACT FROM PUBLISHER]

Functional engineering change order (ECO) is a popular technique for rectifying design errors after synthesis and placement stages. We present a new approach to generating the patch circuits for multierror circuit rectification. In this paper, we propose a two-phase approach of: 1) discovering the functional matches in two circuits followed by 2) determining the final patch circuits from the matches. The ECO engine in this paper discovers functional and structural matches in two circuits by coordinating the SAT-sweeping and the cut-matching algorithms. Then, the patch selection is conducted by the combinational equivalence checking technique and a linear-time selection heuristic. The experimental results on public benchmark and industrial circuits demonstrate that this ECO engine outperforms state-of-the-art interpolation-based engines. [ABSTRACT FROM AUTHOR]

Model checking is a formal method for verifying whether the system satisfies a user-defined specification. Compared to simulation, model checking is restricted in capacity. On the other hand, simulation is weak in detecting bugs that require long and complex sequences of events to be exposed. This paper combines model checking and simulation in an abstraction-refinement scheme to mitigate the problems of both methods. Abstraction refinement iteratively constructs a simplified model to verify the original model. While a simplified model mitigates the weakness of model checking, the set of simplified error traces model helps guide simulation toward deep bugs. In abstraction refinement, concretization—a process of deriving an error trace in the original model from the abstract ones—is used to invalidate spurious abstract error traces or to refute a property. In this paper, we describe a novel concretization algorithm that combines simulation with satisfiability to efficiently refute properties with very long error traces. [ABSTRACT FROM AUTHOR]

Extensible processors have been widely used to achieve the conflicting demands for performance improvement, low power consumption, and flexibility. As extensible processors have become more popular, several algorithms have been proposed for automatically identifying instruction-set extensions in order to reduce the effort of manual design and verification. However, most of them focus on finding large and complex instructions that are used only once, rather than repeatedly used ones. Moreover, some other approaches that consider recurrence are limited to finding small instructions. This paper proposes a novel algorithm that considers the instruction reusability as well as input/output (I/O) serialization. In order to overcome the high complexity of the problem, we develop a canonical-form construction algorithm for fast isomorphism detection on directed acyclic graphs and an incremental template generation algorithm that identifies the best custom instruction in terms of a user-defined fitness function. Moreover, our algorithm serializes I/O operations so that the numbers of inputs and outputs of custom instructions are not limited by the microarchitecture. This paper also proposes an algorithm for multiple custom instructions utilizing a well-known iterative selection algorithm. Last, it presents a hybrid algorithm composed of our algorithm and the previous algorithm that does not consider reusability. Experimental results show that our isomorphism-aware algorithm achieves significant improvement over previous approaches in terms of algorithm runtime, as well as performance gain obtained by custom instructions. [ABSTRACT FROM AUTHOR]

Coarse-grained reconfigurable arrays (CGRAs) are a promising class of architectures conjugating flexibility and efficiency. Devising effective methodologies to map applications onto CGRAs is a challenging task, due to their parallel execution paradigm and constrained hardware resources. In order to handle complex applications, it is important to devise efficient strategies to partition a kernel into pieces that obey resource constraint and methodologies to schedule them on the underlying hardware. In this paper, we tackle these problems by proposing algorithms to address partitioning based on recursive searches over abstract trees. A novel scheduling strategy is also described that, leveraging differences in delays of various operations, is able to efficiently map operations on CGRA architectures. Experimental evidence on kernels derived from a diverse set of data flow graphs and EEMBC benchmarks demonstrate the efficacy of the described methods, which, when combined, achieve a higher runtime performance on a given mesh size than state-of-the-art approaches (as much as 38% for the benchmark applications considered). [ABSTRACT FROM AUTHOR]