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Microporous SiO2 can provide large electric-doublelayer (EDL) capacitance and negligible leakage current, owing to lack of electron carrier and limited mobility of mobile ions. The impedance spectroscopy (ionic-conductivity--frequency and capacitance--voltage characteristics) and Fourier-transformed infrared spectroscopy of microporous SiO2 are characterized, which demonstrated that such dielectric is actually a solid-electrolyte dielectric. InGaZnO4 thin-film transistors (TFTs) on paper substrates gated by microporous-SiO2 solid electrolyte are fabricated at roomtemperature.The largeEDL-specific capacitance (1.36 µF/ cm²) results in the paper TFTs operate at a battery-drivable low voltage of 1.0 V. Both depletion-mode (Vth = .0.45 V) and enhancement-mode (Vth = 0.25 V) operations are realized by rationally controlling the oxygen concentration in argon ambient during InGaZnO4 channel deposition. Electrical characteristics with an equivalent field-effect mobility of ~21 cm²/V ⋅ s, a current ON/OFF ratio of greater than 105, and a subthreshold swing of ~80 mV/dec are demonstrated at low frequencies, which are promising for portable paper electronics. [ABSTRACT FROM AUTHOR]

A novel plasma Charge Accumulative Model (pCAM) by calculating time-integrated Fowler–Nordheim (FN) tunneling charges and field of the gate dielectric in plasma processes is proposed in this paper. Our prior studies have developed and presented a quantitative FinFET plasma recording device by an effective fin-shaped field effect transistor (FinFET) contact-to-metal coupling structure to record and quantify plasma ion charges created in FinFET backend processes. In this paper, a precise analytical model is proposed to model the magnitude of plasma ion charges, time-integrated stressing field, and the criteria of the plasma process for optimum FinFET process technology. The new pCAM is highly matching with the measurement result of 16- and 7-nm FinFET wafers. The model can be adapted to practically estimate the plasma damage with different charge types, process parameters, and ion distribution; it can optimize the FinFET process and further understand the plasma damage mechanism in charging processes of 7-nm FinFET and beyond. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel reconfigurable ferroelectric FET (R-FEFET), which can reconfigure its operation between volatile and nonvolatile modes during run-time by dynamically modulating its hysteresis. The R-FEFET comprises of two gates with ferroelectric (FE) in both the gate stacks. One of these terminals serves as a regular gate, while the other is used as a control to introduce reconfigurability. Employing Landau–Khalatnikov equation-based FEFET model, we extensively analyze the device characteristics in both FinFET and planar technologies. We show that by changing the control voltage between 0 and 1 V, the hysteresis width (HW) can be modulated between 1.1 and 0.3 V. In addition, we show the device characteristics and advantages that R-FEFETs possess to overcome the drawbacks encountered with gate leakage in standard FEFETs. The hold margins in the nonvolatile mode of R-FEFETs increase by ~ $10\times $ with respect to standard FEFETs, and the drive current strengths in the volatile mode show 13% improvements when compared to standard FETs. Using the proposed R-FEFETs, we examine a low-power nonvolatile memory design in Part II of this paper. [ABSTRACT FROM AUTHOR]

In the domain of printed electronics (PE), field-effect transistors (FETs) with an oxide semiconductor channel are very promising. In particular, the use of high gate-capacitance of the composite solid polymer electrolytes (CSPEs) as a gate-insulator ensures extremely low voltage requirements. Besides high gate capacitance, such CSPEs are proven to be easily printable, stable in air over wide temperature ranges, and possess high ion conductivity. These CSPEs can be sensitive to moisture, especially for high surface-to-volume ratio printed thin films. In this paper, we provide a comprehensive experimental study on the effect of humidity on CSPE-gated single transistors. At the circuit level, the performance of ring oscillators (ROs) has been compared for various humidity conditions. The experimental results of the electrolyte-gated FETs (EGFETs) demonstrate rather comparable currents between 30%–90% humidity levels. However, the shifted transistor parameters lead to a significant performance change of the RO frequency behavior. The study in this paper shows the need of an impermeable encapsulation for the CSPE-gated FETs to ensure identical performance at all humidity conditions. [ABSTRACT FROM AUTHOR]

Ferroelectric and negative-capacitance field-effect transistors (FeFETs and NCFETs) have recently garnered great attention as devices for applications in memory and low-power logic, respectively. As these technologies are pursued, it is critical to have a variety of measurement approaches, including methods familiar to the electron-device and microwave communities that can aid in fully understanding the behavior of ferroelectrics in FeFETs and NCFETs. In this paper, we propose and show the viability of using frequency-domain electrical measurement techniques employing the well-known microwave S-parameters, and their large-signal generalization and X-parameters. Our methods provide the means to trace the intrinsic polarization versus electric-field curve of the ferroelectric, i.e., with the parasitics de-embedded, thereby showing the innate ferroelectric response, which cannot be done using conventional techniques. These methods also enable extraction of all the parameters of the Landau–Khalatnikov equation, which is commonly used to model ferroelectric behavior in FeFETs and NCFETs. This paper hence takes a useful step toward methods familiar to the electron-device community that can help to better understand and optimize FeFET and NCFET technologies. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel static random access memory (SRAM) unit cell design and its array structure consisting of single-gated feedback field-effect transistors (FBFETs). To verify the SRAM characteristics, the basic memory operations and write disturbances of the unit cell are investigated through the mixed-mode technology computer-aided design simulations. The unit cell exhibits the superior SRAM characteristics including a write speed of 0.6 ns, a fast read-out speed of ~0.1 ns, and a retention time of 3600 s. Furthermore, the unit cell design exhibits advantages in density, with a small cell area of 8F2, and in the power consumption; the standby power consumption is 0.24 nW/bit for holding “1” and negligible for holding “0.” Moreover, our SRAM array shows reliable ${3} \times {3}$ array operations without any disturbances. This paper demonstrates the promising potential of the FBFET SRAM for high-performance, high-density, and low-power memory applications. [ABSTRACT FROM AUTHOR]

In this paper, the threshold voltage characteristics of silicon nanowire metal–oxide–semiconductor field-effect transistor (MOSFET) with a double-layer gate structure are presented. This type of device is considered to be the most promising application of nanodevice in ultralarge-scale integration, due to several advantages such as similar operation principle as the junctionless nanowire transistor, the screening effect of the upper gate (UG) to shield the lower gate MOSFETs from external electromagnetic disturbance, the tradeoff between the short channel and the thick-gate oxide layer, and the compatible fabrication process with the conventional MOS technology. In this paper, the relations of threshold voltage versus the gate length, the UG bias, the substrate bias, the drain bias, and the temperature are measured and analyzed. Moreover, the penetration effect of the UG electric field is proposed to interpret the short-channel characteristics of the device, and a piecewise curve model is presented to reveal the underlying physics of the relation of the threshold voltage versus the drain bias. The double-layer gate structure technology enables the design of many devices, such as small-signal analog circuit units, single-electron devices, and quantum bit cells. [ABSTRACT FROM AUTHOR]

This paper demonstrates a high-performance black phosphorus nanoribbons field-effect transistor (BPNR-FET) and systematically investigates methods for enhancing its anisotropic carrier transport. The BPNR-FET shows a strong dependence on crystal orientation in which the best mobility performance is achieved in armchair-oriented nanoribbons. A downscaling of nanoribbon width is shown to improve the short-channel effect owing to a better electrostatic gate control. Furthermore, hydrogenation is employed to effectively passivate the dangling bonds and heal the nanoribbon edge defects, leading to nearly hysteresis-free transfer properties. By virtue of bandgap and contact-metal workfunction engineering, n-type BPNR-FET is successfully demonstrated, which enables complementary inverter circuits to be simultaneously realized. This paper unravels the superior performance underscores a conceptually new BPNR-FET, paving the way toward the development of non-planar devices and integrated circuits based on 2-D materials platform. [ABSTRACT FROM AUTHOR]

In this paper, a n-type junctionless FET (JLFET) with a p-type fin body (FB) is investigated using a 3-D numerical simulator. We show that the proposed device (FB-JLFET) with a p+ FB can control the electrostatic potential of the channel more efficiently for multi- ${V} _{\text{TH}}$ (threshold voltage) and dynamic threshold (DT) operation. Moreover, body bias application is implemented in FB-JLFET and a large body factor ($\gamma $) is predicted for wide range ${V} _{\text{TH}}$ modulation. Thanks to the stronger potential coupling between the channel and FB, the proposed device exhibits $\gamma $ improvement compared to the conventional JL bulk FinFETs under the same electrostatic control. In addition, DT operation is studied in the form of a JLFET for the first time and it exhibits 37% improvement of the on-state drive current and better subthreshold swing (S.S.) compared to FB-JLFET without DT. This paper provides the feasibility of multi- ${V} _{\text{TH}}$ operation with body bias mode for high performance or low-power applications and DT operation for high-speed circuits with low power consumption. [ABSTRACT FROM AUTHOR]

In this paper, we explored the characteristic fluctuations induced by various random discrete dopants (RDDs) on gate-all-around silicon nanowire metal–oxide semiconductor field-effect transistors. A 3-D quantum-mechanically corrected transport model was employed to analyze the simulated devices. The statistical results indicate that the variation of threshold voltage ( ${V}_{\text {th}}$ ) not only can be reduced from 28.6% to 10.7% without channel doping and penetration from the source/drain into the channel, but also the variation of 3-dB frequency can be reduced from 8% to 2.7% due to the reduction of the variation of ${V}_{\text {th}}$. We reported that the high-frequency characteristic fluctuations (voltage gain and cutoff frequency) were dominated by electron mobility. This caused by RDDs from the drain extension exhibited less variability than that caused by RDDs from the source extension due to a reduced injection velocity near the S side and a negligible difference in the electron saturation velocity near the D side. This paper provides pertinent information on the design of high-frequency amplifier circuits in relation to devices with RDDs induced by variations in the semiconductor process. [ABSTRACT FROM AUTHOR]

In negative capacitance field-effect transistors (NCFETs), drain current may decrease with increasing ${V}_{\mathrm {ds}}$ in the saturation region, leading to negative differential resistance (NDR). While NDR is useful for oscillator design, it is undesirable for most analog circuits. On the other hand, the tendency toward NDR may be used to reduce the normally positive output conductance ( ${g}_{ \mathrm {ds}}$ ) of a short-channel transistor to a nearly zero positive value to achieve higher voltage gain. In this paper, we analyze the NDR effect for NCFET in the static limit and demonstrate that it can be engineered to reduce ${g}_{\mathrm {ds}}$ degradation in short-channel devices. Small and positive $g_{\mathrm{ ds}}$ is achieved without compromising the subthreshold gain, which is crucial for analog applications. The 7-nm ITRS 2.0 FinFET with 0.7 V ${V}_{\mathrm {dd}}$ is used as the baseline device in this paper. [ABSTRACT FROM AUTHOR]

This paper presents experimental and simulation analysis of an $\Omega $ -shaped silicon junctionless nanowire field-effect transistor (JL-NWT) with gate lengths of 150 nm and diameter of the Si channel of 8 nm. Our experimental measurements reveal that the ON-currents up to 1.15 mA/ $\mu \text{m}$ for 1.0 V and 2.52 mA/ $\mu \text{m}$ for the 1.8-V gate overdrive with an OFF-current set at 100 nA/ $\mu \text{m}$. Also, the experiment data reveal more than eight orders of magnitude ON-current to OFF-current ratios and an excellent subthreshold slope of 66 mV/dec recorded at room temperature. The obtained experimental current–voltage characteristics are used as a reference point to calibrate the simulations models used in this paper. Our simulation data show good agreement with the experimental results. All simulations are based on drift-diffusion formalism with activated density gradient quantum corrections. Once the simulations methodology is established, the simulations are calibrated to the experimental data. After this, we have performed statistical numerical experiments of a set of 500 different JL-NWTs. Each device has a unique random distribution of the discrete dopants within the silicon body. From those statistical simulations, we extracted important figures of merit, such as OFF-current and ON-current, subthreshold slope, and voltage threshold. The performed statistical analysis, on samples of those 500 JL-NWTs, shows that the mean ${I}_{D} - {V}_{\text {Gs}}$ characteristic is in excellent agreement with the experimental measurements. Moreover, the mean ${I}_{D} - {V}_{\text {Gs}}$ characteristic reproduces better the subthreshold slope data obtained from the experiment in comparison to the continuous model simulation. Finally, performance predictions for the JL transistor with shorter gate lengths and thinner oxide regions are carried out. Among the simulated JL transistors, the configuration with 25-nm gate length and 2-nm oxide thickness shows the most promising characteristics offering scalable designs. [ABSTRACT FROM AUTHOR]

Efficient charge carrier transport in organic thin film transistors (OTFTs) often requires thin films with highly oriented feature. Although there are a number of methods to effectively form high-degree and large-scale alignment during the process of film formation, these methods usually resulted in nonuniform films. In order to obtain highly aligned uniform films, this paper provides a postalignment method after film formation. By applying electric field during solvent annealing, the polymer backbone can be reorganized along the direction of the electric field, leading to highly aligned polymer chains and significant improvement in charge mobility. In addition, after doping the polymer films with liquid crystal (LC), with the benefit of LC molecules' template, the degree of orientation of polymer molecular chains was further enhanced, resulting in further improvement of the charge mobility up to 9.42 cm² ·V-1·s-1. This paper exhibits the possibility of improving charge transport after film formation to obtain high-performance solution-processable OTFT for low-cost and large-scale organic electronics. [ABSTRACT FROM AUTHOR]

Parasitic capacitance in nanoscale FETs is becoming a dominant component of the total device capacitance which degrades device and circuit performance. This problem is exacerbated with the introduction of multigate FETs such as FinFET and gate-all-around FETs. In this paper, we introduce the corner spacer design for gate-all-around nanowire FET to significantly decrease parasitic capacitance with negligible degradation in ON-current. We show that the parasitic capacitance of a well-engineered corner spacer in a nanowire FET can be reduced by over 80% compared to the device with full nitride spacers. Ring oscillator stage delay and energy consumption of the corner spacer design are lower than the full spacer by over 50% each. This paper shows the possibility of engineering the spacers as a performance booster to continue scaling. [ABSTRACT FROM AUTHOR]

With lots of interest in negative capacitance field-effect transistors for ultralow-power complementary metal-oxide-semiconductor technology, negative capacitance thin-film transistors (NCTFTs) have also received much attention. Although previous studies on NCTFTs were done, the NC effect in organic-based TFTs was not studied yet. In this paper, P(VDF-TrFE) ferroelectric-gated P3HT semiconductor channel TFTs are experimentally demonstrated with solution-based fabrication process. Especially, this paper shed light on the NC effect in the organic based TFTs. The step-up current-voltage characteristics are repeatedly and reliably observed in diverse TFTs, and then, with the results, transconductance (gm) amplification implemented by the negative capacitance was delved. Moreover, with the aid of ferroelectric polarization switching, super steep-switching characteristic of the organic-based TFT was experimentally confirmed. These experimental results and discussion would be helpful in understanding NC effects in TFTs. [ABSTRACT FROM AUTHOR]

The physical mechanisms involved in the trapping and de-trapping processes associated with surface donor traps in gallium nitride (GaN) transistors are discussed in this paper. The paper challenges the conventional transient techniques adopted for extrapolating the trap energy level via experiments and TCAD simulations. Transient TCAD simulations were employed to reproduce the time-dependent electrical behavior of a metal-on-insulator field-effect transistor and explain the influence of the electric field and energy barrier on the transient time associated with the trapping and de-trapping mechanisms of surface traps. The comparison between three test structures and the relative variation of the trapping and de-trapping times with the bias and trap parameters leads to the suggestion of a proposed test structure and bias configuration to accurately extrapolate the energy level of surface traps in GaN transistors. [ABSTRACT FROM AUTHOR]

Negative capacitance FETs (NCFETs) have attracted significant interest due to their steep-switching capability at a low voltage and the associated benefits for implementing energy-efficient Boolean logic. While most existing works aim to avoid the ID – VG hysteresis in NCFETs, this paper exploits this hysteresis feature for logic-memory synergy and presents a custom-designed nonvolatile NCFET D flip-flop (DFF) that maintains its state during power outages. This paper also presents an NCFET fabricated for this purpose, showing <10 mV/decade steep hysteresisedges and high, up to seven orders inmagnitude, R\text {DS} ratio between the two polarization states. With a device-circuit codesign that takes advantage of the embedded nonvolatility and the high R\text {DS} ratio, the proposed DFF consumes negligible static current in backup and restore operations, and remains robust even with significant global and local ferroelectric material variations across a wide 0.3–0.8 V supply voltage range. Therefore, the proposed DFF achieves energy-efficient and low-latency backup and restore operations. Furthermore, it has an ultralow energy-delay overhead, below 2.1% in normal operations, and operates using the same voltage supply as the Boolean logic elements with which it connects. This promises energy-efficient nonvolatile computing in energy-harvesting and power-gating applications. [ABSTRACT FROM PUBLISHER]

This paper presents a modeling approach to simulate the impact of total ionizing dose (TID) degradation on low-power analog and mixed-signal circuits. The modeling approach has been performed on 180-nm n-type metal–oxide–semiconductor field-effect transistors (n-MOSFETs). The effects of the finger number, channel geometry, and biasing voltages have been tested during irradiation experiments. All Berkeley short-channel insulated gate field-effect transistor model (BSIM) parameters relevant to the transistor properties affected by TID have been modified in an algorithmic flow to correctly estimate the sub-threshold leakage current for a given dose level. The maximum error of the model developed is below 8%. A case study considering a five-stage ring oscillator is simulated with the generated model to show that the power consumption of the circuit increases and the oscillation frequency decreases around by 14%. [ABSTRACT FROM AUTHOR]

In this paper, we develop an explicit model to predict the dc electrical behavior in ultrathin surrounding gate junctionless (JL) nanowire field-effect transistors (FETs). The proposed model considers 2-D electrical and geometrical confinements of carrier charge density within few discrete subbands. Combining a parabolic approximation of the Poisson equation, the first-order perturbation theory for the Schrödinger subband energy eigen-values and the Fermi–Dirac statistics for the confined carrier density lead to an explicit solution of the dc characteristic in ultrathin JL devices. Validity of the model has been verified with technology computer-aided design simulations. The results confirm its validity for all regions of operation, i.e., from deep depletion to accumulation and from linear to saturation. This represents an essential step toward analysis of circuits based on JL nanowire devices. [ABSTRACT FROM AUTHOR]

Silicon nanowire (SiNW) field-effect transistors (SiNWFETs) are of great potential as a high-sensitivity charge sensor. The signal-to-noise ratio (SNR) of an SiNWFET sensor is ultimately limited by the intrinsic device noise generated by carrier trapping/detrapping processes at the gate oxide/silicon interface. This carrier trapping/detrapping-induced noise can be significantly reduced by replacing the noisy oxide/silicon interface with a Schottky junction gate (SJG) on the top of the SiNW. In this paper, we present a tri-SJG SiNWFET (Tri-SJGFET) with the SJG formed on both the top surface and the two sidewalls of the SiNW so as to enhance the gate control over the SiNW channel. Both experiment and simulation confirm that the additional sidewall gates in a narrow Tri-SJGFET indeed can confine the conduction path within the bulk of the SiNW channel away from the interfaces and significantly improve the immunity to the traps at the bottom buried oxide/silicon interface. Therefore, the optimal low-frequency noise performance can be achieved without the need for any substrate bias. This new gating structure holds promises for further development of robust SiNWFET-based charge sensors with low noise and low operation voltage. [ABSTRACT FROM AUTHOR]

Silicon carbide (SiC) has shown substantial promise in the fabrication of high-power devices, and SiC Schottky diodes and field-effect transistors (FETs) have been considered as potential candidates for outerspace and sensors applications. Due to the multipolar structure, SiC gate turn-off thyristor (GTO) device is relatively sensitive to the irradiation-induced point defects. However, how SiC GTO devices perform under neutron irradiation still needs to be clarified. In this paper, the effects of neutron irradiation on the static and dynamic switch characteristics of high-voltage 4H-SiC GTOs are investigated for the first time. For the static electrical properties, it is found that the forward current significantly decreases with the increasing neutron irradiation fluence. While the cathode leakage current in the blocking characteristics shows an insignificant change up to a neutron fluence of ${1.0} \times {10}^{{13}}$ n/cm2. For the switching characteristics, both the pulse peak current and di/dt show substantial reduction as the neutron fluence increases while the delay time increases after irradiation. The degraded performance of the static and dynamic characteristics of SiC GTO devices was then analyzed and attributed to the weakened conductivity modulation and reduced carrier injection efficiency into the drift layer. These two aspects originate from the significantly reduced carrier lifetime and deteriorated forward characteristics of anode-gate diodes, respectively. [ABSTRACT FROM AUTHOR]

In this paper, we present two accurate physics-based models of ballistic metal–oxide–semiconductor field-effect transistors (MOSFETs), both using less than ten parameters. These models—the capacitor model and the virtual source model—are based on the Landauer–Büttiker formalism. We show that the nonthermalization of charge carriers in the channels of ballistic MOSFETs leads to two critical effects that need to be considered in the modeling: the ballistic drain-induced barrier lowering (DIBL) effect and the floating source effect. The ballistic DIBL effect is responsible for a drain voltage dependence of the DIBL parameter; the floating source effect intensifies the injection of high-energy carriers from the source as the gate voltage increases. Specifically, the analysis is carried out on devices composed of monolayer black phosphorus, a 2-D semiconductor with unique electronic and mechanical properties, which make it a promising candidate for 2-D digital logic applications. [ABSTRACT FROM AUTHOR]

Electrolyte-gated, printed field-effect transistors exhibit high charge carrier densities in the channel and thus high on-currents at low operating voltages, allowing for the low-power operation of such devices. This behavior is due to the high area-specific capacitance of the device, in which the electrolyte takes the role of the dielectric layer of classical architectures. In this paper, we investigate intrinsic double-layer capacitances of ink-jet printed electrolyte-gated inorganic field-effect transistors in both in-plane and top-gate architectures by means of voltage-dependent impedance spectroscopy. By comparison with deembedding structures, we separate the intrinsic properties of the double-layer capacitance at the transistor channel from parasitic effects and deduce accurate estimates for the double-layer capacitance based on an equivalent circuit fitting. Based on these results, we have performed simulations of the electrolyte cutoff frequency as a function of electrolyte and gate resistances, showing that the top-gate architecture has the potential to reach the kilohertz regime with proper optimization of materials and printing process. Our findings additionally enable accurate modeling of the frequency-dependent capacitance of electrolyte/ion gel-gated devices as required in the small-signal analysis in the circuit simulation. [ABSTRACT FROM AUTHOR]

A physics-based threshold voltage model of junction-less (JL) double gate (DG) FETs with vertical structural and doping asymmetry is being proposed in this paper. The numerical implementation of vertical asymmetric doping in the FET devices modeling has been studied extensively. A linear approximation, as suggested in the post-annealed implantation technique, is introduced to account for asymmetric-doped profile falling within the channel thickness. Furthermore, Bhaskar’s approximation of sinusoidal has been implemented in the solution to impart due accuracy in the modeling overextended range of device parameters. Overall, appropriate implementation of these mathematical techniques has reduced the complexity of the full evanescent mode analysis immensely and has together retained the accuracy in the solution. The simplicity of the model has provided flexibility to study structural and doping asymmetry together for JL DG FET. Synopsys Sentaurus Device simulation tool has been used for verification of the model results. [ABSTRACT FROM AUTHOR]

Self-heating in fully depleted silicon-on-insulator (FDSOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) is experimentally studied using the gate resistance thermometry technique, in a wide temperature range from 300 down to 4.2 K. We demonstrate that below 160 K, the channel temperature increase ($\Delta {T}$) due to self-heating starts to deviate significantly from the linear variation with the dissipated power, leading to an apparent power dependent thermal resistance. This power dependence is interpreted in terms of temperature dependent thermal conductivity. The thermal resistance dependence on the active device temperature (${T}_{\text {Device}}$) indicates that the former one is mainly driven by the thermal conductivity of the oxide layer. Moreover, based on this dependence we reconstructed the channel temperature increase for each dissipated power and ambient temperature, and we found that the calculated values were in a good agreement with the experimental ones. Results indicate that even at low temperatures, thermal resistance does not depend significantly on the silicon channel thickness (ranging from 7 up to 24 nm), whereas the buried-oxide thinning (145 and 25 nm) strongly reduces the magnitude of the thermal resistance. Finally, this paper intends to fill the gap of experimental data concerning self-heating in advanced FDSOI transistors at low temperatures, revealing limitations and perspectives that should be taken into account for future work. [ABSTRACT FROM AUTHOR]

FETs made on 2-D semiconductors, typically without degenerate doping at the contacts, have a significant Schottky junction (SJ) resistance, which complicates transistor analysis. This paper evaluates the effect of the contact resistance on the 2-D-material FET characteristics through four-terminal (4-T) resistance measurements on WSe2 FETs, which allow studying the channel and contacts characteristics separately. Apart from showing the nonnegligibility of contact resistance, this paper enables a finer understanding of commonly observed phenomena, such as transistor performance improvement with dielectric-encapsulation is observed to have a stronger effect on the contact than the channel; the resistance of the forward-biased SJ is observed to be not negligible, but comparable to that of the reverse-biased junction; at biases commonly referred to as “low-bias,” the WSe2 FET resistance could be dominated by the contacts; and pinchoff can be observed at relatively lower current levels, being related to the channel-contact resistance ratio rather than their magnitudes. In the devices where true channel pinchoff can be verified, a correlation emerges between current saturating behavior and asymmetry in the output characteristics with respect to the drain–source bias polarity, a feature that may serve as a guide toward interpreting standard FET output characteristics in 2-D materials. [ABSTRACT FROM PUBLISHER]

As dimension of bulk Si field-effect transistors scales down, novel techniques for impurity profile design at channel area are required because suppression of short-channel effects and improvement of on-state current is tradeoff in conventional ion implantation process. In this paper, we demonstrate p-type bulk Si fin field-effect transistors by using solid-source doping for better impurity profile in fin to weaken the tradeoff between suppression of short-channel effects and improvement of on-state current. In this paper, impurity profiles in fin with two different kinds of anneal conditions after fin revelation (1000 °C 30 s and 1050 °C spike) are analyzed, and the better impurity profile at channel area is designed by 1000 °C 30-s anneal for better electrical characteristics. The anneal condition with the better impurity profile in fin showsmobility improvement at long gate length ( 1~\mu \textm ) and short gate lengths (60, 70, and 80 nm); subthreshold slope and transconductance are improved at the same time. With those results, we conclude that a fabrication process flow of p-type bulk Si fin field-effect transistors to weaken the tradeoff between suppression of short-channel effects and improvement of on-state current is established with 1000 °C 30-s anneal after fin revelation by using solid-source doping. At the same time, electrical characteristics variation is also suppressed in the case of 1000 °C 30-s anneal. [ABSTRACT FROM AUTHOR]

Black phosphorus (BP) has arisen as the preferred material with great applications in electronics devices. Nanoinvestigation of the thermal properties and thermal stability of BP transistors at the nanoscale is extremely challenging. This paper reports nanothermal investigation of BP MOSFET transistors, using the dual-phase-lagging (DPL) model including the phonon scattering. The thermal properties of the BP including the thermal conductivity and volumetric heat generation rate considered depend on the temperature. The results are compared with those obtained from the classical silicon MOSFET. Using the finite-element method, we have demonstrated that the temperature variation of the BP MOSFET does not exceed 305 K instead of 319 K in the case of a classical MOSFET. This paper not only exposes various novel properties of BP transistors, but also demonstrates the great usefulness of the BP transistors. [ABSTRACT FROM PUBLISHER]

The susceptibility of conventional silicon p-channel MOS transistors to negative bias temperature instabilities (NBTIs) is a serious threat to further device scaling. One possible solution to this problem is the use of a SiGe quantum-well channel. The introduction of a SiGe layer, which is separated from the insulator by a thin Si cap layer, not only results in high mobilities but also superior reliability with respect to NBTI. In part one of this paper, we provide experimental evidence for reduced NBTI by thoroughly studying single traps in nanoscale devices. In this paper, we present detailed TCAD simulations and employ the four-state nonradiative multiphonon model to determine the energetical and spatial positions of the identified single traps. The found trap levels agree with the defect bands estimated in large-area devices. Our conclusions are also supported by the observation of similar activation energies for defects present in transistors of various device geometries. From the calibrated TCAD simulations data, an impressive boost of the time-to-failure for the SiGe transistor can be predicted and explained. [ABSTRACT FROM AUTHOR]

In this paper, a 1-Transitor (1-T) capacitorless dynamic random access memory (DRAM) using bandgap-engineered silicon-germanium Bipolar ionization metal oxide semiconductor field effect transistor (I-MOS) is investigated through numerical simulations. We have demonstrated the application of the proposed Si0.6Ge0.4 Bipolar I-MOS for realization of a 1-T capacitorless DRAM. The proposed device can achieve hysteresis at significantly lower drain voltages ( V\mathrm{LD} =0.45 V to V\mathrm{LU} =1.15 V), in comparison to the inversion mode device ( V\mathrm{LD} = 8 V to V\mathrm{LU} =11 V). In addition, the proposed 1-T capacitorless DRAM exhibits a wider hysteresis window ( \Delta \textV ) of the order ~700 mV and a sensing margin ( \Delta \textI ) of ~5 orders in comparison to the inversion mode based 1-T capacitorless DRAM. Moreover, the proposed 1-T capacitorless DRAM exhibits the retention time of ~750 msec and ~320 msec for T = 25 °C and T = 85 °C, respectively. The proposed 1-T capacitorless DRAM also shows nondestructive read and an extreme long-term endurance. Therefore, the results presented in this paper can provide an opportunity for future DRAM design in deep nanometer technology. [ABSTRACT FROM PUBLISHER]

An analytical model for junctionless double-gate FETs (JLDGFETs) in the subthreshold region is proposed in this paper. As the analytical models based on Young’s approximation demonstrate certain limitations due to the heavily doped channel of the JLDGFET, it is essential to model the electrical characteristics of a JLDGFET using alternative methods. Therefore, in this paper, by using the Fourier series and Green’s function, the potential distribution ( \phi ( {x} , {y} )) in the channel is solved, and the hot-carrier effects and random dopant fluctuation are modeled using localized trap charges and macroscopic analysis. Using the calculated \phi (x, y), {I} _{{\mathsf {DS}}} and {V} _{{\mathsf {th}}} are solved analytically with respect to various L and t {\mathsf {ox}} variations, subthreshold swing, the drain-induced barrier lowering, the localized trap charges, and a single impurity dopant. All results from the analytical model are verified through comparisons with commercially available 2-D ATLAS numerical simulation results. [ABSTRACT FROM PUBLISHER]

Superjunction has arguably been the most creative and important concept in the power device field since the introduction of the insulated gate bipolar transistor (IGBT) in the 1980s. It is the only concept known today that has challenged and ultimately proved wrong the well-known theoretical study on the limit of silicon in high-voltage devices. This paper deals with the history, device and process development, and the future prospects of Superjunction technologies. It covers fundamental physics, technological challenges as well as aspects of design and modeling of unipolar devices, such as CoolMOS. The superjunction concept is compared to other methods of enhancing the conductivity of power devices (from bipolar to employment of wide-bandgap materials) to derive its set of benefits and limitations. This paper closes with the application of the superjunction concept to other structures or materials, such as terminations, superjunction IGBTs, or silicon carbide Field Effect Transistors (FETs). [ABSTRACT FROM AUTHOR]

In this paper, we systematically examined the impact of fin height ( H\mathrm{ Fin} ) and fin angle ( \theta \mathrm{ Fin} ) on the ac performance parameters including total gate capacitance ( C\mathrm{ gg} ), RC delay ( C_{\mathrm{ gg}}V_{\mathrm{ DD}}/I_{\mathrm{\scriptscriptstyle ON}} ), cutoff frequency ( f_{T} ), energy ( E ), total power ( P_{\mathrm{ Total}} ), and leakage power ( P_{\mathrm{ Leakage}} ) of hybrid FinFETs at the supply voltage, V\mathrm{ DD} with on-current I\mathrm{\scriptscriptstyle ON} . The RC delay, energy, and total power consumption are the primary factors limiting the operating frequency of the high-performance devices. Therefore, these electrical parameters are needed to be addressed in the architectural level of the fin based devices. In this paper, a calibrated numerical device simulation tool is used to achieve the best device performances of 14-nm hybrid FinFETs. From the simulated current–voltage ( I – V ) and capacitance–voltage ( C – C\mathrm{ gg}V\mathrm{ DD}/I\mathrm{\scriptscriptstyle ON} , fT , CV2, P\mathrm{ Total} , and P\mathrm{ Leakage} are extracted to analyze the effect of H\mathrm{ Fin} and \theta \mathrm{ Fin} on the performance matrices of these devices. In addition, this paper proposes an optimum structural configuration for 14-nm hybrid FinFET architecture for digital application perspective. [ABSTRACT FROM AUTHOR]

This paper examines the fundamental reliability differences between n-p-n and p-n-p SiGe HBTs. The device profile, hot carrier transport, and oxide interface differences between the two device types are explored in detail as they relate to device reliability. After careful analysis under identical electrical stress conditions for n-p-n and p-n-p, the differences in activation energies for the damage of the oxide interfaces of the two devices is determined to be the primary cause for accelerated degradation seen in p-n-p SiGe HBTs. An analytical model has been adapted for simulating these aging differences between p-n-p and n-p-n devices. This paper has significant implications for predicting the degradation of complementary SiGe HBTs and even engineering future generations with well-matched n-p-n and p-n-p device-level reliability. [ABSTRACT FROM PUBLISHER]

In this paper, we propose a novel dual-metal gate-stack (DMSG) architecture with HfO2 spacer for scaling the nanowire FETs (NWFETs) to the sub-10-nm regime. We demonstrate that the electric field at the channel–drain extension interface is reduced when the inbuilt electric field arising due to a difference in the work function at the interface of the two metals in the DMSG is coupled to the nanowire through the fringing fields through the HfO2 spacer. The reduction in the electric field leads to a larger tunneling width, and therefore suppresses the lateral band-to-band-tunneling component of the gate-induced drain leakage in the DMSG NWFETs. Although the gate capacitance increases in the DMSG NWFETs due to the fringing fields, this paper demonstrates that the increase in the intrinsic delay (~1.5 times) is not very significant to degrade the circuit performance drastically. Using calibrated 3-D simulations, we show that the off-state current is reduced by more than five orders of magnitude in the DMSG NWFETs, leading to a significantly high on-state to off-state current ratio of ~106 even when the channel length is scaled to 7 nm. [ABSTRACT FROM PUBLISHER]

Tunnel FETs (TFETs) have been identified as the most promising steep slope devices for ultralow power logic circuits. In this paper, we demonstrate in-plane InAs/Si TFETs monolithically integrated on Si, using our recently developed template-assisted selective epitaxy approach. These devices represent some of the most scaled TFETs with dimensions of less than 30 nm, combined with excellent aggregate performance with average subthreshold swing (SS), of around 70 mV/decade combined with I\mathrm{\scriptscriptstyle ON} of a few \mu \textA / \mu \textm for |V\mathrm {\mathbf {DS}}| = |V\mathrm {\mathbf {GS}}| = 0.5 V. Here, we will discuss the device fabrication as well as the experimental electrical data. Extensive low temperature characterization and activation energy analysis is used to gain insights into the factors limiting device performance. Combined with the simulation study presented in part 2 of this paper, this will elucidate how traps are ultimately limiting the SS. [ABSTRACT FROM AUTHOR]

An electrostatic nonuniformity in the cantilever vertical tunneling FETs intrinsically exists in the InAs/GaSb junction to InAs cantilever transition region. The effects of the coupling ratio (CR) nonuniformity are investigated in this paper. The results show that the switching characteristics are degraded by the CR nonuniformity, especially in the case of large InAs/GaSb band offset. This paper also reveals that the nonuniformity in InAs/GaSb vertical tunneling FETs can be mitigated with the optimized band offset of heterojunction, scaling of oxide thickness, and acute angle etching profile. [ABSTRACT FROM AUTHOR]

In this paper, the structural and material optimization of gate sidewall spacer in the perspective of OFF-state leakage current was performed in a 3-nm node nanoplate FET (NPFET). Gate-induced drain leakage (GIDL) current, a dominant factor of OFF-state leakage current, and active performance (ON-current, ON/OFF current ratio, and dynamic performance) were co-optimized according to the structural correlation of gate sidewall spacer with other structural components such as gate, source, and drain length. By optimizing the structure for gate and spacer, intrinsic delay was improved by 9.8%, GIDL current was reduced by ~78%, and then on/off current ratio (${I}_{\mathrm{\scriptscriptstyle ON}}/{I}_{\mathrm{\scriptscriptstyle OFF}})$ was enhanced by 4.2 times. On-current (${I}_{\mathrm{\scriptscriptstyle ON}}$) according to contact resistance (${R}_{\text {con}}$) and dynamic performance was analyzed in relation to source/drain (S/D) and spacer. Consequently, the intrinsic delay was improved by 10% and GIDL current reduced by about 92%, which enhanced ${I}_{\mathrm{\scriptscriptstyle ON}}/{I}_{\mathrm{\scriptscriptstyle OFF}}$ by 7.9 times accordingly. Furthermore, by comparing structural relations between gate spacer and S/D spacer, a better structural optimization method was proposed. [ABSTRACT FROM AUTHOR]

In this paper, an analytical model has been proposed to evaluate the effect of temperature on gate-induced drain leakages (GIDL) in a dual-metal nanowire field-effect transistor. Surface potential, electric field ${E} _{z}$ , and GIDL current ${I}_{\text {GIDL}}$ have been formulated and analyzed by solving 2-D Poisson’s equation with appropriate boundary conditions. The calefaction effect has also been inspected for potential and hole concentration contour plot along with in depth analysis of conduction band energy and valence band energy. Drain-induced barrier lowering and electron velocity have also been examined. Furthermore, the effect of temperature on ${g} _{m}$ , ${g} _{d}$ , noise figure, and noise conductance has also been examined. [ABSTRACT FROM AUTHOR]

In this paper, an improved 4H-SiC U-shaped trench-gate metal–oxide–semiconductor field-effect transistors (UMOSFETs) structure with low ON-resistance (${R}_{ \mathrm{\scriptscriptstyle ON}}$) and switching energy loss is proposed. The novel structure features an added n-type region, which reduces ON-resistance of the device significantly while maintaining the breakdown voltage (${V}_{\textsf {BR}}$). In addition, the gate of the improved structure is designed as a p-n junction to reduce the switching energy loss. Simulations by Sentaurus TCAD are carried out to reveal the working mechanism of this improved structure. For the static performance, the ON-resistance and the figure of merit (FOM $= {V}_{\textsf {BR}}^{\textsf {2}}/{R}_{ \mathrm{\scriptscriptstyle ON}}$) of the optimized structure are improved by 40% and 44%, respectively, as compared to a conventional trench MOSFET without the added n-type region and modified gate. For the dynamic performance, the turn-on time (${T}_{ \mathrm{\scriptscriptstyle ON}}$) and turn-off time (${T}_{ \mathrm{\scriptscriptstyle OFF}}$) of the proposed structure are both shorter than that of the conventional structure, bringing a 43% and 30% reduction in turn-on energy loss and total switching energy loss (${E}_{\mathbf {SW}}$). [ABSTRACT FROM AUTHOR]

Bias temperature stress instability on multilayered MoS2 FETs was systematically investigated with the device scheme encapsulated with amorphous fluoropolymers [cyclized transparent optical polymer (CYTOP)] for the secure of minimization of external gas ambient effects. Large threshold voltage shifts ($\Delta {V}_{\textsf {th}}$) for the negative bias temperature stress (NBTS) were observed, compared to the positive bias temperature stress (PBTS). Herein, the asymmetry behaviors on $\Delta {V}_{\textsf {th}}$ , observed in this paper, are ascribed to the sulfur vacancy in MoS2 layers, leading to large hole traps compared to electron traps in MoS2 layers. Moreover, high-temperature-sensitivity [ ${d}$ ($\Delta {V}_{\textsf {th}}$)/ dT] on $\Delta {V}_{\textsf {th}}$ for PBTS than NBTS was observed, and their origins are possibly due to synergetic effects associated with large trap energy distribution (${k}_{o}{T}$) for electron trap levels. [ABSTRACT FROM AUTHOR]

Using TCAD simulations, the silicon carbide metal–oxide–semiconductor field-effect transistor with p-type floating islands (SiC FLIMOSFET) is systematically investigated in this paper. The doping concentration (NFLI), length (L), and position (D1) of floating islands are optimized according to breakdown voltage (BV), electric field distribution, and on-resistance. The results show that $\text{N}_{\textsf {FLI}} = \textsf {1} \times \textsf {10}^{\textsf {17}}$ cm $^{\textsf {-3}}, \textsf {L}= \textsf {2.5}\,\,\mu \text{m}$ , and $\textsf {D1}=9.0\,\,\mu \text{m}$ are superior values for FLI structure considering tradeoff between BV and on-resistance. With the same BV capacity, the on-resistance of SiC FLIMOSFET is decrease by 32% comparing to the conventional SiC VDMOSFET. Besides, the dynamic property shows 16.5% reduction of FoM $\text{R}_{\textsf {on}}\cdot \textsf {Q}_{\textsf {GD}}$ in the SiC FLIMOSFET. Significantly, comparing to the conventional structure, the electro-thermal simulation indicates that the SiC FLIMOSFET has a higher robustness under short-circuit condition owing to the reduction of thermal stress in SiC/SiO2 interface. All the results show that the SiC FLIMOSFET has a good potential in SiC power device. [ABSTRACT FROM AUTHOR]

In this paper, a post superacid (SA) treatment was proposed to enhance the performance of InAs FinFETs on SiO2/Si substrates. Typically, the subthreshold swing (SS) has reduced from 217 to 170 mV/decade and the transconductance (${g}_{m}$) has increased from 6.44 to 26.5 $\mu \text{S}/\mu \text{m}$ after SA treatment. It was found that the interfacial In2O3 at the InAs/ZrO2 interface was effectively reduced after SA treatment due to the strong protonating nature of the SA solution. As a result, the interface trap density was reduced leading to a pronounced reduction of sheet resistance after SA treatment. The modeling of transfer characteristics indicates that the carrier mobility is enhanced by 5.8~7.1 folds after SA treatment due to interfacial traps reduction. The results suggest that SA treatment can be potentially extended to other III–V MOSFETs to enhance the device performances. [ABSTRACT FROM AUTHOR]

A scheme for precisely adjusting the drive strength of an inserted-oxide FinFET (iFinFET) comprising two nanowire (NW) channel regions that are separated by a thin oxide layer, to enhance the manufacturing yield of a minimally sized six-transistor static random access memory (6T-SRAM) cell, is investigated in this paper. The 3-D process simulations show that the upper NW channel region can be selectively rendered nonconducting by dopant ion implantation followed by thermal annealing so that its threshold voltage is greater than the supply voltage (${V}_{\text {DD}}$). Furthermore, the position of the inserted-oxide layer can be adjusted to balance the tradeoff between the read stability and write-ability to achieve the lowest minimum cell operating voltage (${V}_{\text {min}}$). Using a compact transistor model calibrated to 3-D device simulations, doped iFinFET technology is projected to enable ${V}_{\text {min}}$ of a minimally sized 6T-SRAM cell to be substantially lower than ${V}_{\text {DD}}$ , eliminating the need for write-assist circuitry and lowering power consumption. [ABSTRACT FROM AUTHOR]

This paper examines metal–ferroelectric–insulator–semiconductor negative-capacitance FinFET (NC-FinFET) based VLSI subsystem-level logic circuits. For the first time, with the aid of a short-channel NC-FinFET compact model, we confirm the functionality and evaluate the standby-power/switching-energy/delay performance of large logic circuits (e.g., dynamic 4-bit Manchester carry-chain adder and the formal hierarchical 32-bit carry-look-ahead adder) employing 14-nm ultra-low-power NC-FinFETs. Our study indicates that the inverse Vds-dependence of threshold voltage (VT), also known as the negative drain-induced barrier lowering, of negative-capacitance field-effect transistor is not only acceptable but also beneficial for the speed performance of both the static and pass-transistor logic (PTL) circuits, especially for the PTL at low VDD. [ABSTRACT FROM AUTHOR]

In this paper, we show that MoS2 multilayers have mechanical and electrical properties that qualify them as promising channel materials for an n-type piezoelectric FET (PZ-FET). We present extensive density functional theory calculations to investigate the effects of a compressive, out-of-plane stress on MoS2 monolayers and multilayers and extract the corresponding stiffness, as well as the sensitivity to stress of the conduction and valence band edge, and of the effective masses. Then, we use these material properties and a top-of-the-barrier ballistic transistor model to evaluate numerically the ${I}_{\textsf {DS}}$ versus ${V}_{\textsf {G}}$ characteristics of n-type PZ-FETs with an MoS2 channel material. Our results indicate that MoS2 multilayers are the best material option for n-type PZ-FETs, which can reach a subthreshold swing of about 40 mV/decade for a 5-nm-thick piezoelectric layer. This is because the weak interlayer van der Waals bonding makes the conduction band edge in MoS2 multilayers very sensitive to vertical compressive stress. The simulated MoS2 PZ-FETs exhibit large ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratios at low voltage and have better subthreshold steepness compared with the counterpart device employing a 3-D semiconductor. [ABSTRACT FROM AUTHOR]

In this paper, we propose and simulate a charge-plasma (CP)-based dielectrically modulated (DM) source-engineered Schottky barrier field-effect transistor (SE-SB-FET) as a device for biomolecule sensing. The proposed device employs metal silicide (ErSi1.7) as source/drain regions and Hafnium (workfunction = 3.8 eV) as dual metallic source extensions. The oxide below the source extensions are etched out to create two horizontal L-shaped nanogap cavities for biomolecule detection. The presence of biomolecules is characterized by the change in dielectric constants and the associated charge densities, which, in turn, modulates the Schottky barrier (SB) width at the source-channel (metal/Si) junction, owing to the formation of an electron-CP in an undoped-Si film. A comparative analysis of the SE-SB-FET and the conventional DM-FET in terms of sensitivity has been performed as a function of dielectric constant (${K}$) and the associated charge density ($\rho $), along with the thickness (${T}_{\textsf {C}}$) and the length (${L}_{\textsf {C}}$) of the cavity. Furthermore, calibrated simulations reveal that the relative change in ${I}_{ \mathrm{\scriptscriptstyle ON}}$ (sensing parameter herein calculated at ${V}_{\textsf {GS}}={V}_{\textsf {DS}}={1}$ V) in SE-SB-FET is much better (maximum of ${3}\times $ for neutral; ${2.9} \times $ for charged biomolecules at $\rho =-{1}\times {10}^{{11}}$ cm $^{-{2}}$). We further observe a significant improvement in sensitivity at low temperature ($25\times $ at ${K}={5}$ ; $\rho ={0}$ at 100 K). Thus, SE-SB-FET biosensor provides better sensing capability for biomolecule detection when compared to the conventional DM-FET biosensor. [ABSTRACT FROM AUTHOR]

Fin field-effect transistor (FinFET) scaling beyond the 10-nm node requires formation of a junction isolation region between the source and the drain to suppress sub-fin leakage current. In this paper, heavy species such as Sb and As were implanted at room temperature to form a punch-through stop (PTS) layer in ${n}$ -Ge substrates. The impact of PTS implants on channel doping and defects, as well as junction leakage, was investigated for bulk Ge ${p}$ -FinFET applications. We report retrograde doping profiles with a low surface (channel) dopant concentration of 4–5 $\times 10^{\textsf {16}}$ cm−3 for Sb PTS implants post 550 °C and 650 °C activation anneals. Besides achieving low effective channel doping, the 650 °C high-temperature activation anneal post PTS implant also helps in the reduction of channel defect density. Furthermore, low junction leakage currents are also demonstrated for Sb and As PTS implants with 550 °C and 650 °C activation anneals. To avoid damaging the FinFET channel layer due to PTS ion implantation, Ge homoepitaxy was also studied post Sb PTS implants. However, Sb PTS implants activated at 650 °C without Ge epitaxy exhibit the best results in terms of low channel dopant and defect concentrations, besides junction leakage. [ABSTRACT FROM AUTHOR]

In this paper, we develop an accurate analytical electrostatic potential model for both the n-type and p-type double-gate heterostructure tunnel field-effect transistors (H-TFETs). We solve the Poisson’s equation in four distinct regions inside the device, the depletion regions of the source, channel, and drain, and the drift-diffusion region of the channel, where the mobile charge carriers should be taken into account. It is shown that the model predicts the electrostatic potential profile of the various heterostructure devices with different material systems in all regions of the device operation accurately. The potential model is used for developing a model for the tunneling distance at the given energy level. Due to the physical nature of the models, the influence of the transistor parameters on the electrostatic characteristics of H-TFETs with desired heterojunction materials may be easily pursued. We show that the model results accurately predict the numerical simulation results for different device parameters. [ABSTRACT FROM AUTHOR]

A new 500-V ON-state breakdown voltage (ON-BV) parasitic JFET is proposed in this paper. Compared with traditional structures, a special junction field-effect transistor (JFET) region is located at the edge of the LDMOS. The drift region length of the JFET is larger than that of the LDMOS region. When JFET works in high-voltage on-state, the carriers are separated from the LDMOS region by a transition region close to the JFET region. Then the peak electric field and the impact ionization rate are suppressed. It helps the device to achieve the high ON-BV. Experimental results show that the ON-BV of the proposed structure is larger than 500 V, which is far larger than that of the traditional structures. In addition, the OFF-state breakdown voltage is 550 V. [ABSTRACT FROM AUTHOR]