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Ferroelectric and negative-capacitance field-effect transistors (FeFETs and NCFETs) have recently garnered great attention as devices for applications in memory and low-power logic, respectively. As these technologies are pursued, it is critical to have a variety of measurement approaches, including methods familiar to the electron-device and microwave communities that can aid in fully understanding the behavior of ferroelectrics in FeFETs and NCFETs. In this paper, we propose and show the viability of using frequency-domain electrical measurement techniques employing the well-known microwave S-parameters, and their large-signal generalization and X-parameters. Our methods provide the means to trace the intrinsic polarization versus electric-field curve of the ferroelectric, i.e., with the parasitics de-embedded, thereby showing the innate ferroelectric response, which cannot be done using conventional techniques. These methods also enable extraction of all the parameters of the Landau–Khalatnikov equation, which is commonly used to model ferroelectric behavior in FeFETs and NCFETs. This paper hence takes a useful step toward methods familiar to the electron-device community that can help to better understand and optimize FeFET and NCFET technologies. [ABSTRACT FROM AUTHOR]

To effectively solve the crosstalk issue in high-density crossbar array (CBA), high rectifying characteristics should be introduced in the resistance random-access memory (ReRAM) device, and in-depth understanding of the affecting factors on rectifying properties is essential for the large-scale application of ReRAM. In this paper, a high-performance self-rectifying device with CMOS compatible Pd/HfO2/TaOx/Ta structure was demonstrated in a 1-kb CBA. Forming-free, self-compliance, and high uniformity characteristics were successfully achieved. By modulating the thickness of the HfO2 rectifying layer, the rectifying ratio of device could be achieved as high as $\sim 2\times 10^{\textsf {3}}$ under ±3 V at low-resistance state (LRS). It was also experimentally confirmed that the selected unit cell in high-resistance state (logically the “ OFF” state) was stably readable when it was surrounded by unselected LRS (logically the “ ON” state) cells, in an array of up to $32 \times 32$ cells. Furthermore, a model based on interfacial barrier modulation and defects trapping/detrapping was proposed to elucidate the impact of the dielectric thickness on the self-rectifying characteristics of the device. The results presented in this paper provide a great potential for selector-free high-density memory applications. [ABSTRACT FROM AUTHOR]

Magnetic tunnel junctions (MTJs) with low switching current, high thermal stability, and small device size are strongly preferred for low-power, high-reliability, and high-density spintronic memory and logic applications. The research of MTJs from shape in-plane magnetic anisotropy to interfacial perpendicular magnetic anisotropy (i-PMA) has successfully paved the way down to 20-nm scale, below which, however, the i-PMA approach reaches a physical limit in sustaining sufficient thermal stability while achieving low-power spin transfer torque switching. Recently, studies have been reported a new approach to pave the way toward sub-10-nm MTJs satisfying the requirements by revisiting shape perpendicular magnetic anisotropy (s-PMA). In this paper, we present a compact model of the sub-10-nm s-PMA MTJ device, which captures both the static and dynamic physical behaviors. This model is SPICE-compatible for hybrid MTJ/CMOS circuit designs. This paper is expected to push forward the development of sub-10-nm-scale MTJ-based spintronic memory and logic circuits. [ABSTRACT FROM AUTHOR]

In this paper, the NbOx, which was regarded as a promising material based on its insulator–metal transition (IMT) effects, was applied as the switching layer of the device. The threshold switching characteristics were comprehensively investigated with particular emphasis on temperature dependence. The conduction mechanism for high-resistance state (HRS) was fitted and verified to be Schottky emission. With the increase in temperature, the fitting results demonstrated that the Schottky barrier decreased, leading to a reduction in the resistance of HRS. Furthermore, according to Fourier’s law of heat conduction, the fluctuation range of temperature was smaller, causing a narrow distribution of the threshold voltage as the operating temperature increased. In addition, the increasing temperature caused high energy of electrons, which would induce an IMT more easily, leading to a lower threshold voltage. This paper provided the promise for improving the thermal stability of selected devices. [ABSTRACT FROM AUTHOR]

In-memory computing architecture is an emerging revolutionary computing paradigm that can break the von Neumann bottleneck. Computing methodology and circuit codesign using the CMOS compatible 1T1R resistive random access memory (RRAM) integration structure is presented in this paper. Functionally complete Boolean logic and arithmetic functions are experimentally demonstrated. With a single 40-nm CMOS process 1T1R unit, each of the 16 binary logics can be realized in two logic steps with an additional readout step for cascading, which shows functional reconfiguration and low computational complexity. Up to 107 cycles of NAND and XOR logic operations are performed to validate the correctness and reliability. Moreover, several fundamental adder circuits are designed and experimentally demonstrated in 1T1R devices as the proof of concept of the 1T1R computing architecture. The adders proposed in this paper include a ripple-carry adder and its optimized design and a carry-select adder, which all show promising advantages in nonvolatility, computation speed, and circuit area. This paper reports the most complex yet efficient RRAM-based 8-bit addition function experimentally so far and lays a solid foundation for constructing the future in-memory computing architecture. [ABSTRACT FROM AUTHOR]

The introduction of metal nanocrystals (NCs) has been confirmed to improve electrical uniformity of oxide-based resistive random access memory (RRAM) devices significantly; however, the current reports do not systematically elucidate the relationship between the size/distribution of NCs and the electrical uniformity of RRAM devices. In this paper, we focused on the impact of metal NCs size and areal density on the resistive switching (RS) performances of oxide RRAM by atomic layer deposition (ALD) based on the experimental results and theoretical calculation. The dependence of ALD cycles of 50–130 during Pt or CoPtx NCs growth on the RS parameters of Al2O3 or HfO2 memory units has been evaluated systematically. The RRAM embedded Pt or CoPtx NCs shows the trends: with increasing ALD cycles, the forming voltage, set/reset voltage, the resistance in off and on state, and ${R}_{ \mathrm{\scriptscriptstyle OFF}}/{R}_{ \mathrm{\scriptscriptstyle ON}}$ ratio entirely first decrease, then flatten, and increase later with a minimum value at about 100 cycles. Although all metal NCs with various sizes enhance the electric field strength compared to at the planar region, only metal NCs with proper NCs size and areal density (9 nm/6– $10\times 10^{\textsf {11}}$ /cm2 in this paper) can effectively produce stronger localized electric field at the tip of metal NCs, leading to optimal RS behavior. [ABSTRACT FROM AUTHOR]

Negative capacitance FETs (NCFETs) have attracted significant interest due to their steep-switching capability at a low voltage and the associated benefits for implementing energy-efficient Boolean logic. While most existing works aim to avoid the ID – VG hysteresis in NCFETs, this paper exploits this hysteresis feature for logic-memory synergy and presents a custom-designed nonvolatile NCFET D flip-flop (DFF) that maintains its state during power outages. This paper also presents an NCFET fabricated for this purpose, showing <10 mV/decade steep hysteresisedges and high, up to seven orders inmagnitude, R\text {DS} ratio between the two polarization states. With a device-circuit codesign that takes advantage of the embedded nonvolatility and the high R\text {DS} ratio, the proposed DFF consumes negligible static current in backup and restore operations, and remains robust even with significant global and local ferroelectric material variations across a wide 0.3–0.8 V supply voltage range. Therefore, the proposed DFF achieves energy-efficient and low-latency backup and restore operations. Furthermore, it has an ultralow energy-delay overhead, below 2.1% in normal operations, and operates using the same voltage supply as the Boolean logic elements with which it connects. This promises energy-efficient nonvolatile computing in energy-harvesting and power-gating applications. [ABSTRACT FROM PUBLISHER]

In this paper, systematic characterization and the corresponding suppression strategies of dynamic OFF-state leakage current (${I}_{ \mathrm{\scriptscriptstyle OFF}}$) in Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) are presented based on fast pulsed ${I}$ – ${V}$ measurement and consecutive switching measurement. It is found that the high ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ under dynamic pulse mode without hole injection is a result of the reduced voltage blocking capabilities (both lateral and vertical) with weaker trapping effect in the buffer, and the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ induced by ON-state hole injection is caused by further increased lateral conductivity through the buffer from source to drain. The corresponding behaviors under continuous waveforms with different switching conditions are analyzed to identify effective approaches for the suppression of dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ in practical switching operations. A higher temperature is shown to be beneficial to the reduction of the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ induced by ON-state hole injection. To completely eliminate the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ caused by ON-state hole injection and minimize the OFF-state power consumption in practical power switching applications, a sufficiently large negative OFF-state gate bias (e.g., ${V}_{\text {GS}, \mathrm{\scriptscriptstyle OFF}}\le -{3}$ V) is recommended in the gate driver turn-off voltage design for the Schottky-type p-GaN gate HEMTs. [ABSTRACT FROM AUTHOR]

Silicon carbide (SiC) has shown substantial promise in the fabrication of high-power devices, and SiC Schottky diodes and field-effect transistors (FETs) have been considered as potential candidates for outerspace and sensors applications. Due to the multipolar structure, SiC gate turn-off thyristor (GTO) device is relatively sensitive to the irradiation-induced point defects. However, how SiC GTO devices perform under neutron irradiation still needs to be clarified. In this paper, the effects of neutron irradiation on the static and dynamic switch characteristics of high-voltage 4H-SiC GTOs are investigated for the first time. For the static electrical properties, it is found that the forward current significantly decreases with the increasing neutron irradiation fluence. While the cathode leakage current in the blocking characteristics shows an insignificant change up to a neutron fluence of ${1.0} \times {10}^{{13}}$ n/cm2. For the switching characteristics, both the pulse peak current and di/dt show substantial reduction as the neutron fluence increases while the delay time increases after irradiation. The degraded performance of the static and dynamic characteristics of SiC GTO devices was then analyzed and attributed to the weakened conductivity modulation and reduced carrier injection efficiency into the drift layer. These two aspects originate from the significantly reduced carrier lifetime and deteriorated forward characteristics of anode-gate diodes, respectively. [ABSTRACT FROM AUTHOR]

Spin-transfer torque magnetic random-access memory (STT-MRAM) based on a single-barrier magnetic tunnel junction (SBMTJ) and a double-barrier magnetic tunnel junction (DBMTJ) has evolved along with a low switching current and low energy consumption to obtain a high areal density and a fast switching speed. The increment of initial temperature, ${T}_{{\text {in}}}$ , in STT-MRAM can achieve low switching energy, ${E}_{{\text {SW}}}$. However, this leads to an unavoidable decrease in $\Delta $ and switching efficiency. In this paper, SBMTJ and DBMTJ were analyzed in terms of the switching efficiency factor with ${E}_{{\text {SW}}}$ reduction by increasing the ${T}_{{\text {in}}}$. The switching temperature, ${T}_{{\text {SW}}}$ , was investigated using a finite-element method simulation. The results show that the DBMTJ(A) and SBMTJ with the same MgO layer thickness of 0.9 nm provide a higher switching current, ${I}_{{\text {C}}}$ , than the DBMTJ(B) with a MgO layer thickness of 1.3 nm. The ${T}_{{\text {SW}}}$ in a DBMTJ(A) is higher than that in an SBMTJ, while ${T}_{{\text {SW}}}$ for a DBMTJ(B) is the smallest because of its low ${I}_{{\text {C}}}$. The DBMTJ(A) and DBMTJ(B) can be applied in a higher temperature range than the SBMTJ at a $\Delta $ of 40. In addition, the STT efficiency factor, $\Delta /{I}_{{\text {C0}}}$ , for a DBMTJ is better than the factor for an SBMTJ. Although the temperature increment would cause an undesirable reduction in $\Delta $ , it can reach a low ${E}_{{\text {SW}}}$ for the requirement of a fast write access time. Therefore, the control device for increasing the ${T}_{{\text {in}}}$ in the MTJs is attractive and should be promoted in the advancement of memory technology. [ABSTRACT FROM AUTHOR]

Ferroelectric (FE) materials are being studied for a variety of applications in memory, logic, and neuromorphic computing, for which predictive models of FE polarization are essential. In this paper, we present a Monte Carlo simulation framework capable of predicting the dynamic, history-dependent response of an FE under arbitrary input waveforms. The simulation is developed by generalizing the physics-based nucleation-limited switching model for polarization reversal in a polycrystalline FE. Measured polarization reversal data from fabricated FE Hf0.5Zr0.5O2 capacitors are used to extract the statistical distribution of FE grains. After parameter extraction, the model is able to predict the dynamics of the FE capacitor without further calibration. Finally, the model is applied to characterize the dynamic response of FE–dielectric bilayer structures and quantify the reduction in memory window due to device variability. [ABSTRACT FROM AUTHOR]

In this paper, the transition rate (TR) from the high-resistance state to the low-resistance state of a HfO2-based resistive random access memory (RRAM) is investigated. The TR is statistically characterized by applying constant voltage stresses in the range from 0.45 to 0.65 V. It is found that TR follows a voltage dependence which closely resembles the one exhibited by metal-insulator-semiconductor / metal-insulator-metal structures when subjected to constant voltage stress, but with remarkably different fitting parameters. This result suggests a common underlying mechanism in both evolutionary behaviors. Furthermore, the investigation provides additional evidence supporting the micro-structural changes in the oxide after the forming step as well as the role played by the atomic species during the SET event. [ABSTRACT FROM AUTHOR]

Stochastic computing (SC) is a promising technology that can be used for low-cost hardware designs. However, SC suffers from its long latency. Although parallel processing can efficiently shorten the latency, duplicated stochastic number generators (SNGs) are necessary, which cause substantial hardware overhead. This paper proposes a scalable SNG based on the spin-Hall-effect (SHE), which is capable of generating multiple independent stochastic streams simultaneously. The design takes advantages of the efficient charge-to-spin conversion from the Spin-Hall material and the intrinsic stochasticity of nanomagnets. Compared to previous spintronic SNGs, the SHE-SNG can reduce the area by $1.6\times -7.8\times $ and the power by $4.9\times -13\times $ while increasing the degree of parallelism from 1 to 16. Compared to CMOS-based SNGs, the proposed SNG obtained $24\times -120\times $ and $53\times $ reduction in terms of area and power, respectively. Finally, three benchmarks were implemented, and the results indicate that SC implementations with the proposed SHE-SNG can achieve $1.2\times -29\times $ reduction of hardware resources compared to implementations with previous CMOS- and spintronic-based designs while scaling the degree of parallelism from 1 to 64. [ABSTRACT FROM AUTHOR]

This paper presents a ternary content-addressable memory (TCAM) cell based on a skewed straintronic magnetotunneling junction (MTJ) switch. A straintronic magnetotunneling junction (s-MTJ) is a three-terminal switch, where the resistance between two of the terminals switches when a potential is applied to the third (gate) terminal that induces strain in the magnetostrictive free-layer. An s-MTJ is a highly energy-efficient switch that would dissipate only ~aJ of energy during switching. This paper discusses a novel variant of s-MTJ, namely skewed s-MTJ (ss-MTJ), where the MTJ switching can be controlled by two gate terminals. The current through an ss-MTJ is minimum when the potentials at the first and second gate terminals ( V2 and V3 , respectively) obey the relation V3 = V2+VF . Here, VF is a fixed voltage (“offset voltage”). Current in an ss-MTJ increases steeply when V2 and V3 deviate from the above “match” condition. This unconventional I – V characteristic of an ss-MTJ is exploited to design a non-Boolean TCAM cell based on just one transistor, one trench capacitor, and one ss-MTJ. We also discuss search and write operations in the ss-MTJ-TCAM cell, and show that the cell requires very small voltages to operate because of the unique I – V characteristics of the ss-MTJ. [ABSTRACT FROM PUBLISHER]

A p-type shield region (p-shield) under the gate trench is typically adopted in a SiC trench MOSFET for achieving a lower oxide field and reverse transfer capacitance ( Crss) . This paper comparatively studies the effects of a grounded p-shield and a floating p-shield. Device simulations using Sentaurus TCAD are carried out in this paper to reveal the devices’ internal dynamics. The floating p-shield can effectively reduce the OFF-state oxide field as a grounded p-shield does, without degrading its static performance. However, after being switched from the OFF-state, the ON-state oxide field in the trench MOSFET with a floating p-shield (FS-MOS) is dramatically elevated. Compared with the trench MOSFET with a grounded p-shield, the FS-MOS also exhibits a higher C{{\text {rss}}} and a consequently slower switching speed. Furthermore, the FS-MOS exhibits a degradation of dynamic R{ \mathrm{ON}} during switching operation. A charge storage mechanism is then presented to explain the dynamics in FS-MOS. Upon a high V{{\text {DS}}} , holes are emitted from the floating p-shield when the parasitic p-n-p structure consisting of p-shield, p-body, and n-region between them is punched through, leaving negative charges in the floating p-shield even when the high V{{\text {DS}}} is removed. Based on this mechanism, the behaviors of the FS-MOS are well explained. [ABSTRACT FROM AUTHOR]

Resistive switching memory (RRAM) features many optimal properties for future memory applications that make RRAM a strong candidate for storage-class memory and embedded nonvolatile memory. This paper addresses the cycling-induced degradation of RRAM devices based on a HfO2 switching layer. We show that the cycling degradation results in the decrease of several RRAM parameters, such as the resistance of the low-resistance state, the set voltage V\mathrm{ set} , the reset voltage V\mathrm{ reset} , and others. The degradation with cycling is further attributed to enhanced ion mobility due to defect generation within the active filament area in the RRAM device. A distributed-energy model is developed to simulate the degradation kinetics and support our physical interpretation. This paper provides an efficient methodology to predict device degradation after any arbitrary number of cycles and allows for wear leveling in memory array. [ABSTRACT FROM AUTHOR]

The focus of this paper is to understand the impact of the material properties of GaN, exploited using a vertical device, in power switching by estimating switching loss. The study was performed with a cascoded current aperture vertical electron transistor (CAVET). The normally OFF device was simulated and analyzed using a Silvaco ATLAS 2-D drift diffusion model integrated to SPICE-based circuit simulator. Besides evaluating the performance space and, hence, potential application space for GaN CAVETs, this paper presents significant accomplishment in establishing a device to circuit model, thereby, offering a reliable method of evaluating GaN-based power transistors. The accuracy of the model was established through the excellent agreement of simulated data with the data sheet specs of a commercial cascoded GaN high electron mobility transistor. The model was successfully applied to compare SiC MOSFETs with GaN CAVETs. A cascoded GaN CAVET has $2\times $ faster switching time, $3\times $ lower switching loss compared with standard commercial SiC MOSFET, owing to the higher electron mobility in GaN. Operating at frequencies of megahertz with low power loss, a GaN CAVET will, therefore, lead to smaller converter size and higher system efficiency. [ABSTRACT FROM PUBLISHER]

The physical unclonable function (PUF) is a promising innovative hardware security primitive that leverages the inherent randomness in the physical systems to produce unique responses upon the inquiry of challenges, thus the PUF could serve as a fingerprint for device authentication. In this paper, we propose a novel PUF implementation exploiting the sneak paths in the resistive cross-point (X-point) array, as a hardware security primitive. The entanglement of the sneak paths in the X-point array greatly enhances the entropy of the physical system, thereby increasing the space of challenge-response pairs to make a strong PUF. The X-point PUF characteristics, such as uniqueness and reliability, are experimentally evaluated on the fabricated $12 \times 12$ cross-point arrays based on the Pt/HfOx/TiN structure. The measurement results show that the average inter-Hamming distance of the response bits is around 46.2% across 28 different arrays, showing sufficient uniqueness. The measurement results also demonstrate that 0% intra-Hamming distance (or 100% reliability) of the response bits can be maintained more than 7.2 h at 100 °C (or equivalently ten years at 40 °C). This paper demonstrates the feasibility of using X-point PUF as a lightweight and reliable PUF for device authentication. [ABSTRACT FROM PUBLISHER]

Although spin transfer torque (STT)-based magnetic tunneling junction (MTJ) owns advantages of nonvolatility, nonlimited endurance, and fast write/read, its demand for high current density significantly casts a shadow over its future prospects. Recently, a novel three-terminal MTJ cell that combines voltage-controlled magnetic anisotropy (VCMA) effect and negative capacitance (NC) effect is proposed. Drawing support from the NC amplified VCMA effect and the three-step operation scenario, this novel MTJ cell can dramatically lower the energy consumption to fJ as well as keep high operation speed within nanoseconds. The feasibility of the proposed NC enhanced VCMA spintronics device for memory and logic application is proved by extensive physical simulation in our previous work. However, a SPICE compatible compact model of the proposed NC enhanced VCMA spintronics device is still demanded for circuit and system level evaluation. In this paper, we provide an accurate and fast compact model of NC enhanced VCMA device for both memory and logic applications. [ABSTRACT FROM AUTHOR]

In this paper, the requirements of device cross section and aspect ratio (AR) are examined to facilitate steep switching in heavily doped 3-D multiple gate junctionless (JL) transistors. It is shown through well-calibrated simulations and physical insights that the sharp OFF-to- ON switching action is predominantly governed by the area of cross section (${A} _{\textsf {cross}}$) instead of the gate length. A 3-D JL architecture preferably oriented toward a planar topology, i.e., with wider fin and low AR, is conducive for steep switching as a greater bulk area is available for impact ionization. On the contrary, narrow vertical architectures with AR > 1 suppress ${A} _{\textsf {cross}}$ in the bulk and are less likely to support the steep current transition. Steep switching specific scaling methodology is showcased to attain a sharp increase in drain current with a sub-60 mV/decade swing in a tri-gate JL transistor along with an associated negative value of total gate capacitance. [ABSTRACT FROM AUTHOR]

In spite of the apparent simplicity of the system under study, compact modeling of complementary resistive switching (CRS) devices, i.e., two antiserially connected memristive structures, is by no means straightforward. This requires a deep understanding of the voltage drops occurring across the circuit elements and correct treatment of the so-called snapback (SB) effect typical of the breakdown process of a thin dielectric film in an MIS or a MIM structure. The SB effect fundamentally consists in a sudden reduction of the device resistance caused by the formation of a filamentary path spanning the insulator. Beyond this point, the filament widens keeping the voltage drop across its extremes constant. The consequence of disregarding this effect is clearly distinguishable in the simulated curves: progressive openings of the on-state windows for both positive and negative voltages instead of abrupt ones. In this paper, a modification is introduced in the original memdiode model for memristive devices in order to account for this remarkable feature. Ta2O5-based CRS devices are considered to demonstrate the suitability of our approach. [ABSTRACT FROM AUTHOR]

This paper investigates material modifications induced by cosputtering indium-tin oxide (ITO) with gadolinium (Gd) at two different power levels. In addition, resistance switching (RS) properties were also verified for use as an insulator in resistive random access memory (RRAM). Comparison of scanning electron microscope (SEM) measurements for the two different cosputtering powers indicated significant changes of the ITO surface. Transparency was also verified by an N&K analyzer measurement, with results indicating a constant in transparency induced by the lower power Gd doping, indicating potential for transparent applications. Furthermore, the mole fraction ratio defined by X-ray photoelectron spectroscopy reveals a Gd2O3 peak, a likely reason for the ITO thin film becoming less conductive. This ITO/Gd:ITO/TiN RRAM can exhibit stable and robust RS characteristics at a lower forming voltage. In addition, lower operating voltages, including both SET and RESET voltages, can be obtained. Reliability tests including endurance and retention were carried out to confirm its RS stability. The RS mechanism of this ITO/Gd:ITO/TiN device was also investigated with the current–voltage (${I}$ – ${V}$) fitting method. Moreover, temperature effects were also applied to verify the high-resistance state (HRS) mechanism. Finally, a conduction model was proposed to clarify the RS characteristics and confirm that the ITO/Gd:ITO/TiN device is appropriate for data storage. [ABSTRACT FROM AUTHOR]

In this paper, an improved 4H-SiC U-shaped trench-gate metal–oxide–semiconductor field-effect transistors (UMOSFETs) structure with low ON-resistance (${R}_{ \mathrm{\scriptscriptstyle ON}}$) and switching energy loss is proposed. The novel structure features an added n-type region, which reduces ON-resistance of the device significantly while maintaining the breakdown voltage (${V}_{\textsf {BR}}$). In addition, the gate of the improved structure is designed as a p-n junction to reduce the switching energy loss. Simulations by Sentaurus TCAD are carried out to reveal the working mechanism of this improved structure. For the static performance, the ON-resistance and the figure of merit (FOM $= {V}_{\textsf {BR}}^{\textsf {2}}/{R}_{ \mathrm{\scriptscriptstyle ON}}$) of the optimized structure are improved by 40% and 44%, respectively, as compared to a conventional trench MOSFET without the added n-type region and modified gate. For the dynamic performance, the turn-on time (${T}_{ \mathrm{\scriptscriptstyle ON}}$) and turn-off time (${T}_{ \mathrm{\scriptscriptstyle OFF}}$) of the proposed structure are both shorter than that of the conventional structure, bringing a 43% and 30% reduction in turn-on energy loss and total switching energy loss (${E}_{\mathbf {SW}}$). [ABSTRACT FROM AUTHOR]

This paper investigates the issues of oxygen accumulation and variation in the high-resistance state of HfO2-based resistive random access memory (RRAM), with improvement attained by inserting a thin oxygen-vacancy-rich layer of indium-tin-oxide (ITO) film. By acting as the oxygen ion reservoir, this ITO thin film on the TiN electrode can further stabilize resistance switching (RS) characteristics. In terms of reliability, ac endurance, and retention tests confirm stable RS characteristics for the Pt/HfO2/ITO/TiN device. Finally, a conducting model was proposed to explain the influence of the ITO thin layer and clarify the physical mechanism of electrical improvements. [ABSTRACT FROM AUTHOR]

Ferrimagnets (FiMs) are divided into small domains comprising of oppositely polarized magnetic moments and weak anisotropy. FiM possesses a small net magnetization with strong exchange coupling energy. When FiM comes in contact with a material having strong spin–orbit coupling, such as heavy spin Hall metal, the nonlinear magnetic exchange interaction known as Dzyaloshinskii–Moriya interaction (DMI) becomes significant, especially at the FiM/heavy metal (HM) interface. In this paper, we derive the contribution of DMI in FiM magnetization and show that DMI plays a crucial role in FiM magnetization dynamics. We show that torque is being exerted on the interfacial magnetic moments due to DMI, trying to reorient the interfacial magnetization landscape in FiM. On the other hand, exchange coupling tries to resist the external perturbation due to DMI and keep the interfacial magnetic moments at their respective equilibrium positions. Our analysis shows that simultaneous action of DMI and exchange coupling result in small tilting of the interfacial magnetic moments. Moreover, spin-polarized current, injected into the FiM, introduces oscillation due to two different types of spin-transfer torques—namely, “field-like” torque and “damping-like” torque. We also show that the oscillation frequency of magnetic moments near the FiM/HM interface is a function of only internal FiM exchange coupling and interfacial DMI when the injected spin current density is low. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the relationship between size, shape, and the performance of the voltage-controlled magnetic anisotropy (VCMA)-based magnetic tunnel junctions (MTJs) suitable for gigabit scale MRAMs with 10 years of retention time. A Fokker–Planck simulation framework is developed to model the magnetization dynamics in the presence of thermal noise. Here, we numerically show that the optimization of the MTJ geometry can significantly improve the performance of the VCMA-based MTJs. Using an elliptical MTJ with aspect ratio (AR) of 3 reduces the required supply voltage and energy consumption by 80.7% and 92%, respectively, compared to a circular MTJ when the minimum feature size is 50 nm. The design requirements on the VCMA coefficient, ${\xi }$ , are also reduced by 67%. However, the influence of AR is observed to diminish with reduction in the minimum feature size of the MTJ. For instance, when the minimum feature size is 20 nm, the required supply voltage and energy consumption reduce only by 60.29% and 65.30%, respectively. We, then, perform a comprehensive scaling analysis on the VCMA-based MTJs by varying size, geometry, and ${\xi }$ of the MTJs. The predicted scaling trends are then compared with those of the STT MTJs. [ABSTRACT FROM AUTHOR]

Resistive random access memory (ReRAM), a new emerging nonvolatile memory technology based on changes in electrical resistivity of a dielectric film, offers promising advantages such as scalability, fast switching, and low operation voltage. However, for ReRAM to become a successful technology, it is necessary to accurately control the stochastic nature of the conductive nanoscale filaments (CNFs) that governs the resistive switching (RS) behavior of the device and limits its long-term stability and reliability. In this paper, we developed a highly scalable nanostructured/textured electrode that is composed of an array of Al nanotips based on an anodic aluminum oxide template. The nanotips improve the RS characteristics by intensifying the electric field at the apex of each nanotip which is demonstrated using numerical simulations. The localized electric field induces the repetitive nucleation/ formation/rupture of the CNFs in a more controlled fashion compared to a flat Al electrode. As a result, the nanotip sample exhibits uniform and reduced forming/reset voltages as low as 4.70 ± 0.98V/1.00 ± 0.19 V, stable endurance, and long-term retention. As a result, we were able to achieve ultralow-power and error-free operation of 100 cells covering a large area, significantly demonstrating improved uniformity and reliability compared to devices made using flat Al electrodes. This universal bottom-up strategy of self-organized nanostructured-electrodes provides a pathway toward large-scale, highly reliable, and RS memory devices. [ABSTRACT FROM AUTHOR]

The reverse-conducting insulated gate bipolar transistor (RC-IGBT) has several benefits over a separate IGBT and diode solution and has the potential to become the dominant device within many power electronic applications; including, but not limited to, motor control, resonant converters, and switch-mode power supplies. However, the device inherently suffers from many undesirable design tradeoffs which have prevented its widespread use. One of the most critical issues is the snapback seen in the forward conduction characteristic which can prevent full turn-on of the device and result in the device becoming unsuitable for parallel operation (required in many high voltage modules). This phenomenon can be suppressed but at the expense of the reverse conduction performance. This paper provides an overview of the technical design challenges presented by the RC-IGBT structure and reviews alternative device concepts which have been proposed in literature. Analysis shows that these alternate concepts either present a tradeoff in performance characteristics, an inability to be manufactured, or a requirement for a custom gate drive. [ABSTRACT FROM AUTHOR]

In the study of resistive random access memory using GeTeOx film as the switching layer, the device performed excellent property of bipolar resistive switching (BRS), which could be gradually transformed to the complementary resistive switching (CRS) by varying SET process current compliance. The conductive filament conduction mechanism of BRS could be verified by electrical characteristics and reliable data fitting. Through increasing current compliance of the SET process, CRS could be achieved due to higher activity of oxygen vacancies originated from the intensified thermal effect. This paper was beneficial to understand the switching mechanisms of BRS and CRS and provide a method to realize interconversion. Moreover, it was also a potential and promising device to be applied in the neurosynaptic biomimetic field. [ABSTRACT FROM AUTHOR]

Mechanisms of time-dependent dielectric breakdown (TDDB) in nonfilamentary a-Si/TiO2 RRAM cell [a-vacancy modulated conductive oxide (VMCO)] have been examined in this paper, including defects generation in the grain boundary, defects clustering, and different defects generation rates in a-Si and TiO2 layers. The unique feature of a bimodal Weibull distribution at low-resistance state (LRS) and a single shallow slope distribution at high-resistance state (HRS) cannot be explained by the above mechanisms. By using a combination of constant voltage stress, time-to-breakdown Weibull distribution, and random telegraph noise (RTN)-based defect profiling in devices of various sizes, layer thicknesses, and processes, it is revealed that the defect profile is modulated when switching between HRS and LRS and the correlation of defect profile modulation with local defect generation rate can explain the difference in Weibull distributions at HRS and LRS. The transition from bimodal distribution at LRS to a single-steep slope with thinner a-Si layer, and the good area scaling of Weibull distribution at HRS but not at LRS, can also be explained. The critical layers affecting the TDDB in a-VMCO are identified, providing useful guidance for device performance improvement. [ABSTRACT FROM AUTHOR]

Feedback field-effect transistor (FBFET), an alternative switching device, has received attention due to its ideal steep switching feature. By utilizing the positive feedback phenomenon, the total amount of electrons and holes contributing to drain current is sharply surged. Although the device has conspicuous subthreshold slope (SS) properties, advanced research for structure and performance of it is lacking. In this paper, single-gated and spacer-less silicon-on-insulator (SOI) FBFET with extremely steep switching (~1 mV/decade) characteristic is studied in various aspects; SS attribute, performance variation of scaled FBFET, the impact of structural variation, the gate margin for the device layout, and the hysteresis window. The prospect of SOI FBFET as a future candidate for CMOS logic application is investigated in detail. [ABSTRACT FROM AUTHOR]

An intentionally introduced interface layer in the resistive random-access memory (RRAM) devices play an important role in the improvement of resistive switching characteristics. In this paper, the resistive switching characteristics of ZrO2-based RRAM devices by inserting a thin TiO2 interface layer between electrodes and ZrO2 resistive switching layer were investigated. Compared with the Cu/ZrO2/Pt and Cu/ZrO2/TiO2/Pt devices, the Cu/TiO2/ZrO2/Pt and Cu/TiO2/ZrO2/TiO2/Pt devices showed much improved programing voltages, including lower forming voltage and lower set voltage. Moreover, the reset current was also improved. These results indicate that the TiO2 interface layer between the anode electrode and the resistive switching layer plays an important role in improving device performance. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel technique of realizing discrete-time (D-T) signal amplification using Nano-Electro-Mechanical systems (NEMS). The amplifier uses mechanical switches instead of traditional solid-state devices and acts as an inherent sample and hold amplifier. The proposed NEMS D-T amplifier operates on a wide dynamic range of signals without consuming the dc power. Moreover, the proposed amplifier does not suffer from the leakage current and the nonlinearity associated with the sampling ohmic switch. As a proof of concept, the proposed NEMS D-T amplifier is demonstrated in circuit simulations using the calibrated verilog-A models of the NEMS device. The simulated amplifier achieves a gain of ~5, handles the maximum differential input signal of 0.65 V, and consumes only $0.6~\mu \text{W}$ of power for a sampling frequency of 100 kHz. The nonidealities present in the proposed amplifier are highlighted and possible ways to overcome them are discussed. Finally, the design considerations required for the NEMS D-T amplifier are described. [ABSTRACT FROM AUTHOR]

In the quest for novel, scalable and energy-efficient computing technologies, spin-based logic devices are being extensively explored due to their potential for nonvolatility, small cell area, and low operational power. Spin torque majority gate (STMG) is one of the most promising options for beyond CMOS nonvolatile logic circuits for normally-off computing. However, significant problems arose with cascade-ability, signal nonreciprocity, and complicated circuit configurations based on STMG. In this paper, a novel magnetic majority gate (MMG) logic has been proposed, utilizing both spin transfer torque and spin–orbit torque effects. A logic family including and/nand and or/nor functions can be achieved with an easy configuration and under a stable operation. Communication between logic units is realized by spin current injection through a nonferromagnetic metal wire to ensure its cascade-ability and nonreciprocity to design multiple logic-depth circuits. With all of these advantages, the proposed cascadable MMGs can be utilized to design logic functions such as the BUFFER/ NOT, XOR/ XNOR, and complicated logic gates, which pave the pathway for designing robust and comprehensive logic circuits using full spintronic devices. [ABSTRACT FROM AUTHOR]

The figure of merit (FOM) of a semiconductor device represents an important quality as it pertains to its performance limits and is often used to drive the technology development in a specific direction. Comparing the performances of switching power MOSFETs using their FOMs has become ubiquitous practice in power semiconductor and power electronics industries. In this paper, a critical review of the proposed power MOSFET FOMs is presented, and key limitations are discussed. It is shown that the quality factor ${Q}_{F2}={(}{\lambda {E}_{c}}/{R_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}}{)}$ along with ${Q}_{G}$ and ${T}_{j\textsf {max}}$ may be used to guide the development of future generations of power semiconductor device technologies for power electronics switching applications, where $\lambda $ and ${E}_{c}$ are the thermal conductivity and critical electric field strength for the avalanche breakdown of the semiconductor material, respectively, ${R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ is the specific on-state electrical resistance, ${Q}_{G}$ is the gate charge, and ${T}_{j\textsf {max}}$ is the maximum junction temperature of the semiconductor power device, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a comparison of switching performances between the in-situ oxide, gallium nitride (GaN) interlayer FET (OG-FET) and the conventional GaN metal–oxide–semiconductor FET (MOSFET), and explores the influence of the channel electron mobility on the device switching performance. GaN OG-FET is a novel structure with a pristine GaN layer grown between the gate oxide and the p-GaN enhancing the channel mobility up to 185 cm2/ $\text {V}\cdot \text {s}$ , which is over $3{\times}$ larger than that of the typical reported value (50 cm2/ $\text {V}\cdot \text {s}$) in GaN MOSFET. Owing to the high channel electron mobility, the GaN OG-FET showed a switching loss 30% lower than that of the conventional GaN trench MOSFET. Our results indicate that GaN OG-FET has the potential to attain greater efficiency, particularly at higher frequencies, showing a possible patch toward megahertz range conversions. [ABSTRACT FROM AUTHOR]

When developing silicon carbide (SiC) devices, the reliability of the internal body diode is an important issue. Stacking faults (SFs) are expanded from basal plane defects by using a body diode. Although it is well known that ON-voltage degradation occurs due to SFs, their effects on dynamic reliability have not been studied well. Furthermore, including the effects of SFs, there are not many reports about the dynamic reliability of SiC-MOSFETs. In this paper, a double-pulse switching test using 3.3-kV SiC-MOSFETs was carried out to clarify the failure mechanism of the switching operation of SiC-MOSFETs and effects of SFs on the safe operation area (SOA). Before the switching test, current stress was applied to the body diode of the devices under test (DUTs) to expand the SFs. The circuit configuration was half-bridge type, and a double-pulse gate signal was applied to the lower arm DUT. The switching voltage was 1.8 kV, and the switching current increased at about 8-A steps to failure. As a result, reverse recovery SOA (RRSOA) reliability decreased depending on the amount of SFs in the SiC-MOSFET. Because RRSOA failure was caused by avalanche due to the hole concentration during reverse recovery and the SFs raised local current density, reverse bias SOA (RBSOA) hardly decreased even if SFs containing SiC-MOSFETs were used. This is because RBSOA failure was caused by degradation of the gate isolation layer due to overheating and the temperature coefficient of the SFs electric resistance indicated negative. [ABSTRACT FROM AUTHOR]

In this paper, we present the effects of curing temperature on switching between the transparent and translucent states in a polymer-stabilized liquid-crystal (PSLC) cell. When cured at a low temperature, polymer structures are formed without disturbing the initial alignment of LCs so that haze in the transparent state is dramatically reduced. Moreover, we can achieve very fast switching between the haze-free transparent and high-haze translucent states because there is a little degradation in the performance of the transparent and translucent states when the polymer concentration is increased. We demonstrated an ON–OFF response time of less than 3 ms and a gray-to-gray response time of less than 6 ms in a PSLC cell. [ABSTRACT FROM AUTHOR]

In this paper, vanadium oxide (VOx) was chosen for the resistive switching layer in a typical resistive random access memory (RRAM) structure. During negative forming bias, we found an initial selector property. This indicates the presence of metal–insulator-transition characteristics in the VOx layer even without an annealing process. In order to study this phenomenon, material analyses were conducted, with results indicating that there are V-O stretching bonds and an oxide/vanadium ratio of nearly 2.2 (${O}/{V} = {2.2}$). In addition, the experimental results of the dc sweeping test indicated that off-state current gradually decreased after each cycle, meaning that the selectivity characteristics in the VOx selector could be improved. Endurance performance of our experimental devices reached 108, sufficient for integration with RRAM devices in a 1S1R array. To further investigate this special phenomenon, current fitting analysis and simulation analyses were conducted. The results of the fitting analysis indicated that the conduction mechanism for off-state current was Schottky emission and the Schottky distance increased with increasing numbers of cycles. In other words, oxide ions migrate toward the filament at low negative voltage during dc sweeping, causing the formation of VOx. Furthermore, the results of thermal field simulation analysis indicated that there is a thermal concentration effect in and around the filament. Thus, oxide ions more easily migrate toward the vanadium filament when a stronger electrical field is present around the filament during dc sweeping cycles. Finally, stable vanadium selector characteristics are obtained and a conduction filament behavior model is proposed. [ABSTRACT FROM AUTHOR]

The switching properties of Te and TeTiW top electrodes (TEs) on TiW/SiN/TiN resistive switching memory devices are explored in this paper. The TeTiW TE device exhibits more favorable bipolar resistive switching behavior because of the decrease in binding energy after its use. This finding is confirmed through X-ray photoelectron spectroscopy analyses. The filament of the TeTiW TE device is metal like after forming, and the reset process corresponds with the thermal-dissolution mechanism. A physical model based on a Te filament is constructed to explain such phenomena. The TeTiW TE device provides the excellent endurance of more than 104 cycles, with an ON/OFF ratio of 500. The improvement can be attributed to the filament’s robustness during the forming and set processes, which prevent its diffusion even at high temperature. The device also features long retention for up to 104 s at 225 °C without stress, and 104 s at 85 °C with stress of −0.3 V. Therefore, it has high potential for high-density nonvolatile memory applications. [ABSTRACT FROM AUTHOR]

Negative capacitance FET (NCFET) has become a research topic of interest in recent years due to its interesting properties. It has the ability to retain the polarization state even in the absence of electric field. By virtue of this ability, it can be designed as a nonvolatile memory. NCFET can also be configured as a steep-slope switch and thereby providing energy efficiency while used in digital designs. However, the benefits offered by NCFETs for analog circuit domain has not well reported. In this paper, we analyze the impact of body effect on an NCFET-based bootstrapped switch and illustrate that the linearity of NCFET-based switch can be improved resulting from the internal amplification of the employed NCFET. When designed at 0.6-V supply (${V}_{\text {dd}}$), results show that the variation of the on resistance of the bootstrapped switch is about $67~\Omega $ during the sampling period, which is one-third smaller than the MOSFET-based switch. As a result, the sampling linearity is improved and the distortion at the output can be decreased. On condition that the Nyquist input frequency is 10 MHz, the proposed NCFET-based bootstrapped switch succeeds in improving the total harmonic distortion performance by 16.7 dB, compared with that of a conventional MOSFET-based bootstrapped switch. [ABSTRACT FROM AUTHOR]

In this paper, we demonstrate the linear conductance-change characteristics of a conductive-bridging RAM (CBRAM) to be employed as an artificial synapse device in neuromorphic systems. The CBRAM with a bilayer electrolyte structure (${\mathrm {Cu/Cu}}_{{2}-{x}}\text{S}$ / $\mathrm {WO}_{{3}-{x}}$ /W) exhibits analog switching behavior during the depression process due to the well-controlled dissolution of the conductive filament. To analyze the origin of this motion, we investigate the effective voltage applied to $\mathrm {Cu}_{{2}-{x}}\text{S}$ and $\mathrm {WO}_{{3}-{x}}$. Our findings reveal that $\mathrm {Cu}_{{2}-{x}}\text{S}$ , acting as a voltage divider, helps in suppressing the large voltage drop in $\mathrm {WO}_{{3}-{x}}$ , where the formation/dissolution of filament occurs. Furthermore, due to the diode-like characteristics of $\mathrm {Cu}_{{2}-{x}}\text{S}$ and the division of voltage drop between $\mathrm {WO}_{{3}-{x}}$ and $\mathrm {Cu}_{{2}-{x}}\text{S}$ , an optimum programming energy is applied to $\mathrm {WO}_{{3}-{x}}$ during the depression process. This leads to linear conductance-change characteristics under identical pulses. However, abrupt conductance-change characteristics are observed during the potentiation process. Thus, we use only the device characteristics of the depression part for the neuromorphic system. An excellent classification accuracy is achieved due to the linear conductance-change characteristics and optimized pulse conditions. [ABSTRACT FROM AUTHOR]

The accurate calculation of switching voltage (${V}_{s}$) is necessary for the reliable and low-power operation of monolithic 3-D (M3D) CMOS-nanoelectromechanical (NEM) hybrid reconfigurable logic circuits because ${V}_{s}$ corresponds to the operating voltage (${V}_{\text {dd}}$) of NEM memory switches. In this paper, based on the Euler–Bernoulli equation, the physics-based analytical model is proposed to determine ${V}_{s}$. The accuracy of the proposed model is verified by both the finite-element analysis and experimental results. Our proposed model shows >3% error compared with experimental data. Also, the design guidelines of NEM memory switches are presented in terms of minimum ${V}_{s}$ (${V}_{s\_{}{m}}$) and device dimensions. [ABSTRACT FROM AUTHOR]

This paper reports on the suppression of single-transistor latch, an extreme condition of impact ionization (I.I.), in n-type double-gate germanium (Ge) junctionless (JL) transistors. It is shown that JL transistors can be latched to the on-state due to an increase in the I.I. generated power per unit volume with an increase in drain bias, film thickness, oxide thickness, and doping. Latch, being detrimental to switching, can be effectively suppressed by applying an appropriate negative (positive) back-gate bias for n-type (p-type) JL MOSFET. The independent gate operation with appropriate back bias allows the device to overcome latching and regain switching action with a subthreshold swing (${S}$ -swing) <10 mV/decade at room temperature. The work showcases the limit imposed on back bias due to an increase in off-state current due to band-to-band tunneling along with the utility of sidewall spacer to effectively suppress the same. We also show the tunability of hysteresis using back-gate bias. The work highlights a systematic methodology to eliminate single-transistor latch while preserving sub-60 mV/decade switching in Ge JL MOSFETs. [ABSTRACT FROM AUTHOR]

Bipolar redox-based resistive random-access memory cells are intensively studied for new storage class memory and beyond von Neumann computing applications. However, the considerable variability of the resistance values in ON and OFF state as well as of the SET voltage remains challenging. In this paper, we discuss the physical origin of the significant reduction in the switching variability of HfO2-based devices achieved by the insertion of a thin TiOx layer between the HfO2 layer and the oxygen exchange metal layer. Typically, HfO2 single layer cells exhibit an abrupt SET process, which is difficult to control. In contrast, self-compliance effects in the HfO2/TiOx bilayer devices lead to an increased stability of SET voltages and OFF-state resistances. The SET process is gradual and the RESET becomes abrupt for higher switching currents. Comparison of the experimental data with simulation results achieved from a physics-based compact model for the full description of the switching behavior of the single layer and bilayer devices clearly reveal three major effects. The TiOx layer affects the temperature distribution during switching (by modifying the heat dissipation), forms an additional series resistance and changes the current conduction mechanism in the OFF state of the bilayer device compared to the single layer device. [ABSTRACT FROM AUTHOR]

Performance of the crossbar memory array highly depends on the selector characteristics. In this paper, rigorous transient analyses are performed for a large-size crossbar memory array using novel NbO2-based selectors with a threshold switching behavior. To enable accurate and efficient array-level simulation, an electrostatic discharge-based compact model is employed to effectively describe the ${I}$ – ${V}$ characteristics of the selector. Multiple key design parameters of the selector are investigated, such as the threshold voltage, leakage current, and intrinsic switching speed. A sensitivity analysis is performed to evaluate the impact of hypothetical improvements in various selector parameters. In addition, the impacts of resistances of interconnect and memory element on the array-level access delay and energy dissipation are quantified. The results show that reducing the threshold voltage of selectors provides the most significant performance improvement, where up to 80% of the energy-delay product saving is observed if the threshold voltage is reduced by 50%. [ABSTRACT FROM AUTHOR]

A comprehensive study on the dielectric modulated (DM) drift region for power devices is presented in this paper. The performance of this drift region structure is theoretically analyzed and compared with other two structures: conventional and superjunction. In this paper, a study is focused on switching performance. The C – V relationships during switching are analytically derived, and the depletion widths predicted by the proposed analytical model agree well with simulation in a wide reverse bias region. The switching energy loss is evaluated based on the analytical model and its accuracy is verified by 2-D simulations. An effective depletion charge QD is defined as E\mathrm {loss} / breakdown voltage (BV), from which a figure of merit (FOM) of R\mathrm{\scriptscriptstyle ON,\mathrm {sp}}{}^\ast QD is proposed to compare the performances of these different drift region structures, considering both the conduction and switching losses. The discussions in part I on Si and silicon carbide device structures are extended in part II to include FOMs. It is found that the DM drift region structures show better R\mathrm{\scriptscriptstyle ON,\mathrm {sp}} -BV tradeoffs compared with the conventional structures, but slighter inferior FOMs. However, DM structures are still attractive for applications, where switching loss is less critical than the conduction loss, such as low frequency or soft switching. [ABSTRACT FROM PUBLISHER]

Power consumption of today’s integrated circuit is very difficult to reduce because the MOSFET is subjected to the thermal limit of 60 mV/decade for the subthreshold swing (SS). In this paper, we show that this SS limit of thermionic current can be conquered—thus power consumption drastically reduced by density of states (DOS) engineering at the source. Specifically, the linear DOS of Dirac electrons at the source concomitant with an efficient gate control brings the SS limit down to 37 mV/decade, and further down to very small values by suppressing the thermal tail contribution with a small bandgap in the injected DOS. Using the first principles analysis, we demonstrate that FETs with Dirac source to possess extremely promising device performance in both energy dynamic power and switching speed at the ultralow operating voltage regime of 0.3 V compared with ultrathin-body Si FETs. [ABSTRACT FROM AUTHOR]

Spin transfer torque (STT)-based switching of magnetic random access memories (MRAMs) has stimulated considerable research interest in recent years. The nonvolatility of STT-MRAMs, high areal density, and low static power dissipation makes them a strong contender for possible replacement of conventional silicon-based memories. However, a major bottleneck associated with STT-MRAMs is their high write current requirement. Recently, it has been demonstrated that the high write current of the STT switching mechanism can be improved by using other magnetic switching techniques like voltage-controlled magnetic anisotropy, spin Hall effect, and magnetoelectric effect. Interestingly, each of these new physics increases the design space to be explored and presents interesting tradeoffs with respect to read and write mechanisms. It is, therefore, important to analyze these devices with respect to their readability, writability, and areal density in a unified framework that is based on the state-of-the-art experimental results. Toward that end, in this paper, we present an overview of various physics underlying these magnetic memories and discuss associated bit-cell circuitry. Furthermore, we present a holistic comparative analysis based on detailed numerical simulations highlighting the various design tradeoffs. [ABSTRACT FROM AUTHOR]

Resistive random access memory is known as a type of nonvolatile memory. An abnormal volatile memory characteristic of a normal ZnSnO resistive memory is first demonstrated in this paper. Although the ${I}$ – ${V}$ curves exhibit a normal and stable resistive switching memory behavior, the resistance state is found to be only determined by the initial applied voltage along with the voltage sweep direction. It is set/reset processes free. Namely, it is volatile. The resistance states are found to be dominated by trap-assisted tunneling, trap-controlled space-charge-limited conduction, and hopping transport. Different resistance states are related to different carrier transport mechanisms. Each resistance state can independently and repeatably appear for over 1000 voltage sweeps. The ratio of the high-resistance state to the low-resistance state is $\sim 3\times 10^{2}$. [ABSTRACT FROM AUTHOR]