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This paper investigates the multilevel behavior of phase-change random access memory devices with a dual phase-change material (PCM) stack, i.e., two PCMs stacked on one another. The dual PCM stack comprises of a \Ge2\Sb2\Te5 (GST) layer and a top PCM layer sandwiching a SiN barrier layer. The top PCM layer was varied in three different splits: \Ag0.5\In0.5\Sb3\Te6 (AIST), \Ge1\Sb4\Te7 (GST147), and nitrogen-doped GST (NGST). Extensive electrical characterization and statistical analysis were performed. The intrinsic properties of AIST, GST147, and NGST were used to explain the differences in electrical performances of the three multilevel device splits. The AIST/SiN/GST device split was found to have had the best electrical performance. The difference in electrical resistivities and thermal conductivities played a major role in the power consumption as well as the resistance values of the three multilevel states in these dual PCM multilevel devices. [ABSTRACT FROM PUBLISHER]

Understanding the physical mechanisms for resistance change in metal oxides is a key challenge to assess the scalability of resistive-switching random access memory (RRAM) devices. From this standpoint, the time dependence of filament formation and dissolution in metal oxides can provide a useful insight into the fundamental mechanism of resistive switching. In this paper, we show an experimental study of the time-dependent filament growth and of the voltage dependence of set/reset times in \HfOx-based RRAM devices. The voltage across the device is shown to be regulated at any given time irrespective of the compliance current and the applied voltage, evidencing that voltage is the controlling parameter for the filament formation and dissolution during switching. These results are explained in terms of a thermally-activated ion migration model for filamentary switching. The model allows for an analytical calculation of the scaling dependence of set/reset times and energies in RRAM. [ABSTRACT FROM AUTHOR]

This paper presents a CMOS image sensor with 10-bit column-parallel successive approximation analog-to-digital converters (SA-ADCs). The SA-ADC in each column integrates the binary-weighted references instead of using an internal digital-to-analog converter (DAC) to reduce the area. The area of the column 10-bit SA-ADC is \9\ \mu\m \times \425\ \mu\m. The area of the capacitor array in the SA-ADC is reduced to only 2.8% compared with that of a conventional binary-weighted capacitor DAC. In order to reduce the power consumption, the SA-ADC uses the switched power technique. The constant analog-to-digital conversion time and the switched power technique increase the power saving rate as the frame rate decreases. The proposed image sensor has been fabricated using a 0.13-\mu \m CMOS process. The measured power consumption of the proposed SA-ADC is reduced to 85% and 58% of that in the SA-ADC without the switched power technique at the frame frequencies of 15 and 150 frames/s, respectively. [ABSTRACT FROM PUBLISHER]

Using the model developed in Part I of this two-part paper, the simulated dc sweep and pulse transient characteristics of a metal oxide resistive random access memory cell are corroborated with the experimental data of \HfOx memory. Key switching features such as the abrupt SET process, gradual RESET process, current fluctuation in the RESET process, and multilevel resistance state distributions are captured by the simulation. The current fluctuation in the RESET process is caused by the competition between the simultaneous oxygen vacancy recombination and generation processes. The origin of the high-resistance state variation and the tail bit problem are attributed to the variation of the tunneling gap distances and the stochastic nature of new Vo generation in the tunneling gap region, respectively. The use of the write–verify technique and a bilayer oxide structure are proposed to achieve a tighter resistance distribution. [ABSTRACT FROM AUTHOR]

Solid-state memory technology is undergoing a renaissance of new materials and novel device concepts for higher scalability as the mainstream technology, i.e., Flash, is approaching physical limits. Emerging memory technologies, which have unique characteristics not available in Flash, are leading transformations in the design of the memory hierarchy. Phase change memory (PCM) is a promising candidate for the next-generation nonvolatile-memory technology. It has been extensively studied for its electrical properties and material scalability. Yet, questions remain unanswered as to what extent a functional PCM cell can be ultimately scaled to and what properties a PCM cell has at the single-digit nanometer scale. In this paper, we demonstrated a fully functional cross-point PCM cell working close to its ultimate size-scaling limit by using carbon nanotubes (CNTs) as the memory electrode. The utilization of CNT electrode brings the lithography-independent critical dimension down to 1.2 nm and contributes to a large reduction of the reset programming current to 1.4 \mu\A and the programming energy to 210 fJ using a 10 ns reset pulse. Measured electrical characteristics validate the advantage of further device area scaling on reducing the programming current of PCM cells and confirm the potential viability of a highly scaled ultradense PCM array down to the bottom electrode contact area that corresponds to a 1.8 nm node technology. [ABSTRACT FROM AUTHOR]

The variation of switching parameters is one of the major challenges to both the scaling and volume production of metal-oxide-based resistive random-access memories (RRAMs). In this two-part paper, the source of such parameter variation is analyzed by a physics-based simulator, which is equipped with the capability to simulate a large number (\sim1000) of cyclic SET–RESET operations. By comparing the simulation results with experimental data, it is found that the random current fluctuation experimentally observed in the RESET processes is caused by the competition between trap generation and recombination, whereas the variation of the high resistance states and the tail bits are directly correlated to the randomness of the trap dynamics. A combined strategy with a bilayer dielectric material and a write-verification technique is proposed to minimize the resistance variation. We describe the simulation methodology and discuss the dc results in Part I. The corroboration of the model and the device optimization strategy will be discussed in Part II. [ABSTRACT FROM AUTHOR]

In this paper, we investigated the forming-free resistive-switching (RS) behavior in the \Ru/REOx/\TaN (\RE =\break \Ce, Pr, Sm, and Eu) memory device using \CeOx, \PrOx, \SmOx, and \EuOx thin films fabricated in a full-room-temperature process. The dominant conduction mechanism of \Ru/REOx\/ \TaN memory devices in the low-resistance state is ohmic behavior, whereas the high-resistance state is space-charge-limited conduction. The \Ru/CeOx \/\TaN devices show a high resistance ratio of > \10^4, reliable data retention for \10^5 \ \s, and stable endurance characteristics for up to 1000 cycles. This result suggests the high concentration of the cerium ions and the low density of chemical defects (oxygen vacancies) in the \CeOx film. The \Ru/CeOx\/\TaN structure memory is a very promising candidate for future nonvolatile RS memory applications. [ABSTRACT FROM AUTHOR]

Nonvolatile memory (NVM) devices based on storage layers, p-n junctions and transistors, such as FLASH, suffer from poor retention at high temperature, high voltage writing, and wear out while cycling. This paper presents the structure, operation, and modeling of a nanoelectromechanical NVM based on the switching of a free electrode between two stable states. This electrode, called the shuttle, has no mechanical anchors and commutes between two positions. It is guided inside an insulator pod. Adhesion forces between the shuttle and fixed electrodes serve to hold the shuttle in stable positions. Smooth metal layers give strong Van der Waals stiction between two surfaces in contact. Memory detection is obtained by probing the conductance between two fixed contacts; the shuttle serves as a switchable open/short electrode. Electromechanical contacts have an ideally large resistance ratio between on and off levels. At microscale, gravity is found to be negligible compared with adhesion forces, which motivates the anchorless design for high-temperature data storage. The model proposed is based on charge induction over the surface of metal electrodes and is validated by finite-element method. Kinematic equations and energy transfers of the shuttle device are explored. Due to its unique anchorless design, the scalability of the anchorless shuttle memory is found to be excellent. [ABSTRACT FROM AUTHOR]

This paper estimates the temperature distribution within a spin-torque-transfer RAM (STTRAM) cell due to self-heating using a thermal simulation based on the finite volume method. The analysis shows that, due to high switching current and small volume of the magnetic tunnel junction (MTJ), there can be significant rise in temperature in the MTJ as well as the silicon transistor. The impacts of the increased temperature on operational reliability metrics of the STTRAM cell, i.e., read disturb, write failure, and sensing accuracy, are evaluated. It is shown that, due to the self-heating effect, the operational reliability of an STTRAM cell depends on the read–write history of that cell. [ABSTRACT FROM AUTHOR]

Magnetic tunnel junctions (MTJs) composed of ferromagnetic layers with perpendicular magnetic anisotropy (PMA) are of great interest for achieving high-density nonvolatile memory and logic chips owing to its scalability potential together with high thermal stability. Recent progress has demonstrated a capacity for high-speed performance and low power consumption through current-induced magnetization switching. In this paper, we present a compact model of the CoFeB/MgO PMA MTJ, a system exhibiting the best tunnel magnetoresistance ratio and switching performance. It integrates the physical models of static, dynamic, and stochastic behaviors; many experimental parameters are directly included to improve the agreement of simulation with experimental measurements. Mixed simulation based on the 65-nm technology node of a magnetic flip-flop validates its relevance and efficiency for MTJ/CMOS memory and logic chip design. [ABSTRACT FROM AUTHOR]

High leakage power in sub-100-nm memory technology nodes drives the need for nonvolatile memory devices to reduce power consumption and enhance battery life. Spin-transfer torque magnetic tunneling junction (STT-MTJ) is a promising nonvolatile memory device with comparable read and write performances as SRAM and eDRAM with almost zero standby power. In this paper, we present a simulation framework that can solve transport [using nonequilibrium Green's function (NEGF) formalism] and magnet dynamics [using Landau–Lifshitz–Gilbert (LLG) equation] self-consistently to study the read and write performances of STT-MTJ. Due to process variations, thermal disturbances, and stray fields, the performance of STT-MTJ degrades and results in one transistor–one STT-MTJ (1T–1STTMTJ) memory failures. A thorough memory design space investigation can help us to reduce such failures. Hence, we present a design space exploration framework for 1T–1STTMTJ memory, which consists of magnetic materials with different RAPA products, different genres of MTJ stacks, and a transistor. A comprehensive study based on critical memory performance metrics such as tunneling magnetoresistance, JC, and write cycle shows the relative merits and demerits of each MTJ stack for embedded memory applications. Finally, the benefits of synthetic antiferromagnet free layer in providing immunity against stray fields are shown illustrating the need for coupled free-layer stacks in scaled technology nodes. [ABSTRACT FROM AUTHOR]

Resistive switching memory (RRAM) devices generally rely on the formation/dissolution of conductive filaments through insulating materials, such as metal oxides and chalcogenide glasses. Understanding the mechanisms for filament formation and disruption in resistive switching materials is a critical step toward the development of reliable and controllable RRAM for future-generation storage. In particular, the capability to control the filament resistance and the reset current through the compliance current during filament formation may provide a key signature to clarify the switching mechanism. This paper provides a physically based explanation for the universal resistance switching in bipolar RRAM devices. A numerical model of filament growth based on thermally activated ion migration accounts for the resistance switching characteristics. The same physical picture is extended to numerically model the reset transition. The impact of migration parameters and experimental setup on the set/reset characteristics is discussed through numerical simulations. [ABSTRACT FROM AUTHOR]

This paper introduces a novel structure for filamentary-conduction-type resistance change memory. The new structure utilizes the fringing field from the top metal electrode to effectively confine the position of the filaments in the cell. Nanoscale (100–50 nm) memory cells are fabricated using nickel oxide (NiO) thin film as the resistance-switching layer to demonstrate the feasibility and functionality of the new structure. The fabricated nanoscale memory cells achieved low reset current (100–200 \mu\A), narrower distribution in low-resistance states, and higher on/off ratio than those of the standard structure. In addition, good scalability down to 50 nm was demonstrated. [ABSTRACT FROM AUTHOR]

The need for reliable models that take into account the nonlinear kinetics of dopants is nowadays of paramount importance, particularly with the physical dimensions of electron devices shrinking to the deep nanoscale range and the development of emerging nanoionic systems such as the memristor. In this paper, we present a novel nonlinear dopant drift model that resolves the boundary issues existing in previously reported models that can be easily adjusted to match the dynamics of distinct memristive elements. With the aid of this model, we examine switching mechanisms, current–voltage characteristics, and the collective ion transport in two terminal memristive devices, providing new insights on memristive behavior. [ABSTRACT FROM PUBLISHER]

This paper presents, for the first time, the study of the application of a lateral diffused metal–oxide–semiconductor field-effect transistor (LDMOSFET) in a common-gate configuration to radio-frequency (RF) transmit/receive (T/R) switching circuits. A single-pole double-throw (SPDT) 900-MHz T/R switch is implemented using 0.25-\mu\m LDMOSFET foundry technology. Measured results show that our switching circuit can achieve a low insertion loss of 0.82 dB and a high power handling capability of 27 dBm. This result is promising in integrating power management integrated circuits, RF power amplifiers, and switching circuits in a single chip, based on LDMOSFET technology, to realize an RF transmit front-end system-on-chip solution. [ABSTRACT FROM AUTHOR]

The GaN high-electron mobility transistor (HEMT) structure has been widely investigated, particularly for radio-frequency applications. This structure is suitable for high-frequency switching applications in power electronics because of the high breakdown field of GaN and the high mobility of the channel. In this paper, a physical model for predicting the power-switching operation of GaN-based HEMTs as a function of material and device parameters is proposed. Analytical equations for total losses and power dissipation density are derived and discussed both qualitatively and quantitatively. [ABSTRACT FROM PUBLISHER]

This paper reports on the first demonstration of a reconfigurable complementary-metal–oxide–semiconductor (CMOS) oscillator based on microelectromechanical system (MEMS) resonators operating at four different frequencies (268, 483, 690, and 785 MHz). A bank of multifrequency switchable AlN contour-mode MEMS resonators was connected to a single CMOS oscillator circuit that can be configured to selectively operate in four different states with distinct oscillation frequencies. The phase noise (PN) of the reconfigurable oscillator was measured for each of the four different frequencies of operation, showing values between -94 and -70 dBc/Hz at a 1-kHz offset and PN floor values as low as -165 dBc/Hz at a 1-MHz offset. Jitter values as low as a 114-fs root mean square (integrated 12 kHz–20 MHz) and switching times as fast as 20 \mu\s were measured. This first prototype represents a miniaturized solution (30 times smaller) over commercially available voltage-controlled surface-acoustic-wave oscillators and potentially has the advantage of generating multiple stable frequencies without the need of cumbersome and power-consuming phase-locked-loop circuits. [ABSTRACT FROM PUBLISHER]

This paper reports the effects of rapid thermal annealing (RTA) on resistive switching (RS) characteristics and mechanisms of \SrZrO3 (SZO)-based memory devices. SZO thin films were deposited on \LaNiO3 (LNO) (\100)/\Pt/Ti/SiO2/\Si using radio-frequency magnetron sputtering and were followed by an RTA process in \N2, Ar, and \O2 ambients, respectively, at various temperatures for improving RS performance. Experimental results indicate that an SZO device annealed in \O2 at 600 ^\circ\C (\O2-600) exhibits stable RS properties and has a high device yield (\sim 90%), a reliable retention characteristic (up to \1 \times \10^6\ \s at 100 ^\circ\C), and steady nondestructive readout properties (over \1.4 \times \10^4\ \s at 100 ^\circ\C). However, by increasing RTA temperature to more than 700 ^\circ\C, random formation of LNO (110) precipitates on the bottom surface of SZO grains might shorten the effective thickness of the SZO thin films. Furthermore, a strong electric field possibly occurs at the region between Al top electrodes and low-resistivity LNO precipitates. It is speculated that an RS phenomenon, which occurs within SZO grains instead of on grain boundaries, easily leads to RS failure, further resulting in severe degradation of device yield in the \O2-700 and \O2-800 devices. When compared with other devices, \O2-600 SZO memory devices exhibit highly reliable RS characteristics. [ABSTRACT FROM AUTHOR]

The aim of this paper is to demonstrate the application of the superjunction (SJ) design in an insulated gate bipolar transistor (IGBT). Bipolar conduction is present and enhanced at the cathode side of the device, while the p-pillars collect the plasma deep from the anode side, thus significantly enhancing its turn-off speed. The disconnected soft \punchthrough+\ (\SPT+) SJ IGBT is similar to the SJ IGBT, which we have previously reported, but the drift region pillars do not extend up to the cathode contact. Instead, the upper part of this device is similar to the \SPT+ IGBT, i.e., it features an \n+ injector around the p-well and the n-drift region that is lightly doped. The improvement in the overall performance is impressive (25% lower on-state losses and 30% lower switching losses) and can indeed justify the technology cost associated with the SJ technology. We also demonstrate how this technology can be used to form a snapback-free reverse conducting IGBT. [ABSTRACT FROM PUBLISHER]

The transient simulation of threshold switching in phase-change memory (PCM) devices is essential for the prediction and optimization of cell behavior depending on the circuit parameters and for the understanding of the ultimate limit of operation speed. This paper presents a simulation study of threshold switching in PCM devices aimed at investigating the role of delay and switching times in cell behavior. The analytical Poole–Frenkel model for conduction and the energy gain model for threshold switching are used to evaluate the transient effects. The current and field transients at the basis of the switching phenomenon are shown and discussed with the aid of the numerical model. The impact of cell parasitics, in particular the parallel capacitance, is finally addressed. [ABSTRACT FROM PUBLISHER]

In this paper, we examine the performance characteristics of bilayer graphene pseudospin devices as we scale the layer width of the monolayers of graphene which comprise the bilayer structure. We find that, for layer widths of 30 nm, the device performance can exceed analytical predictions due to thermal smoothing of the interlayer interactions. However, when the device is further scaled to 20 nm and below, we find an appreciable drop of the maximum current the device can sustain when compared with the predicted values which result from increased quantum interference between injected quasi-particles and those reflected off of the excitonic gap opened at the Fermi energy. These results provide important insight into the maximum achievable performance characteristics and optimal device-design parameters for this promising potential post-CMOS logic device. [ABSTRACT FROM PUBLISHER]

This paper presents a new class of charge-trap Flash memory device with resistive switching mechanisms. We propose a fused memory scheme using a structure of metal/\Pr0.7 \Ca0.3\MnO3 (PCMO)/nitride/oxide/silicon to graft fast-switching features of resistive random access memory onto high-density silicon/oxide/nitride/oxide/silicon memory structures. In this scheme, both program and erase (P/E) are performed by the conduction of the carriers that are injected from the gate into the nitride layer through the PCMO, which is a resistive switching material; the resistance state determines whether a program or erase function is performed. In the proposed memory devices, we observed improved memory characteristics, including the current–voltage hysteresis having a resistive ratio exceeding three orders of magnitude at a set voltage of \pm4.5 V, a memory window of 2.3 V, a P/E speed of 100 ns/1 ms, data retention of ten years, and endurance of \10^5 P/E cycles. This approach will offer critical clues about how one can best implement universal features of nonvolatile memories in a single chip. [ABSTRACT FROM PUBLISHER]

A novel solid-electrolyte nonvolatile switch that we previously developed for programmable large-scale-integration circuits turns on or off when a conducting Cu budge is formed or dissolved in the solid electrolyte. Cu+ ion migration and an electrochemical reaction are involved in the switching process. For logic applications, we need to adjust its turn-on voltage (VON), which was too small to maintain the conductance state during logic operations. In this paper, we clarified that VON is mainly affected by the rate of Cu+ ion migration in the solid electrolyte. Considering the relationship between the migration rate and VON, we replaced the former electrolyte, Cu2-αS, with Ta2O5, which enabled us to appropriately adjust VON with a smaller Cu+ ion diffusion coefficient. [ABSTRACT FROM AUTHOR]