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A comprehensive study on the dielectric modulated (DM) drift region for power devices is presented in this paper. The performance of this drift region structure is theoretically analyzed and compared with other two structures: conventional and superjunction. In this paper, a study is focused on switching performance. The C – V relationships during switching are analytically derived, and the depletion widths predicted by the proposed analytical model agree well with simulation in a wide reverse bias region. The switching energy loss is evaluated based on the analytical model and its accuracy is verified by 2-D simulations. An effective depletion charge QD is defined as E\mathrm {loss} / breakdown voltage (BV), from which a figure of merit (FOM) of R\mathrm{\scriptscriptstyle ON,\mathrm {sp}}{}^\ast QD is proposed to compare the performances of these different drift region structures, considering both the conduction and switching losses. The discussions in part I on Si and silicon carbide device structures are extended in part II to include FOMs. It is found that the DM drift region structures show better R\mathrm{\scriptscriptstyle ON,\mathrm {sp}} -BV tradeoffs compared with the conventional structures, but slighter inferior FOMs. However, DM structures are still attractive for applications, where switching loss is less critical than the conduction loss, such as low frequency or soft switching. [ABSTRACT FROM PUBLISHER]

In this paper, we demonstrate the linear conductance-change characteristics of a conductive-bridging RAM (CBRAM) to be employed as an artificial synapse device in neuromorphic systems. The CBRAM with a bilayer electrolyte structure (${\mathrm {Cu/Cu}}_{{2}-{x}}\text{S}$ / $\mathrm {WO}_{{3}-{x}}$ /W) exhibits analog switching behavior during the depression process due to the well-controlled dissolution of the conductive filament. To analyze the origin of this motion, we investigate the effective voltage applied to $\mathrm {Cu}_{{2}-{x}}\text{S}$ and $\mathrm {WO}_{{3}-{x}}$. Our findings reveal that $\mathrm {Cu}_{{2}-{x}}\text{S}$ , acting as a voltage divider, helps in suppressing the large voltage drop in $\mathrm {WO}_{{3}-{x}}$ , where the formation/dissolution of filament occurs. Furthermore, due to the diode-like characteristics of $\mathrm {Cu}_{{2}-{x}}\text{S}$ and the division of voltage drop between $\mathrm {WO}_{{3}-{x}}$ and $\mathrm {Cu}_{{2}-{x}}\text{S}$ , an optimum programming energy is applied to $\mathrm {WO}_{{3}-{x}}$ during the depression process. This leads to linear conductance-change characteristics under identical pulses. However, abrupt conductance-change characteristics are observed during the potentiation process. Thus, we use only the device characteristics of the depression part for the neuromorphic system. An excellent classification accuracy is achieved due to the linear conductance-change characteristics and optimized pulse conditions. [ABSTRACT FROM AUTHOR]

As a promising new generation of nonvolatile memory, HfO2-based resistive random-access memory (RRAM) has attracted extensive research. However, the problem of data retention has prevented its industrial production as embedded memory. In this paper, from the microscopic understanding, a Monte Carlo simulator is developed to investigate the effects of an oxygen reservoir layer (ORL) on the resistance instability of HfO2-based RRAM. The evolution of conductive filaments (CF) during the retention degradation is visualized by our simulation considering the physical mechanisms of oxygen ions absorbed and released by the ORL. The simulation results are further validated with experiments to provide the prediction of retention performance of RRAMs with different ORLs and operation schemes. [ABSTRACT FROM AUTHOR]

In this paper, the requirements of device cross section and aspect ratio (AR) are examined to facilitate steep switching in heavily doped 3-D multiple gate junctionless (JL) transistors. It is shown through well-calibrated simulations and physical insights that the sharp OFF-to- ON switching action is predominantly governed by the area of cross section (${A} _{\textsf {cross}}$) instead of the gate length. A 3-D JL architecture preferably oriented toward a planar topology, i.e., with wider fin and low AR, is conducive for steep switching as a greater bulk area is available for impact ionization. On the contrary, narrow vertical architectures with AR > 1 suppress ${A} _{\textsf {cross}}$ in the bulk and are less likely to support the steep current transition. Steep switching specific scaling methodology is showcased to attain a sharp increase in drain current with a sub-60 mV/decade swing in a tri-gate JL transistor along with an associated negative value of total gate capacitance. [ABSTRACT FROM AUTHOR]

In the study of resistive random access memory using GeTeOx film as the switching layer, the device performed excellent property of bipolar resistive switching (BRS), which could be gradually transformed to the complementary resistive switching (CRS) by varying SET process current compliance. The conductive filament conduction mechanism of BRS could be verified by electrical characteristics and reliable data fitting. Through increasing current compliance of the SET process, CRS could be achieved due to higher activity of oxygen vacancies originated from the intensified thermal effect. This paper was beneficial to understand the switching mechanisms of BRS and CRS and provide a method to realize interconversion. Moreover, it was also a potential and promising device to be applied in the neurosynaptic biomimetic field. [ABSTRACT FROM AUTHOR]

A new concept high-voltage pseudo-p-channel lateral double-diffused MOS (p-LDMOS) with multiple current paths for conduction is proposed and investigated in this paper. The proposed power device consists of two hole current paths (p-channel MOS device) and one electron current path (n-channel MOS device). The gate of the n-channel device is automatically controlled by an induced signal inside the chip, thus the proposed device can be considered as a p-LDMOS with more than 66.2% reduction of specific on-resistance in comparison with the conventional p-LDMOS device. Furthermore, the proposed device has a much better safe operation area, since the compensation of the electric flux density brought by electron and hole currents. [ABSTRACT FROM AUTHOR]

The focus of this paper is to understand the impact of the material properties of GaN, exploited using a vertical device, in power switching by estimating switching loss. The study was performed with a cascoded current aperture vertical electron transistor (CAVET). The normally OFF device was simulated and analyzed using a Silvaco ATLAS 2-D drift diffusion model integrated to SPICE-based circuit simulator. Besides evaluating the performance space and, hence, potential application space for GaN CAVETs, this paper presents significant accomplishment in establishing a device to circuit model, thereby, offering a reliable method of evaluating GaN-based power transistors. The accuracy of the model was established through the excellent agreement of simulated data with the data sheet specs of a commercial cascoded GaN high electron mobility transistor. The model was successfully applied to compare SiC MOSFETs with GaN CAVETs. A cascoded GaN CAVET has $2\times $ faster switching time, $3\times $ lower switching loss compared with standard commercial SiC MOSFET, owing to the higher electron mobility in GaN. Operating at frequencies of megahertz with low power loss, a GaN CAVET will, therefore, lead to smaller converter size and higher system efficiency. [ABSTRACT FROM PUBLISHER]

This paper investigates the impact of cell variability on the read performance of the one-selector one-resistor (1S1R) cross-point array. A variability-aware array-sizing analysis methodology is introduced, considering three independent variability sources, namely, the data pattern randomness, the selector variability, and the resistive switching element (RSE) variability. By analyzing the impact of each variability factor separately, we show that the data pattern randomness is not an important contributor for the read margin (RM) degradation. While the intrinsic RSE variability reflected in the narrowing of the ON/OFF RSE window degrades the RM, the selector variability adds to this further, mainly affecting the ON-state readout current, and causing extra RM degradation. To accommodate cell variability and guarantee acceptable read performance, additional cell performance margin is required. The 1S1R requirements are extrapolated for 1-Mb array, assuming variability-affected cells. It is found that, with a typical selector variability, a minimal RSE window of 5 and a selector half-bias nonlinearity of $\sim 8000$ are required to achieve at least 10% RM. [ABSTRACT FROM AUTHOR]

This paper presents a detailed numerical analysis of work-function modulated cylindrical gate metal–oxide–semiconductor field-effect transistor (MOSFET)-based CMOS inverter. Introduction of work-function modulation in the control gate of dual-material cylindrical gate MOSFET exhibits significant reduction in short-channel effects (SCEs) and threshold voltage. The analytic potential-based model of this device is developed by considering 2-D Poisson’s equation in the cylindrical coordinate system. Development of the numerical model is based on certain boundary conditions to study the electrostatic behavior effectively. The results thus obtained from the analytical model are in good agreement with the model developed in the TCAD simulator. Improved drain current, reduced threshold voltage, immunity against SCEs, lower circuit delay, and high-speed switching have made this device a leader in CMOS logic family. [ABSTRACT FROM AUTHOR]

Logic gates based on the resistive switching random access memory (RRAM) allow normally-off digital computing because of the nonvolatile nature of the RRAM switch [1]. An extremely small area consumption can be achieved because of the 2–terminal structure of the RRAM switch and its capability of 3-D stacking. However, the details of RRAM organization within the array must be thoroughly investigated. This paper discusses the array organization and the select/unselect schemes of the RRAM logic circuits. We demonstrate a 1-bit adder to support the high functionality of RRAM logic. These results support RRAM as a promising technology for nonvolatile logic circuits beyond CMOS. [ABSTRACT FROM AUTHOR]

This paper presents an extensive investigation of the properties of the trap with activation energy equal to 0.6 eV, which has been demonstrated to be responsible for current collapse (CC) in AlGaN/GaN HEMTs. The study was carried out on AlGaN/GaN HEMTs with increasing concentration of iron doping in the buffer. Based on pulsed characterization and drain current transient measurements, we demonstrate that for the samples under investigation: 1) increasing concentrations of Fe-doping in the buffer may induce a strong CC, which is related to the existence of a trap level located 0.63 eV below the conduction band energy and 2) this trap is physically located in the buffer layer, and is not related to the iron atoms but—more likely—to an intrinsic defect whose concentration depends on buffer doping. Moreover, we demonstrate that this level can be filled both under OFF-state conditions (by gate-leakage current) and under ON-state operation (when hot electrons can be injected to the buffer): for these reasons, it can significantly affect the switching properties of AlGaN/GaN HEMTs. [ABSTRACT FROM AUTHOR]

This paper presents low insertion loss, high isolation, ultra-wideband double-pole-double-throw (DPDT) switch matrix designed in a 0.13- \mu \textm commercial high resistivity trap-rich silicon-on-insulator (SOI) CMOS process for the first time. The switches are designed using series–shunt–series configuration in a ring-type structure with input and output matching networks. Transistor width and transistor channel length effects on the wideband DPDT switch performance are thoroughly investigated. The designed switches achieve widest bandwidth from dc to 30 GHz with a low insertion loss of 2.5 dB and a high isolation of 32 dB up to 30 GHz. The measured input P1dB of designed switches is higher than 18 dBm. It was found both second and third harmonics can be improved by widening switch transistor channel width, and third harmonic can be improved by shortening channel length. The active chip area of designed $2 \times2$ switch matrix is very small size of only 0.28 mm $\times0.21$ mm. [ABSTRACT FROM PUBLISHER]

Current collapse is a phenomenon that increases the channel resistance during the switching process when the high gate and drain voltages are applied. The effect can be found from GaN-based high-electron mobility transistors (HEMTs) and is an obstacle for their applications to power electronics. There have been numerous reports on suppressing current collapse using semiconductor process technologies. In this paper, an enhancement mode (E-mode) AlGaN/GaN/AlGaN double heterostructure was proposed. The current collapse phenomena were studied on devices of E-mode MIS and Schottky gate HEMTs. The results indicate the suppression of current collapse for devices with double heterostructure. [ABSTRACT FROM AUTHOR]

Vertical alignment liquid crystal (LC) cell driven by in-plane field with 3-D polymer network exhibited no pooling mura under an external mechanical pressure; however, the operating voltage of the device was increased, because the polymer network hinders field-induced reorientation of LC. In this paper, we adopted a modified cell structure in which a counter electrode on top substrate of the conventional mode is existed, to improve upon this drawback. The proposed device in which the polymer network is formed in bulk of vertically aligned LC layer shows a very fast response time of 2 ms (rise + decay), 57% reduction in operating voltage, and also keeps image quality although the cell is curved. [ABSTRACT FROM AUTHOR]

Resistive switching memory (RRAM) features many optimal properties for future memory applications that make RRAM a strong candidate for storage-class memory and embedded nonvolatile memory. This paper addresses the cycling-induced degradation of RRAM devices based on a HfO2 switching layer. We show that the cycling degradation results in the decrease of several RRAM parameters, such as the resistance of the low-resistance state, the set voltage V\mathrm{ set} , the reset voltage V\mathrm{ reset} , and others. The degradation with cycling is further attributed to enhanced ion mobility due to defect generation within the active filament area in the RRAM device. A distributed-energy model is developed to simulate the degradation kinetics and support our physical interpretation. This paper provides an efficient methodology to predict device degradation after any arbitrary number of cycles and allows for wear leveling in memory array. [ABSTRACT FROM AUTHOR]

Due to outstanding properties of silicon carbide (SiC) and unipolar current conduction mechanism, the active chip size of SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) is significantly shrunk, which significantly improves switching performance. However, the termination region cannot be scaled down due to the existence of high breakdown electric field enclosing active region. Therefore, a SiC MOSFET switching loss model considering termination region effect is proposed in this paper with revealing physical insights into termination region during switching process. Furthermore, through theoretical analysis, model establishment, and simulation results, the loss breakdown under various blocking voltages (800, 1000, and 1200 V) for 1-, 3-, and 6-A current rated devices is obtained. ${E}_{\textsf {term}}$ and ${E}_{\textsf {acti}}$ as intrinsic loss of turn-on process make a significant contribution to the total switching loss under fast gate drive condition. The model shows that the turn-on and turn-off losses are under and overestimated, respectively, by using the commonly used electrical measurement. The loss from termination region aggravates the underestimation of turn-on loss and overestimation of turn-off loss further. The proposed loss estimation equation could provide accurate loss to help choose device and design power circuit for power electronic community. The results also raise new perspective to edge termination of efficient/reliable SiC MOSFET for device people. [ABSTRACT FROM AUTHOR]

Resistive random access memory (ReRAM), a new emerging nonvolatile memory technology based on changes in electrical resistivity of a dielectric film, offers promising advantages such as scalability, fast switching, and low operation voltage. However, for ReRAM to become a successful technology, it is necessary to accurately control the stochastic nature of the conductive nanoscale filaments (CNFs) that governs the resistive switching (RS) behavior of the device and limits its long-term stability and reliability. In this paper, we developed a highly scalable nanostructured/textured electrode that is composed of an array of Al nanotips based on an anodic aluminum oxide template. The nanotips improve the RS characteristics by intensifying the electric field at the apex of each nanotip which is demonstrated using numerical simulations. The localized electric field induces the repetitive nucleation/ formation/rupture of the CNFs in a more controlled fashion compared to a flat Al electrode. As a result, the nanotip sample exhibits uniform and reduced forming/reset voltages as low as 4.70 ± 0.98V/1.00 ± 0.19 V, stable endurance, and long-term retention. As a result, we were able to achieve ultralow-power and error-free operation of 100 cells covering a large area, significantly demonstrating improved uniformity and reliability compared to devices made using flat Al electrodes. This universal bottom-up strategy of self-organized nanostructured-electrodes provides a pathway toward large-scale, highly reliable, and RS memory devices. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel technique of realizing discrete-time (D-T) signal amplification using Nano-Electro-Mechanical systems (NEMS). The amplifier uses mechanical switches instead of traditional solid-state devices and acts as an inherent sample and hold amplifier. The proposed NEMS D-T amplifier operates on a wide dynamic range of signals without consuming the dc power. Moreover, the proposed amplifier does not suffer from the leakage current and the nonlinearity associated with the sampling ohmic switch. As a proof of concept, the proposed NEMS D-T amplifier is demonstrated in circuit simulations using the calibrated verilog-A models of the NEMS device. The simulated amplifier achieves a gain of ~5, handles the maximum differential input signal of 0.65 V, and consumes only $0.6~\mu \text{W}$ of power for a sampling frequency of 100 kHz. The nonidealities present in the proposed amplifier are highlighted and possible ways to overcome them are discussed. Finally, the design considerations required for the NEMS D-T amplifier are described. [ABSTRACT FROM AUTHOR]

In this paper, a distributed circuit model for on-die power distribution network in single and 3-D ICs is developed, and a set of difference equations are derived based on the circuit model and numerically solved using the finite-difference method. Both IR-drop and simultaneous switching noise, two components of power supply noise (PSN), are iteratively solved in time domain, thereby enabling a transient analysis of PSN. Under the assumptions that on-die power/ground pads, power density, and decoupling capacitors are uniformly distributed, PSN within a unit cell is accurately simulated with <1% error compared with HSPICE simulation. By reducing modeling grid fineness, the numerical modeling approach is applied to a full chip that has multiple blocks with nonuniform power/ground pads, power density, and decoupling capacitance density. Based on full-chip modeling, the PSN distribution of a two-die stack is simulated, and the impact of increasing decoupling capacitance and power/ground pads is investigated. [ABSTRACT FROM PUBLISHER]

GaN-based devices are seen as ideal candidates for power-switching applications. For the acceptance of GaN-based devices by module designers, obtaining enhancement-mode (e-mode) behavior in GaN-based heterostructure field-effect transistors (HFETs) has long been in the focus. Although the gate-injection approach appears to be the most promising one to achieve e-mode devices, using a double heterostructure in conjunction with a gate insulator has still its advantages, such as steeper turn-ON characteristics and lower leakage currents. An analytical expression to predict the threshold voltage V\mathrm {th} for a given double heterostructure device has not yet been derived. Moreover, neither an evaluation of the tradeoff between V\mathrm {th} and ON-state resistance $R_{{\text {ds}},\mathrm {\scriptstyle {{ON}}}} has been performed to date. This paper addresses these two aspects. We will show an analytical expression for a metal–insulator–semiconductor double HFET (MIS-DHFET), which in certain cases is also valid for the gate-injection transistor. On the basis of this, we will discuss the actual influence of the Al concentration in the backbarrier on V\mathrm th . We will further employ technology computer aided design (TCAD) device simulations to evaluate the impact on R{\text {ds},\mathrm {\scriptstyle {{ON}}}} when using MIS-DHFETs. It will be shown that by implementing a double heterostructure in MIS devices, it is possible to suppress the typically observed negative V\mathrm {th} –oxide thickness relationship while maintaining a constant $R_{{\text {ds}},\mathrm {\scriptstyle {{ON}}}}$ . [ABSTRACT FROM AUTHOR]

This paper presents the development of electrostatically actuated polymer-based microelectromechanical relays as a potential replacement for organic field-effect thin-film transistors in order to enable near-zero-power flexible transparent large-area electronics. A low-temperature five-mask surface-micromachining process is developed to fabricate two types of prototype relays: purely polymeric and partially polymeric (inorganic–organic hybrid) relays. Experimental results demonstrate the operation of the prototypes as a switch, showing immeasurably low OFF-state leakage current ( $\sim 10$ fA), abrupt switching behavior and high ON/OFF-current ratio (>105 over an effective input voltage swing of ≤100 mV), small hysteresis voltages (≤100 mV), and low contact adhesive forces (<10 nN/ \mu \text{m}^{2}) . The influence of temperature on switching characteristics, including hysteresis voltages, is investigated as well. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the influence of the drain electrode on the dynamic switching behavior of AlGaN/GaN high-electron-mobility transistors on Si substrate. By adding a field plate to the drain electrode, a dramatic increase in the dynamic ON-resistance dynR \mathrm{\scriptscriptstyle ON} was identified. The dispersion effect is correlated with the high electric field below the drain field plate (DFP), the onset of which is caused by the full electron depletion from both the channel and the GaN cap layer. We show that the electron distribution is modified by the passivation method, backside bias, or surface charges and, hence, shifts the onset voltage of the trapping effect. Trapped electrons underneath the DFP are thought to be responsible for the measured rise of the dynR \mathrm{\scriptscriptstyle ON} . With the introduction of an extended ohmic drain contact, the influence of a metallization overhang at the drain edge can be suppressed. The detrapping energies associated with the surface defects were determined to 0.2, 0.3, and 0.7 eV, respectively. Simulations and measurements indicate that charges inside the passivation below the DFP worsen the switching behavior. [ABSTRACT FROM AUTHOR]

The modular multilevel converter (MMC) is the most promising converter topology for medium- and high-power applications. One of the main concerns in the operation of the MMC, particularly for high-power applications, is its efficiency, which should be maximized. Silicon Carbide (SiC)-based devices have the potential to provide significant efficiency improvement compared with silicon devices. However, the possibility and impact of using SiC-based devices instead of silicon devices for high-power conversion have not been thoroughly explored. This paper reports on the results obtained from a detailed study to evaluate the performance of MMCs based on medium-voltage SiC MOSFETs and diodes with hybrid MMCs that employ silicon IGBTs and SiC diodes. The results are based on detailed circuit simulations that use simple physics-based circuit models. The study suggests the potential for significant efficiency gain for MMCs based on SiC power devices. [ABSTRACT FROM AUTHOR]

The figure of merit (FOM) of a semiconductor device represents an important quality as it pertains to its performance limits and is often used to drive the technology development in a specific direction. Comparing the performances of switching power MOSFETs using their FOMs has become ubiquitous practice in power semiconductor and power electronics industries. In this paper, a critical review of the proposed power MOSFET FOMs is presented, and key limitations are discussed. It is shown that the quality factor ${Q}_{F2}={(}{\lambda {E}_{c}}/{R_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}}{)}$ along with ${Q}_{G}$ and ${T}_{j\textsf {max}}$ may be used to guide the development of future generations of power semiconductor device technologies for power electronics switching applications, where $\lambda $ and ${E}_{c}$ are the thermal conductivity and critical electric field strength for the avalanche breakdown of the semiconductor material, respectively, ${R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ is the specific on-state electrical resistance, ${Q}_{G}$ is the gate charge, and ${T}_{j\textsf {max}}$ is the maximum junction temperature of the semiconductor power device, respectively. [ABSTRACT FROM AUTHOR]

The accurate calculation of switching voltage (${V}_{s}$) is necessary for the reliable and low-power operation of monolithic 3-D (M3D) CMOS-nanoelectromechanical (NEM) hybrid reconfigurable logic circuits because ${V}_{s}$ corresponds to the operating voltage (${V}_{\text {dd}}$) of NEM memory switches. In this paper, based on the Euler–Bernoulli equation, the physics-based analytical model is proposed to determine ${V}_{s}$. The accuracy of the proposed model is verified by both the finite-element analysis and experimental results. Our proposed model shows >3% error compared with experimental data. Also, the design guidelines of NEM memory switches are presented in terms of minimum ${V}_{s}$ (${V}_{s\_{}{m}}$) and device dimensions. [ABSTRACT FROM AUTHOR]

Mott materials have been investigated since late 1950s for their remarkably abrupt insulator to metal transition (IMT) in response to changes in temperature, strain, or electrical stimulus. Interest in these materials has been revived by recent demonstration of nanosecond-scale switching along with reproducible and fully reversible transitions in VO2-based thin film devices. These phenomena make VO2-based Mott insulator devices technologically relevant for various applications, such as memory selectors, logic switches, and building blocks for neuromorphic computing. Several groups have provisionally attributed the IMT switching to Joule heating. However, an electrothermal device simulation framework that self-consistently reproduces IMT phase transition, and in addition, explaining a variety of electrical/optical phenomena associated with IMT is still lacking. In this paper, we develop a self-consistent electrothermal device simulation framework which captures these key experimental attributes of IMT using VO2 as a model material. This framework will enable predictive modeling as well as provide insight on switching mechanisms and design of novel Mott insulator devices. [ABSTRACT FROM AUTHOR]

This paper analyzes write errors in spin-torque switching due to thermal fluctuations in a system with perpendicular magnetic anisotropy. Prior analytical and numerical methods are summarized; a physics-based general 2-D Fokker–Planck equation (FPE) is solved numerically. Due to its computational efficiency and broad applicability to all switching regimes and system symmetries, the 2-D FPE has been used to study the relation between write error slope and material parameters as well as some emerging switching schemes. [ABSTRACT FROM PUBLISHER]

In this paper, indium-tin-oxide (ITO) was used to act as both insulator and top electrode in resistive random access memory (RRAM) on identical bottom substrates. This is achieved by cosputtering an ITO target with nitride (N2) or oxygen (O2) gas as the insulator; then capping by an ITO electrode, such that both the rectifier and RRAM characteristics can be achieved before and after a forming process, respectively. In contrast, using pure ITO as an insulator does not exhibit RRAM behavior. To verify the rectifier and RRAM characteristics, material analyses and electrical measurements at various temperatures were conducted. Reliability tests including retention and endurance were also applied to verify the resistance switching stability. Finally, the rectifier and RRAM conduction models were proposed to examine the resistance switching behaviors. By applying the ITO material as both electrode and insulator, the resistance switching characteristic with high reliability is thus obtained. [ABSTRACT FROM AUTHOR]

Disordered ionic-bonded transition metal oxide thin-film transistors (TFTs) show promise for a variety of dc and RF switching applications, especially those that can leverage their low-temperature, substrate-agnostic process integration potential. In this paper, enhancement-mode zinc-oxide TFTs were fabricated and their switching performance evaluated. These TFTs exhibit the drain-current density of 0.6 A/mm and minimal frequency dispersion, as evidenced by dynamic current–voltage tests. A high-frequency power switch figure of merit $R_{{\mathrm{\scriptscriptstyle ON}}}Q_{G} of 359 \textm\Omega \,\cdot \, nC was experimentally determined for 0.75- \mu \textm long-channel devices, and through scaling 45.9 \textm\Omega \,\cdot \, nC is achievable for 11 V-rated devices (where R\mathrm{\scriptscriptstyle ON} is ON-state drain–source resistance, and QG is gate charge). An RF switch cutoff frequency fc of 25 GHz was measured for the same 0.75- \mu \textm TFT, whereas fc exceeding 500 GHz and power handling in the tens of watts are projected with optimization. [ABSTRACT FROM AUTHOR]

In this paper, we present a compact model for metal–oxide-based resistive random access memory (RRAM) devices with bipolar switching characteristics. The switching mechanism relies on the dynamics of conductive filament growth/dissolution in the oxide layer. Besides the dc and pulsed $I$ – $V$ characteristics, the model also captures the RRAM retention property and the temperature dynamics. The model parameters and the device variations are calibrated from the experimental data of IMEC HfOx-based RRAM devices. The model has been implemented in Verilog-A, which can be easily adapted into the SPICE simulator for the circuit-level analysis. As case studies, we demonstrate the model’s applications on the programming scheme design of the 1-transistor-1-resistor array, as well as the design space exploration of the 1-selector-1-resistor cross-point array toward megabit-level. [ABSTRACT FROM PUBLISHER]

This paper deals with the design of an ac switch structure for specific ac mains applications 230 V–50 Hz. The targeted power level is about a hundred watts, and the currently used converter circuits make use of bidirectional switches that are realized using anti-series connected MOS transistors. Despite the improvements in performance provided by some of these structures, their fabrication cost is still high and limits their widespread diffusion in a market shared with the triac. To replace the triac, an original current and voltage bidirectional bipolar device called a Bipolar ac (Bipac) is proposed, designed, realized, and characterized. It can be controlled both to turn-on and turn-off with respect to a single reference electrode. It exhibits a very low ON-state voltage drop that makes it interesting for specific mains applications with low load current (0.5 $\text{A}_{{\text {rms}}}$). The study of the Bipac structure is carried out using 2-D Sentaurus physical simulations. The Bipac structure is realized on n-type and on p-type substrates for two different wafer thicknesses. The operating modes of the monolithic bidirectional Bipac switch were validated through electrical characterizations. [ABSTRACT FROM AUTHOR]

To extend the scaling of digital integrated circuits, beyond-CMOS approaches based on advanced materials and novel switching concepts are strongly needed. Among these approaches, the resistive switching random access memory (RRAM) allows for fast and nonvolatile switching at scalable power consumption. This work presents functionally complete logic gates based on RRAM technology. Logic computation is obtained through conditional switching in RRAM circuits with serially connected switches. AND, implication, NOT, and bit transfer operations are demonstrated, each using a single clock pulse, while other functions (e.g., OR and XOR) are achieved in multiple steps. The results support RRAM logic for normally-off digital circuits with extremely high density. [ABSTRACT FROM AUTHOR]

10 kV, 2 A SiC p-i-n diodes have been designed and fabricated. The devices feature excellent stability of forward characteristics and robust junction termination with avalanche capability of 1 J. The fabricated diodes have been electrically evaluated with respect to dynamic ON-state voltage, reverse recovery behavior, bipolar stability, and avalanche capability. More than 60% reduction of losses has been demonstrated using newly developed 10-kV p-i-n diodes in a multikilowatt high voltage, high-frequency dc/dc soft-switching converter. [ABSTRACT FROM AUTHOR]

Using a commercial self-consistent Poisson–Schrödinger solver with the built-in possibility of allowing elastic energy minimization, the strain and the sheet charge density induced at the pseudomorphically grown Ga-face Wurtzite AlGaN/GaN heterojunctions are evaluated in the context of 3-D simulation of heterostructure field-effect transistor (HFET) epilayers etched into a variety of isolation-feature sizes and geometries. Through these studies and in the presence of surface states, the extent of the relevance of strain minimization in the vicinity of the unconstrained boundaries of isolation features of different degrees of roundness and perimeter-to-area ratio to threshold-voltage engineering is assessed. Although it is demonstrated that threshold-voltage shift caused by this induced strain minimization is smaller than the amount of shift levied by the depleting effect of the negatively charged states on the sidewall facets, it is shown that the reduction of the isolation-feature size is capable of substantially reducing the average trace of the stress tensor across such heterointerfaces. Considering the importance of this factor to the long-term reliability of AlGaN/GaN HFETs, especially when undergoing self-heating at high-power levels, use of alternative isolation features such as small islands of a lateral area less than 1000 nm2 is proposed as a solution. [ABSTRACT FROM AUTHOR]

A new oscillational phenomenon has been found in high-biased semi-insulating (SI) 4H-SiC photoconductive semiconductor switches (PCSSs) with high densities of vanadium and nitrogen dopants, and this oscillational phenomenon has no relationship with the laser wavelength, bias voltage, the charge capacitor, and the shape/size of the 4H-SiC PCSS. This paper shows that the photo activated charge domain theory in SI GaAs PCSS may explain this phenomenon. Due to the high densities of vanadium and nitrogen dopants, the intervalley scattering may occur in the 4H-SiC PCSS, and the space charge field region will appear in the 4H-SiC PCSS for the electrons accumulation. This region looks upon an equivalent capacitor, when the accumulation of the electrons is over, the equivalent capacitor will discharge, and the oscillational phenomenon appears. [ABSTRACT FROM AUTHOR]

A large-signal circuit model is used to compute the switching time for double-barrier resonant-tunneling diodes. The model consists of linear circuit elements plus a nonlinear $I$ – $V$ characteristic. The linear elements include a series resistor, a capacitor, and an inductor. The capacitance considers the charge accumulation, depletion in spacer layers, as well as charging-discharging of the quantum-well (QW) region. The inductance accounts for the delay of the current with respect to the voltage across the QW during the abrupt switching transition through the negative differential resistance region. A second-order Runge–Kutta method is used to solve for the switching transient, and then fit to experimental data for a high-quality InGaAs/AlAs resonant tunneling diode (RTD) using the QW inductance as a fitting parameter. Excellent agreement is found for the 10%–90% switching time with a calculated capacitance of 98 fF and a fitted inductance of 1300 pH. This large-signal inductance is approximately $7\times $ greater than the small-signal inductance that has been successfully used to predict the fmax of RTDs such as the one tested here. [ABSTRACT FROM PUBLISHER]

Although Marx-bank connection of avalanche transistors is widely used in applications requiring high-voltage nanosecond and subnanosecond pulses, the physical mechanisms responsible for the voltage-ramp-initiated switching of a single transistor in the Marx chain remain unclear. It is shown here by detailed comparison of experiments with physical modeling that picosecond switching determined by double avalanche injection in the collector–base diode gives way to formation and shrinkage of the collector field domain typical of avalanche transistors under the second breakdown. The latter regime, characterized by a lower residual voltage, becomes possible despite a short-connected emitter and base, thanks to the 2-D effects. [ABSTRACT FROM PUBLISHER]

A two-point expression of effective drive current ( Ieff\PG) for pass-gate (PG) transistors is proposed for the first time. We demonstrate that the proposed expression of Ieff\PG estimates the PG latency with a reasonable accuracy (relative error <15%) under different technology nodes from 90 to 20 nm and a wide range of biasing conditions including gate overdrive voltage up to 0.4 V and nonzero body bias between −0.3 and 0.3 V. The effective drive current expression is simple to use, independent of process technologies, and maintains accuracy when transistors are scaled down to deep submicron regime with severe nonidealities such as drain-induced barrier lowering. Ieff\PG provides a simple yet efficient approach for technology evaluation and projection for PG heavy applications such as field-programmable gate array routing. We also show that the previously proposed static CMOS effective drive current ( Ieff\inv) is not a valid figure of merit when applied to PG transistors, because PG transistors operate in a different regime from the transistors in CMOS inverters. The scaling trend of Ieff\PG is discussed, which illustrates the Ieff\PG does not improve from device scaling as much as CMOS saturation current ( $I_{{\mathrm{dsat}}})$ and effective drive current ( Ieff\inv) do. [ABSTRACT FROM PUBLISHER]

This paper investigates the impact of threshold switching (TS) selector characteristics on the one-selector one-resistor (1S1R) cross-point array performance. TS selector parameter requirements are extracted for 1 Mb array, considering 1S, 1R cell compatibility, read/write margin, and power consumption constraints. The SPICE simulation results show that the threshold voltage ( V\mathrm {\mathbf {th}} ) and the ON-state resistance ( Rs ) are important selector parameters. Low V\mathrm {\mathbf {th}} eliminates 1R disturb issue during the read operation, but this comes at the expense of losing full cell nonlinearity (NL) during the write operation. Increase of V\mathrm {\mathbf {th}} and Rs improves the full cell NL and alleviate read disturb issue. However, these reduce 1S1R read window and additional voltages are required for both read and write operations. Compared with selector with nonabrupt current-voltage ( $I$ – $V$ ) characteristics, the TS selector is more favorable for the low-voltage operation. Finally, different reported TS selectors are evaluated, and the improvement directions are suggested. [ABSTRACT FROM PUBLISHER]

A nonvolatile and programmable routing switch featuring two-varistor selected complementary atom switch (2V-1CAS also known as via-switch) is evaluated. The a-Si/SiN/a-Si varistor as a selector for the atom switch shows superior nonlinear current–voltage characteristics with high selectivity of ~105, which originates from the staircase barrier height in the layers. The two control lines connected to the varistors realize multiple fan-outs of the crossbar switch without select transistors. The $50\,\,\sf \times20$ crossbar switch block is demonstrated, where the atom switch is placed at each cross point and programmed through the varistors. The developed via-switch crossbar switch is a strong candidate for achieving energy-efficient nonvolatile field-programmable gate array in the Internet-of-Things applications. [ABSTRACT FROM AUTHOR]

Amorphous Ge15Te80–xIn5Agx ($6\le {x} \le24$) thin films prepared in sandwich geometry exhibit memory switching behavior unlike the bulk sample that has shown both threshold switching for less current (1–2 mA) and memory switching for current greater than 2 mA. As anticipated, the threshold voltage of Ge15Te80–xIn5Agx($6\le {x} \le24$) thin films is found to be lower as contrast to those of bulk counterparts. The compositional dependence of amorphous system shows an extensive plateau in the range of $\textsf {6} \le {x} \le \textsf {12}$ which literally stands for the intermediate phase after which there is a drastic increase in the threshold field. Shifted rigidity percolation threshold has also been confirmed from the compositional dependence of threshold field of amorphous Ge15Te80–xIn5Agx thin films. In addition, the optical bandgap of a-Ge15Te80–xIn5Agx thin-film sample has been reckoned considering absorption spectra, and the compositional dependence has been described based on average bond energy of the system. [ABSTRACT FROM AUTHOR]

Different source field plate (FP) connections are compared for the all-GaN integrated cascode device to address the capacitance matching and turn-off controllability issues reported in the conventional GaN plus Si cascode. The experimental results suggest that the cascode device with an FP connected to the source terminal can significantly suppress the off-state internode voltage, leading to minimized capacitive energy loss and reduced overvoltage stress at the internode. This is attributed to the reduced ratio of the drain–source capacitance of the depletion mode cascode part to the total capacitance at the cascode internode. An additional FP on the E-mode cascode part is proposed to further suppress the off-state internode voltage and benefit the device. Cascode devices with the source FP connecting to the enhancement mode gate have an improved switching controllability via gate resistance during turn-off and hence enhanced dv/dt immunity in the drain loop. [ABSTRACT FROM AUTHOR]

A normally-OFF p-GaN gate AlGaN/GaN high-electron-mobility transistor with high ON-state resistance (${R}_{ \mathrm{\scriptscriptstyle ON}}$) uniformity was realized using a self-terminated digital etching technique. ${R}_{ \mathrm{\scriptscriptstyle ON}}$ uniformity control was improved by simultaneously using an AlN etching stop layer in an epitaxial design and a novel digital etching procedure. Digital etching includes the multiple-cycle oxidation and the wet etching of p-GaN layers and provides easy control of p-GaN removal depth and surface damage reduction at the gate-to-drain and gate-to-source spacing areas. Low-frequency noise and pulse measurements indicated that device surface traps and current collapse phenomena were suppressed. [ABSTRACT FROM AUTHOR]

A negative differential resistance fin-shaped field-effect transistor (NDR-FinFET) using a Pb(Zr0.52Ti0.48)O3 threshold selector (TS) is investigated. From the measured input transfer characteristic of NDR-FinFET, the following results are demonstrated: 1) superior reduction of off current by a factor of 350 (as compared to a baseline FinFET); 2) on current of NDR-FinFET comparable to that of the baseline FinFET; and 3) subthreshold slope of 3 mV/decade at 300 K. The operating principle of NDR-FinFET is demonstrated using MATLAB simulation. In the on-to-off and off-to-on switching processes, the existence of an unstable resistive switching region is verified through the comparison between simulation data and experimental results. The major device parameters that affect the formation of the unstable resistive switching region are revealed. Finally, it is proposed that: 1) lowering the hold voltage of the TS and 2) applying the drain voltage comparable to the threshold voltage can have the NDR-FinFET to work appropriately (i.e., not in unstable region). [ABSTRACT FROM AUTHOR]

The performance of electronic switching between multiple backward-wave modes is studied in a designed extended interaction oscillator (EIO) based on a ladder circuit with finite number of periods to overcome electronic tuning range limits of EIOs operated in standing-wave mode. The dispersion characteristic of the circuit with finite number of periods, which is constructed by a series of discrete modes, is investigated. The mode separation is analyzed and reduced to support continuous switching between multiple different modes by increasing the number of periods as compared with the standing-wave EIO approach. An output circuit is designed to extract the power of backward wave. The electronic switching between nine backward-wave modes has been achieved by changing the beam voltage from 4.1 to 10.5 kV, where the maximum output power over 58 W is obtained at 5.3 kV from the simulation prediction. The EIO can operate over an electronic tuning range of 3.53 GHz from 89.65 to 93.18 GHz in ensuring the output power no less than 20 W. This technique can be extensively applied to increase operating band for extended interaction klystrons (EIKs) and electronic tuning range for EIOs, making them more suitable for many potential applications. [ABSTRACT FROM AUTHOR]

A set/reset switching model of Cu atom switch based on electrolysis is newly proposed. A nanometer-thick solid electrolyte gives a high electric field of ~3.3 MV/cm in the solid electrolyte at 2 V, enabling an ionization of Cu and a formation of Cu bridge. It is revealed that the switching voltage depends on the resistance of electrolyte, where the modified Faraday’s law of electrolysis with exponential factors on current and time well falls on the experimental on-resistance. The proposed simple compact model is useful for estimating the resistance of the Cu atom switch programmed by any conditions. [ABSTRACT FROM PUBLISHER]

HfOx-based resistive switching device has been explored as one of the promising candidates for the electronic synapses of neuromorphic computing systems due to its high performance, low cost, and compatibility with CMOS technology. To meet the codesign requirement of HfOx-based electronic synapses with CMOS neurons in the neuromorphic computing systems, a compact model that can capture the synaptic futures of HfOx-based resistive switching device is developed. The developed model can accurately describe the multilevel conductance transition behaviors during RESET process for depression learning as well as the binary stochastic transition behavior during SET process for potentiation learning. After the verification with experimental data, the model is used to simulate a winner-take-all neural network to classify patterns with unsupervised competitive learning algorithm. Simulation results imply that the average recognition accuracy would decrease with the increase of the resistance variation of low resistance state (LRS) due to the “trap” effect. Guided by the simulation, a synapse cell consisted of a HfOX-based device and a fixed resistor series connection is proposed to achieve almost 100% recognition accuracy even if the resistance variation of LRS is 50%. [ABSTRACT FROM PUBLISHER]

A high-K/metal gate (HKMG)-stack (TiN/Al-doped-HfOx/SiO2/Si)-based bipolar resistive random access memory (RRAM) cell is proposed and fabricated by 28/20-nm HKMG CMOS compatible technology. Robust reliability behaviors (retention at 200~ ^\circ \text C > 4 \times 10^4 s and endurance $> 10^{{{5^{\vphantom {\frac {}{,}}}}}} cycles) and ultralow switching current ( <0.1\mu \textA for RESET and <0.3\mu \textA for SET) are both demonstrated. The sub- \mu \textA switching current and self-selection nonlinear $I$ – V$ characteristics are attributed to the SiO2 interfacial layer rather than the decrease of conductive filament size and oxygen vacancy ( V_{O} ) density, which can be verified by HRTEM and measured conduction behavior. Therefore, robust reliability property is also achieved. The demonstrated excellent memory characteristics of HKMG stacked RRAM cell enable constituting 1-Mb workable crosspoint array even though the feature size scales down to 10 nm according to the HSPICE simulation. [ABSTRACT FROM AUTHOR]

The resistive-switching memory (RRAM) is currently under consideration for fast nonvolatile memory thanks to its relatively low cost and high performance. A key concern for RRAM reliability is stochastic switching, which impacts the operation of the digital memory due to distribution broadening. On the other hand, stochastic behaviors are enabling mechanisms for some computing tasks, such as physical unclonable function (PUF) and random number generation (RNG). Here, we present new circuit blocks for physical RNG, based on the coupling of two RRAM devices. The two-resistance scheme allows to overcome the need of probability tracking, where the operation voltage must be tuned to adjust the generation probabilities of 0 and 1. Probability tests are proved successful for one of the three proposed schemes. [ABSTRACT FROM AUTHOR]

We present a physical circuit model of ferroelectric (FE) polarization switching for the analysis and design of hybrid FE-CMOS circuits. Stochastic geometry is applied to domain nucleation, growth, and coalescence under arbitrary voltage and current input signals. The circuit model is first constructed for ideal FE capacitors and then extended to the realistic effects of lateral scaling, anisotropic growth, and disorder in polycrystalline films. Reliability degradation by imprint and fatigue is also incorporated. The interaction of model parameters and circuit design for three different nonvolatile latch topologies is presented in Part II. [ABSTRACT FROM AUTHOR]