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Reliability is an important consideration during semiconductor technology development, which ensures that the performances of devices, circuits, and systems are maintained over a specified period of time, leading to successful products. Device reliability is at the core of overall product reliability, which continues to remain an important area of research and has attracted the attention of IEEE Transactions on Electron Devices (T-ED) authors and readers throughout the years. Device reliability can be classified into two broad areas: gradual drift of device performance over time or sudden failure, and both are of importance for logic, memory, RF, and power devices. Different aspects of device reliability are usually reported, such as the development of electrical or physical characterization methods, investigation and modeling of a particular phenomenon, impact of material and processes on reliability, and development of reliability tolerant technologies. [ABSTRACT FROM AUTHOR]

In this paper, we present a comprehensive reviewand discussion of the state-of-the-art device technology and application development of GaN-on-Si power electronics. Several device technologies for realizing normally off operation that is highly desirable for power switching applications are presented. In addition, the examples of circuit applications that can greatly benefit from the superior performance of GaN power devices are demonstrated. Comparisonwith other competingpower device technology, such as Si superjunction-MOSFET and SiC MOSFET, is also presented and analyzed. Critical issues for commercialization of GaN-on-Si power devices are discussed with regard to cost, reliability, and ease of use. [ABSTRACT FROM AUTHOR]

A dual-gate superjunction insulated gate bipolar transistor (IGBT) (DG-SJ-IGBT) is proposed and studied with numerical TCAD simulations. The new structure utilizes the superjunction structure as a controlling port for the strength of conductivity modulation inside the IGBT, so that a low VON is obtained by a strong conductivity modulation during ON-state and a near-unipolar turn-off is achieved by removing the minority carriers before the turn-off event. For this purpose, the p-pillar in the DG-SJ-IGBT is connected to the p-body using a built-in p-channel MOSFET. The primary gate and the auxiliary gate (i.e., gate of p-MOSFET) are controlled by two separate driving signals. In the IGBT’s ON-state, the p-MOSFET disconnects the p-pillar, enabling full conductivity-modulated bipolar conduction and a consequent low VON. As a well-known issue, conductivity modulation is accompanied by significant additional turn-off loss (EOFF). To overcome this issue, the DG-SJ-IGBT takes advantage of the p-pillar which extends through the entire drift region. Before the IGBT’s turn-off event, the p-MOSFET electrically grounds the p-pillar to the p-body. The grounded p-pillar serves as a hole extractor, suppresses the minority carrier density throughout the depth of the drift region, and brings the device into a near-unipolar conduction mode. Thus, a near-unipolar turn-off can be obtained, resulting in a low EOFF. [ABSTRACT FROM AUTHOR]

A cost-effective engineered bulk silicon (EBUS) substrate technology is presented, featuring p-n junction implemented on bulk Si substrates using mainstream ion implantation and thermal annealing processes. Standard p-GaN/AlGaN/GaN heterostructures are successfully grown on the EBUS substrate and used to fabricate 200-V enhancement-mode p-GaN gate HEMTs. By creating deep trenches in the EBUS substrate to isolate the local P+ silicon regions underneath the high-side (HS) and low-side (LS) power switches, adverse effects (e.g., back-gating and dynamic ON-resistance degradation) in the use of conventional bulk Si substrate are all eliminated. The mechanism of crosstalk suppression in the GaN-on-EBUS platform is revealed in comparison with conventional GaN-on-Si platform and verified by a series of designed tests. [ABSTRACT FROM AUTHOR]

Recently, a GaN reverse-conducting high-electron-mobility transistor (RC-HEMT) has been demonstrated. The RC-HEMT features built-in distributive Schottky contacts, which provide a low-loss freewheeling path. The RC-HEMT offers the same functionality as an HEMT/Schottky barrier diode (SBD) pair, but consumes much less chip area, thus its ${R}_{ \mathrm{\scriptscriptstyle ON}}$ (ON-resistance $\times $ total device width) is significantly reduced. Theoretically, ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of the RC-HEMT can approach that of an HEMT. In practice, due to certain geometry limitations, ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of an RC-HEMT lies between an HEMT/SBD pair and a single HEMT. This work investigates the factors that influence ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of the RC-HEMT using both experimental measurements and numerical simulations. It is found that ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of the RC-HEMT is strongly affected by the geometry of the source and channel regions, where HEMT sections and SBD sections are interdigitally distributed. With coarse patterning of these regions, ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of the RC-HEMT is close to the HEMT/SBD pair. Through proper geometry scaling, ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of RC-HEMT is reduced and approaches that of HEMT. [ABSTRACT FROM AUTHOR]

In this article, an ultrathin-barrier (UTB) AlGaN/GaN diode featuring metal–insulator–semiconductor (MIS)-gated hybrid anode (MG-HAD) and in situ Si3N4 cap passivation is demonstrated. The intrinsic turn-on voltage (VON) as low as 0.31 V determined by the as-grown AlGaN-barrier thickness (4.9 nm) is obtained and the VON exhibits excellent uniformity. More importantly, benefit from the MIS-gated hybrid anode structure, the UTB MG-HAD features good thermal stability in reverse blocking capability. The device delivers a substantially low leakage less than 1~μm/mm at −300 V at high temperature (HT) up to 200 °C, which is more than 100 × lower than that in the reference device w/o gate dielectric. Besides, the device exhibits respectably improved dynamic characteristics due to the incorporation of in situ Si3N4-cap passivation layer and remote plasma pretreatment (RPP) prior to Al2O3 gate dielectric deposition. The UTB MG-HAD featuring precisely VON modulation and low reverse leakage is of great interest for power electronic applications. [ABSTRACT FROM AUTHOR]

We conducted reliability characterization under reverse-bias stress (i.e., stress at OFF-state with high VDS) on the E-mode GaN metal–insulator–semiconductor field-effect-transistors (MIS-FETs) with various substrate terminations. The MIS-FETs with floating substrate (FS) show worse threshold voltage (VTH) stability than that with a grounded substrate. A non monotonic dependence of VTH shifts and OFF-state time-to-breakdown (tbd) on the positive substrate bias (Vsub) was also observed. The underlying mechanisms are the different impacts of positive Vsub on the drift of electrons and holes during the long-term stress. An important indication is that positive-biased and FS terminations should be restricted at OFF-state in order to obtain good VTH stability in applications of the GaN MIS-FET. [ABSTRACT FROM AUTHOR]

In this paper, systematic characterization and the corresponding suppression strategies of dynamic OFF-state leakage current (${I}_{ \mathrm{\scriptscriptstyle OFF}}$) in Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) are presented based on fast pulsed ${I}$ – ${V}$ measurement and consecutive switching measurement. It is found that the high ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ under dynamic pulse mode without hole injection is a result of the reduced voltage blocking capabilities (both lateral and vertical) with weaker trapping effect in the buffer, and the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ induced by ON-state hole injection is caused by further increased lateral conductivity through the buffer from source to drain. The corresponding behaviors under continuous waveforms with different switching conditions are analyzed to identify effective approaches for the suppression of dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ in practical switching operations. A higher temperature is shown to be beneficial to the reduction of the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ induced by ON-state hole injection. To completely eliminate the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ caused by ON-state hole injection and minimize the OFF-state power consumption in practical power switching applications, a sufficiently large negative OFF-state gate bias (e.g., ${V}_{\text {GS}, \mathrm{\scriptscriptstyle OFF}}\le -{3}$ V) is recommended in the gate driver turn-off voltage design for the Schottky-type p-GaN gate HEMTs. [ABSTRACT FROM AUTHOR]

In this paper, we carried out a systematic investigation on gate degradation and the physical mechanism of the Schottky-type ${p}$ -GaN gate HEMTs under positive gate voltage stress. The frequency- and temperature-dependent measurements have been conducted. It is found that the time-dependent gate degradation exhibits weak relevance with frequencies ranging from 10 to 100 kHz under dynamic gate stress and is similar to that in static gate stress. Both the gate breakdown voltage (BV) and mean-time-to-failure (MTTF) show positive temperature dependence. Moreover, the current–voltage (I–V) characteristics and threshold voltage (${V}_{\text {TH}}$) instability of ${p}$ -GaN devices before/after gate degradation are compared and analyzed. The degraded Schottky junction exhibits an ohmic-like gate behavior. It is revealed that under a large gate bias stress, high-energy electrons accelerated in the depletion region of the ${p}$ -GaN layer would promote the formation of defect levels near the metal/ ${p}$ -GaN interface, leading to the initial ${p}$ -GaN layer degradation. The subsequent high gate leakage density could cause the final degradation of the AlGaN barrier. [ABSTRACT FROM AUTHOR]

Low-loss reverse-conducting normally- OFF double-channel AlGaN/GaN power transistor with the built-in Schottky barrier diode (SBD) has been systematically studied. This device features the MOS-gate section and SBD-anode section paralleled to an interdigital layout along the gate width direction. A common access region that conducts current at both forward and reverse ON-states is employed, which is beneficial to reduce the conduction loss. With a MOS-HEMT/SBD finger width of ${4}~\mu \text{m}/2~\mu \text{m}$ and a total width ratio of 2:1, the device exhibits a threshold voltage of +0.8 V at a drain current of ${10}~\mu \text{A}$ /mm and a low forward ON-resistance of $12.1~\Omega \cdot \text {mm}$. The Schottky metal contacts 2-DEG directly, which results in a low reverse turn-on voltage of −0.6 V (at −1 mA/mm) and low reverse ON-state voltage of −1.7 V (at −50 mA/mm). A leakage suppression MOS field plate (FP) is applied to shield the Schottky contact from the strong electric field, leading to a low OFF-state leakage current of 14 nA/mm at +100-V drain bias and a high breakdown voltage (BV) of +698 V. The finger width and the number of fingers should be optimized. A narrow finger width benefits the current sharing at the access region, while the increasing number of fingers introduces more Schottky depletion regions along the gate width direction that degrade ${R}_{ \mathrm{\scriptscriptstyle ON}}$. [ABSTRACT FROM AUTHOR]

In this paper, we carried out a systematic comparison between the enhancement-mode GaN-based fully recessed metal-insulator-semiconductor field-effect transistors (MIS-FETs) and partially recessed MIS-high-electron-mobility transistors (MIS-HEMTs) with the same gate dielectric stack (LPCVD-SiNx/PECVD-SiNx) that has delivered promising long-term reliability and stability. Despite a moderately larger on-resistance (${R}_{ \mathrm{ON}}$), the MIS-FETs deliver superior ${V}_{\text {TH}}$ uniformity and thermal stability. Under long-term gate bias stress, both the MIS-HEMT and MIS-FET deliver similar small positive-bias temperature instability, while the negative-bias temperature instability of the MIS-HEMT is much larger than that of MIS-FET. The MIS-FET also delivers a higher ${V}_{\text {TH}}$ stability than the MIS-HEMT under dynamic gate bias stress. It is suggested that the differences in ${V}_{\text {TH}}$ stability mainly originate from the different spatial separation between the trap states and the conducting channel, with it being larger in MIS-HEMT than in MIS-FET. [ABSTRACT FROM AUTHOR]

A systematic analytical investigation of the charge distribution and gate control of the normally-off GaN double-channel MOS-HEMT (DC-MOS-HEMT) is presented in this paper. Compared to conventional GaN MOS-HEMT, the DC-MOS-HEMT features a thin AlN insertion layer (AlN-ISL) below the original two dimensional electron gas (2DEG) channel, thus forming a second channel at the interface between AlN-ISL and the underlying GaN. This paper reveals the impact of the AlN-ISL on the 2DEG distribution and the gate control of the channels. The sensitivity of ${V}_{\text {th}}$ against the recess depth is also analytically studied and is found to be nearly independent of the recess depth as long as the recess is terminated in the upper channel layer. The analytical results are well supported by numerical device simulations, and the physical mechanisms behind these findings are explained along with the analytical investigations. [ABSTRACT FROM AUTHOR]

(Al)GaN recess-free normally OFF technology is developed for fabrication of high-yield lateral GaN-based power devices. The recess-free process is achieved by an ultrathin-barrier (UTB) AlGaN/GaN heterostructure that features a natural pinched-off 2-D electron gas channel. The top–down manufacturing technique overcomes the challenges in etching of AlGaN barrier with well-controlled depth and uniformity, which is especially attractive for fabrication of normally OFF GaN-based high-electron-mobility transistors (HEMTs) and metal–insulator–semiconductor HEMTs (MIS-HEMTs) on large-size Si substrate. With SiNx passivation grown by low-pressure chemical-vapor deposition, on-resistance of the UTB-AlGaN/GaN-based power devices can be significantly reduced. High-uniformity low-hysteresis normally OFF HEMTs and Al2O3/AlGaN/GaN MIS-HEMTs are successfully demonstrated on the UTB AlGaN/GaN-on-Si platform. It is also a compelling technology platform for manufacturing high-performance GaN-based lateral power diodes, and normally OFF p-(Al)GaN heterojunction field-effect transistors. [ABSTRACT FROM PUBLISHER]

Bulk traps in the high-resistivity buffer stack underneath the 2-dimensional electron gas (2DEG), which can interact with the high vertical electric field at OFF state, impose a critical challenge to the dynamic ON-resistance (RON) of AlGaN/GaN-on-Si power devices. In this paper, the impact of substrate bias polarity on carrier injection/transport and buffer-induced current collapse has been investigated by using ramped and transient back-gating characterizations as well as TCAD simulations. High voltage applied to the conductive Si substrate can modulate 2DEG conductivity through the back-gate effect, whereby the dynamics of both acceptor and donor buffer traps are identified. Distinct buffer trapping and asymmetric vertical leakage under opposite top-to-substratebias polarities have been observed, which are attributed to the fundamentally different carrier injection/transport mechanisms. It is suggested that the energy barrier at the nucleation-layer/Si interface can limit the electron injection from Si substrate into the buffer stack and consequently influence the bufferrelated current collapse. [ABSTRACT FROM AUTHOR]

In this paper, we report a systematic study of the nitridation effects on GaN surface by first-principles calculations and X-ray/ultraviolet photoemission spectroscopy (XPS/UPS). According to the calculated electronic structures, two surface bands (i.e., the upper band and the lower band) can be seen within the bandgap for the typical surface configurations that may occur in the experimental condition as a result of surface reconstruction. By the deployment of sufficient nitridation, the energy positions of the lower band are modified toward the valence band by ~1 eV, resulting in the overlapping of the lower surface band with the valence band. Meanwhile, the upper surface band is also modified toward the valence band, but by a smaller amount. The modification to the positions of the surface bands is furthermore manifested by XPS/UPS spectra characterization performed on GaN sample that underwent surface treatment with low-energy remote N2 plasma. The theoretical and experimental results insightfully proclaim the nitridation effects on material properties at atomic level, and support a surface-state ionization model for the GaN band-edge (3.4 eV) emission in metal-AlGaN/GaN Schottky-on-heterojunction diode under forward bias. [ABSTRACT FROM PUBLISHER]

A p-type shield region (p-shield) under the gate trench is typically adopted in a SiC trench MOSFET for achieving a lower oxide field and reverse transfer capacitance ( Crss) . This paper comparatively studies the effects of a grounded p-shield and a floating p-shield. Device simulations using Sentaurus TCAD are carried out in this paper to reveal the devices’ internal dynamics. The floating p-shield can effectively reduce the OFF-state oxide field as a grounded p-shield does, without degrading its static performance. However, after being switched from the OFF-state, the ON-state oxide field in the trench MOSFET with a floating p-shield (FS-MOS) is dramatically elevated. Compared with the trench MOSFET with a grounded p-shield, the FS-MOS also exhibits a higher C{{\text {rss}}} and a consequently slower switching speed. Furthermore, the FS-MOS exhibits a degradation of dynamic R{ \mathrm{ON}} during switching operation. A charge storage mechanism is then presented to explain the dynamics in FS-MOS. Upon a high V{{\text {DS}}} , holes are emitted from the floating p-shield when the parasitic p-n-p structure consisting of p-shield, p-body, and n-region between them is punched through, leaving negative charges in the floating p-shield even when the high V{{\text {DS}}} is removed. Based on this mechanism, the behaviors of the FS-MOS are well explained. [ABSTRACT FROM AUTHOR]

In this paper, static and dynamic performances of an AlGaN/GaN-on-Si power FET utilizing the integrated photonic-ohmic drain (PODFET) were systematically investigated. The operational mechanisms of the PODFET, including both the conditions of photon generation and the related physical processes, were explained. The dynamic switching tests were carried out under two types of hard switching conditions. With the photon generation and channel current inherently switched ON and OFF in synchronization, the dynamic performances of the PODFET can be significantly enhanced owing to photon pumping of deep electron traps. In addition, the generated photons were proved to be confined in proximity of the drain terminal without causing adverse effects on the device performances (e.g., the OFF-state leakage degradation). [ABSTRACT FROM PUBLISHER]

A GaN/SiC hybrid field-effect transistor (HyFET) is proposed as a high-voltage power device that provides a high-mobility lateral AlGaN/GaN channel to reduce the channel resistance and a vertical SiC drift region to sustain the high OFF-state voltage. The performance of the HyFET is evaluated by numerical device simulations. Compared with the conventional SiC MOSFET, the HyFET exhibits a greatly reduced R\mathrm{\scriptscriptstyle ON} together with a low C\mathrm{ GD} and low gate charges. The figures of merit Q\mathrm{ G}\times R\mathrm{\scriptscriptstyle ON} and Q\mathrm{ GD}\times R\mathrm{\scriptscriptstyle ON} of the HyFET are dramatically improved. [ABSTRACT FROM AUTHOR]

In this paper, we systematically investigated the leakage and breakdown mechanisms of the low-pressure chemical vapor deposition (LPCVD) silicon nitride thin film deposited on AlGaN/GaN heterostructures. The LPCVD-SiNx gate dielectric exhibits low leakage and high breakdown electric field. The dominant mechanism of the leakage current through LPCVD-SiNx gate dielectric is identified to be Poole–Frenkel emission at low electric field and Fowler–Nordheim tunneling at high electric field. Both electric-field-accelerated and temperature-accelerated time-dependent dielectric breakdown of the LPCVD-SiNx gate dielectric were also investigated. [ABSTRACT FROM PUBLISHER]

The temperature dependence of current collapse (CC) in AlGaN/GaN high-electron mobility transistors on silicon substrate is studied in this paper. Devices without and with Si3N4 passivation are used to investigate the behavior of surface- and buffer-induced CC, respectively. It is found that the degree of surface-induced CC in unpassivated devices has a weak temperature dependence, which is induced by the cancelling out between enhanced carrier injection based on surface hopping and enhanced emission when the temperature is increased. On the other hand, the degree of buffer-induced CC in the Si3N4 passivated devices is reduced at higher temperature since the energy of hot electrons is reduced due to the phonon scattering and the trapping of hot electrons in the buffer is mitigated. Temperature-dependent transient measurement is also carried out to investigate the recovery process for these two type of CC. Two types of trap levels are identified in the unpassivated and Si3N4 passivated devices, respectively. The trap level $E1$ with an activation energy of 0.08 eV is supposed to be related to the surface trapping, while $E2$ with an activation energy of 0.22 eV is located in the buffer layer. [ABSTRACT FROM AUTHOR]

Effective interface trap characterization approaches are indispensable in the development of gate stack and dielectric surface passivation technologies in III-nitride (III-N) insulated-gate power switching transistors for enhanced stability and dynamic performance. In III-N metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) that feature a buried channel, the polarized barrier layer separates the critical dielectric/III-N interface from the two-dimensional electron gas (2DEG) channel and consequently complicates interface trap analysis. The barrier layer not only causes underestimation/uncertainty in interface trap extraction using conventional ac-conductance method but also allows the Fermi level dipping deep into the bandgap at the pinch-off of the 2DEG channel. To address these issues, we analyze the frequency/temperature dispersions of the second slope in capacitance-voltage characteristics and develop systematic ac-capacitance techniques to realize interface trap mapping in MIS-HEMTs. The correlation between ac-capacitance and pulse-mode hysteresis measurements show that appropriate gate bias need to be selected in the interface trap characterization of MIS-HEMTs, in order to match the time constant of interface traps at the Fermi level with ac frequency and pulsewidth. [ABSTRACT FROM AUTHOR]

We report the first gallium nitride (GaN)-based pulse width modulation (PWM) integrated circuit (IC) featuring monolithically integrated enhancement- and depletion-mode high electron mobility transistors and lateral field-effect rectifiers on the GaN smart power technology platform. The PWM IC is able to generate 1-MHz PWM signal with its duty cycle modulated effectively by a reference voltage ( Vc) over a wide range with good linearity. It features a 5 V supply voltage and is composed of a sawtooth generator and a comparator, both of which can be operated at 1 MHz and exhibit proper functionality over a wide temperature range (from 25 °C to 250 °C). This circuit demonstration further proves the feasibility of an all-GaN solution that features monolithically integrated peripheral gate control circuits and power switches for GaN power converters. An all-GaN solution would lead to a compact system with improved efficiency and enhanced reliability. [ABSTRACT FROM AUTHOR]

Al2O3–AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs) featuring indium tin oxide transparent gate electrode are fabricated for the purpose of evaluating the gate reliability. The transparent gate electrode allows electroluminescence (EL) observation in the region directly under the gate, which cannot be performed in conventional MIS-HEMTs with opaque gate electrode. Normally OFF transparent-gate MIS-HEMTs were realized by implanting fluorine ions into the AlGaN barrier prior to the deposition of Al2O3. The dependence of EL on bias condition was investigated with the color of EL resolved by filters. Gate dielectric degradation in MIS-HEMTs was induced by OFF state drain-bias stress, as detected by the increased gate leakage current. Location of the gate degradation could be clearly identified by EL imaging through the transparent gate. From the EL image, the passivation layer under the overhang of T-shaped gate is found to be vulnerable to OFF-state stress, which is confirmed by simulation. [ABSTRACT FROM AUTHOR]

We investigate in detail the influence of AlN passivation on dynamic ON-resistance ( \(R_{\mathrm{{\scriptstyle ON}}}\) ) and electric field ( \(E\) -field) distribution in high-voltage AlGaN/GaN high electron mobility transistors (HEMTs) on a Si substrate based on pulsed \(I\) – \(V\) measurements, electroluminescence (EL) microscopy, and 2-D physics-based numerical device simulations. It is found that the dynamic \(R_{\mathrm{{\scriptstyle ON}}}\) increase has been significantly suppressed to below 10% at various temperatures ranging from −50 to 200 °C owing to the effective and robust compensation of deep acceptor-like trap states at the AlN/GaN (passivation/cap) interface by the additional positive polarization charges induced in the epitaxial AlN thin passivation layer grown in a plasma-enhanced atomic layer deposition system. To the best of our knowledge, this is the first time that highly suppressed current collapse in an AlGaN/GaN HEMT on a Si substrate within a wide temperature range is ever reported. By monitoring the dynamic \(R_{\mathrm{{\scriptstyle ON}}}\) for 100 consecutive 133-kHz switching cycles, its variation is observed to be less than 2.5%, indicating excellent stability of the passivation effectiveness. The electric field in an AlN-passivated device is found to be well confined at the drain-side gate edge, as shown in EL measurement and numerical simulation results. This phenomenon directly suggests that the virtual gate effect arising from surface trap charging has been effectively alleviated by the AlN passivation technique. [ABSTRACT FROM AUTHOR]

On a GaN smart power integrated circuit (IC) platform, a highly linear (i.e., proportional to absolute temperature) temperature sensor IC is demonstrated for building voltage references as well as temperature compensation functional blocks. The circuit is designed based on the temperature-dependent characteristics of GaN-based peripheral devices (e.g., heterojunction Schottky barrier diode, enhancement-/depletion-mode high electron mobility transistors, and lateral field-effect rectifiers) that are monolithically integrated with high-voltage power devices. This monolithic integration scheme facilitates the design efforts in taking full advantages of GaN’s superior capability to operate at high temperatures. Proper circuit operation was demonstrated at 275 °C. [ABSTRACT FROM AUTHOR]