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To effectively solve the crosstalk issue in high-density crossbar array (CBA), high rectifying characteristics should be introduced in the resistance random-access memory (ReRAM) device, and in-depth understanding of the affecting factors on rectifying properties is essential for the large-scale application of ReRAM. In this paper, a high-performance self-rectifying device with CMOS compatible Pd/HfO2/TaOx/Ta structure was demonstrated in a 1-kb CBA. Forming-free, self-compliance, and high uniformity characteristics were successfully achieved. By modulating the thickness of the HfO2 rectifying layer, the rectifying ratio of device could be achieved as high as $\sim 2\times 10^{\textsf {3}}$ under ±3 V at low-resistance state (LRS). It was also experimentally confirmed that the selected unit cell in high-resistance state (logically the “ OFF” state) was stably readable when it was surrounded by unselected LRS (logically the “ ON” state) cells, in an array of up to $32 \times 32$ cells. Furthermore, a model based on interfacial barrier modulation and defects trapping/detrapping was proposed to elucidate the impact of the dielectric thickness on the self-rectifying characteristics of the device. The results presented in this paper provide a great potential for selector-free high-density memory applications. [ABSTRACT FROM AUTHOR]

In this paper, the NbOx, which was regarded as a promising material based on its insulator–metal transition (IMT) effects, was applied as the switching layer of the device. The threshold switching characteristics were comprehensively investigated with particular emphasis on temperature dependence. The conduction mechanism for high-resistance state (HRS) was fitted and verified to be Schottky emission. With the increase in temperature, the fitting results demonstrated that the Schottky barrier decreased, leading to a reduction in the resistance of HRS. Furthermore, according to Fourier’s law of heat conduction, the fluctuation range of temperature was smaller, causing a narrow distribution of the threshold voltage as the operating temperature increased. In addition, the increasing temperature caused high energy of electrons, which would induce an IMT more easily, leading to a lower threshold voltage. This paper provided the promise for improving the thermal stability of selected devices. [ABSTRACT FROM AUTHOR]

The introduction of metal nanocrystals (NCs) has been confirmed to improve electrical uniformity of oxide-based resistive random access memory (RRAM) devices significantly; however, the current reports do not systematically elucidate the relationship between the size/distribution of NCs and the electrical uniformity of RRAM devices. In this paper, we focused on the impact of metal NCs size and areal density on the resistive switching (RS) performances of oxide RRAM by atomic layer deposition (ALD) based on the experimental results and theoretical calculation. The dependence of ALD cycles of 50–130 during Pt or CoPtx NCs growth on the RS parameters of Al2O3 or HfO2 memory units has been evaluated systematically. The RRAM embedded Pt or CoPtx NCs shows the trends: with increasing ALD cycles, the forming voltage, set/reset voltage, the resistance in off and on state, and ${R}_{ \mathrm{\scriptscriptstyle OFF}}/{R}_{ \mathrm{\scriptscriptstyle ON}}$ ratio entirely first decrease, then flatten, and increase later with a minimum value at about 100 cycles. Although all metal NCs with various sizes enhance the electric field strength compared to at the planar region, only metal NCs with proper NCs size and areal density (9 nm/6– $10\times 10^{\textsf {11}}$ /cm2 in this paper) can effectively produce stronger localized electric field at the tip of metal NCs, leading to optimal RS behavior. [ABSTRACT FROM AUTHOR]

The switching properties of Te and TeTiW top electrodes (TEs) on TiW/SiN/TiN resistive switching memory devices are explored in this paper. The TeTiW TE device exhibits more favorable bipolar resistive switching behavior because of the decrease in binding energy after its use. This finding is confirmed through X-ray photoelectron spectroscopy analyses. The filament of the TeTiW TE device is metal like after forming, and the reset process corresponds with the thermal-dissolution mechanism. A physical model based on a Te filament is constructed to explain such phenomena. The TeTiW TE device provides the excellent endurance of more than 104 cycles, with an ON/OFF ratio of 500. The improvement can be attributed to the filament’s robustness during the forming and set processes, which prevent its diffusion even at high temperature. The device also features long retention for up to 104 s at 225 °C without stress, and 104 s at 85 °C with stress of −0.3 V. Therefore, it has high potential for high-density nonvolatile memory applications. [ABSTRACT FROM AUTHOR]

In this paper, we demonstrate the linear conductance-change characteristics of a conductive-bridging RAM (CBRAM) to be employed as an artificial synapse device in neuromorphic systems. The CBRAM with a bilayer electrolyte structure (${\mathrm {Cu/Cu}}_{{2}-{x}}\text{S}$ / $\mathrm {WO}_{{3}-{x}}$ /W) exhibits analog switching behavior during the depression process due to the well-controlled dissolution of the conductive filament. To analyze the origin of this motion, we investigate the effective voltage applied to $\mathrm {Cu}_{{2}-{x}}\text{S}$ and $\mathrm {WO}_{{3}-{x}}$. Our findings reveal that $\mathrm {Cu}_{{2}-{x}}\text{S}$ , acting as a voltage divider, helps in suppressing the large voltage drop in $\mathrm {WO}_{{3}-{x}}$ , where the formation/dissolution of filament occurs. Furthermore, due to the diode-like characteristics of $\mathrm {Cu}_{{2}-{x}}\text{S}$ and the division of voltage drop between $\mathrm {WO}_{{3}-{x}}$ and $\mathrm {Cu}_{{2}-{x}}\text{S}$ , an optimum programming energy is applied to $\mathrm {WO}_{{3}-{x}}$ during the depression process. This leads to linear conductance-change characteristics under identical pulses. However, abrupt conductance-change characteristics are observed during the potentiation process. Thus, we use only the device characteristics of the depression part for the neuromorphic system. An excellent classification accuracy is achieved due to the linear conductance-change characteristics and optimized pulse conditions. [ABSTRACT FROM AUTHOR]

Performance of the crossbar memory array highly depends on the selector characteristics. In this paper, rigorous transient analyses are performed for a large-size crossbar memory array using novel NbO2-based selectors with a threshold switching behavior. To enable accurate and efficient array-level simulation, an electrostatic discharge-based compact model is employed to effectively describe the ${I}$ – ${V}$ characteristics of the selector. Multiple key design parameters of the selector are investigated, such as the threshold voltage, leakage current, and intrinsic switching speed. A sensitivity analysis is performed to evaluate the impact of hypothetical improvements in various selector parameters. In addition, the impacts of resistances of interconnect and memory element on the array-level access delay and energy dissipation are quantified. The results show that reducing the threshold voltage of selectors provides the most significant performance improvement, where up to 80% of the energy-delay product saving is observed if the threshold voltage is reduced by 50%. [ABSTRACT FROM AUTHOR]

Negative capacitance FETs (NCFETs) have attracted significant interest due to their steep-switching capability at a low voltage and the associated benefits for implementing energy-efficient Boolean logic. While most existing works aim to avoid the ID – VG hysteresis in NCFETs, this paper exploits this hysteresis feature for logic-memory synergy and presents a custom-designed nonvolatile NCFET D flip-flop (DFF) that maintains its state during power outages. This paper also presents an NCFET fabricated for this purpose, showing <10 mV/decade steep hysteresisedges and high, up to seven orders inmagnitude, R\text {DS} ratio between the two polarization states. With a device-circuit codesign that takes advantage of the embedded nonvolatility and the high R\text {DS} ratio, the proposed DFF consumes negligible static current in backup and restore operations, and remains robust even with significant global and local ferroelectric material variations across a wide 0.3–0.8 V supply voltage range. Therefore, the proposed DFF achieves energy-efficient and low-latency backup and restore operations. Furthermore, it has an ultralow energy-delay overhead, below 2.1% in normal operations, and operates using the same voltage supply as the Boolean logic elements with which it connects. This promises energy-efficient nonvolatile computing in energy-harvesting and power-gating applications. [ABSTRACT FROM PUBLISHER]

This paper presents a ternary content-addressable memory (TCAM) cell based on a skewed straintronic magnetotunneling junction (MTJ) switch. A straintronic magnetotunneling junction (s-MTJ) is a three-terminal switch, where the resistance between two of the terminals switches when a potential is applied to the third (gate) terminal that induces strain in the magnetostrictive free-layer. An s-MTJ is a highly energy-efficient switch that would dissipate only ~aJ of energy during switching. This paper discusses a novel variant of s-MTJ, namely skewed s-MTJ (ss-MTJ), where the MTJ switching can be controlled by two gate terminals. The current through an ss-MTJ is minimum when the potentials at the first and second gate terminals ( V2 and V3 , respectively) obey the relation V3 = V2+VF . Here, VF is a fixed voltage (“offset voltage”). Current in an ss-MTJ increases steeply when V2 and V3 deviate from the above “match” condition. This unconventional I – V characteristic of an ss-MTJ is exploited to design a non-Boolean TCAM cell based on just one transistor, one trench capacitor, and one ss-MTJ. We also discuss search and write operations in the ss-MTJ-TCAM cell, and show that the cell requires very small voltages to operate because of the unique I – V characteristics of the ss-MTJ. [ABSTRACT FROM PUBLISHER]

3-D integrations are unavoidable task for new emerging memories, including resistive switching random-access memory (RRAM), in order to overcome the market-leading nand flash. However, an RRAM crossbar array (CBA) suffers severe read margin degradation due to the sneak current, which becomes even more critical as the memory density increases with the 3-D integration. In this paper, we extend the two-port readout scheme for a 2-D CBA, proposed in our previous work, to the 3-D vertical structure. A closed-form expression of the operating principle is derived, and HSPICE simulation using a $32\times 32\times8$ vertical RRAM CBA considering practical circuit parameters verifies feasibility of the two-port scheme to the 3-D CBA. [ABSTRACT FROM AUTHOR]

In the study of resistive random access memory using GeTeOx film as the switching layer, the device performed excellent property of bipolar resistive switching (BRS), which could be gradually transformed to the complementary resistive switching (CRS) by varying SET process current compliance. The conductive filament conduction mechanism of BRS could be verified by electrical characteristics and reliable data fitting. Through increasing current compliance of the SET process, CRS could be achieved due to higher activity of oxygen vacancies originated from the intensified thermal effect. This paper was beneficial to understand the switching mechanisms of BRS and CRS and provide a method to realize interconversion. Moreover, it was also a potential and promising device to be applied in the neurosynaptic biomimetic field. [ABSTRACT FROM AUTHOR]

Mechanisms of time-dependent dielectric breakdown (TDDB) in nonfilamentary a-Si/TiO2 RRAM cell [a-vacancy modulated conductive oxide (VMCO)] have been examined in this paper, including defects generation in the grain boundary, defects clustering, and different defects generation rates in a-Si and TiO2 layers. The unique feature of a bimodal Weibull distribution at low-resistance state (LRS) and a single shallow slope distribution at high-resistance state (HRS) cannot be explained by the above mechanisms. By using a combination of constant voltage stress, time-to-breakdown Weibull distribution, and random telegraph noise (RTN)-based defect profiling in devices of various sizes, layer thicknesses, and processes, it is revealed that the defect profile is modulated when switching between HRS and LRS and the correlation of defect profile modulation with local defect generation rate can explain the difference in Weibull distributions at HRS and LRS. The transition from bimodal distribution at LRS to a single-steep slope with thinner a-Si layer, and the good area scaling of Weibull distribution at HRS but not at LRS, can also be explained. The critical layers affecting the TDDB in a-VMCO are identified, providing useful guidance for device performance improvement. [ABSTRACT FROM AUTHOR]

Noise in resistive switching memory (RRAM) is among the main concerns due to its impact on the reliability of single-bit and multilevel cell devices. Although noise in typical RRAM cells is understood fairly well, the statistics of noise and the presence and impact of statistical tails in the current fluctuation is what mostly affects the RRAM reliability at the array level. This paper addresses current noise in RRAM arrays, focusing on high-resistance state distribution and its broadening with time. We highlight two main contributions to the tail behavior, namely, random walk (RW) and random telegraph noise (RTN) with random start and stop. We provide evidence for a time decay of RW amplitude with time, which we explain by time-dependent stabilization of defects. We finally develop a statistical Monte Carlo model for noise, which is capable of explaining the broadening of the resistance distribution based on a physical description of RW and RTN components. [ABSTRACT FROM AUTHOR]

In this paper, we investigate in depth Forming, SET, and Retention of conductive-bridge random-access memory (CBRAM). A kinetic Monte Carlo model of the CBRAM has been developed considering ionic hopping and chemical reaction dynamics. Based on inputs from ab initio calculations and the physical properties of the materials, the model offers the simulation of both the Forming/SET and the Data Retention operations. It aims to create a bond between the physics at atomic level and the device behavior. From the model and experimental results obtained on decananometric devices, we propose an understanding of the physical mechanisms involved in the CBRAM operations. Using the consistent Forming/SET and Data Retention model, we obtained good agreement with the experimental data. Finally, the impact of each layer of the CBRAM on the Forming/SET behavior is decorrelated, allowing an optimization of the performance. [ABSTRACT FROM AUTHOR]

Resistive random access memory is known as a type of nonvolatile memory. An abnormal volatile memory characteristic of a normal ZnSnO resistive memory is first demonstrated in this paper. Although the ${I}$ – ${V}$ curves exhibit a normal and stable resistive switching memory behavior, the resistance state is found to be only determined by the initial applied voltage along with the voltage sweep direction. It is set/reset processes free. Namely, it is volatile. The resistance states are found to be dominated by trap-assisted tunneling, trap-controlled space-charge-limited conduction, and hopping transport. Different resistance states are related to different carrier transport mechanisms. Each resistance state can independently and repeatably appear for over 1000 voltage sweeps. The ratio of the high-resistance state to the low-resistance state is $\sim 3\times 10^{2}$. [ABSTRACT FROM AUTHOR]

Partial bias schemes reduce the disturbance during the writing of crossbar arrays (CBAs). Detailed analysis of two partial bias schemes is presented in this paper: 1) 1/2 bias scheme for low-power operation and 2) 1/3 bias scheme for high-performance (i.e., high Vdd) operation. With partial bias schemes, a sneak leakage reversal phenomenon may occur due to line-resistance-induced voltage degradation, which provides a measure of voltage driving range along access lines. Voltage dividing effect of selector devices reduces disturbance in CBAs and leads to similar writing voltage margin in both bias schemes. Matching a proper partial bias scheme with the selector device choice optimizes the performance of CBAs. [ABSTRACT FROM AUTHOR]

In this paper, the use of HfO2-based oxide-based resistive memory (OxRAM) devices operated in binary mode to implement synapses in a convolutional neural network (CNN) is studied. We employed an artificial synapse composed of multiple OxRAM cells connected in parallel, thereby providing synaptic efficacies. Electrical characterization results show that the proposed HfO2-based OxRAM technology offers good electrical properties in terms of endurance ( > 10^8 cycles), speed (<10 ns), and low energy (<10 pJ), and thus being well suited for neuromorphic applications. A device physical model is developed in order to study the variability of the resistance as a function of the stochastic position of oxygen vacancies in 3-D. Finally, the proposed binary OxRAM synapse has been used for CNN system-level simulations. High accuracy (recognition rate > 98%) is demonstrated for a complex visual pattern recognition application. We demonstrated that the resistance variability and the reduced memory window of the OxRAM cells when operated at extremely low programming conditions (<10 pJ per switching event) have a small impact on the performances of proposed OxRAM-based CNN (recognition rate 94%). [ABSTRACT FROM AUTHOR]

Chalcogenide glass-based programmable metallization cell (PMC) devices undergo Ag+-ion transport and controlled resistance change under the application of electrical bias. In this paper, photo-doped PMC devices are characterized with impedance spectroscopy. Photo doping is an important step in PMC fabrication as it introduces the mobile Ag into the electrolyte and, therefore, has a significant effect on device characteristics. Data obtained from measurements on devices with different areas in both their high resistance state (HRS) and low resistance state (LRS) are used to parameterize equivalent circuit models. The models elucidate the differences in the HRS and LRS electrical properties. [ABSTRACT FROM AUTHOR]

Resistive switching memory (RRAM) relies on the voltage-driven formation/disruption of a conductive filament (CF) across a thin insulating layer. Due to the 1-D structure of the CF and discrete nature of defects, the set and reset states of the memory device generally display statistical variability from cycle to cycle. For projecting cell downscaling and designing improved programming operations, the variability as a function of the operation parameters, such as the maximum current in the set process and maximum voltage in the reset process, need to be evaluated and understood. This paper addresses set/reset variability, presenting statistical data for HfOx-based RRAM and introducing a physics-based Monte Carlo model for switching statistics. The model can predict the distribution of the set state as a function of the compliance (maximum) current during set and distribution of the reset state as a function of the stop (maximum) voltage during reset. Numerical modeling results are finally presented to provide additional insight into discrete fluctuation events. [ABSTRACT FROM AUTHOR]

We demonstrate a metal sandwiched Al-doped zinc tin oxide (AZTO) thin-film device to exhibit a characteristic evolution process from Schottky junction diode to resistive-switching random access memory (RRAM) applications. The proposed TiN/Ti/AZTO/Pt device can initially show good rectifying characteristics and high forward-bias current for Schottky diodes. After applying with an electrically triggered forming process, the transition of electrical behavior occurs and evolves from the diode to RRAM characteristics. The RRAM device exhibits the coexistence of bipolar and unipolar resistive-switching modes through the positive-bias forming and reversed-bias forming process, respectively. In addition, the RRAM device with bipolar mode can perform the functionality of multilevel cell storage, while the one with unipolar mode shows stable resistive-switching performance. Furthermore, one-transistor and one-resistor (1T1R) architecture with an RRAM cell connected with a thin-film transistor (TFT) device is developed in this paper. The TFT device using AZTO film as an active channel layer performs good electrical characteristics for a driver in the 1T1R operation scheme. The integration of AZTO-based electronic devices has great potential for increasing the application diversity of metal oxide AZTO thin film as well as the flexibility of circuit design in the emerging optoelectronic technologies. [ABSTRACT FROM PUBLISHER]

Stateful in-memory logic (IML) is a promising paradigm to realize the unity of data storage and processing in the same die, exhibiting great feasibility to break the bottleneck of the conventional von Neumann architecture. On the roadmap toward developing such a logic platform, a critical step is the effective and efficient realization of a complete set of logic functions within a memory. In this paper, we report a realization of stateful reconfigurable logic functions via a single three-terminal magnetic tunnel junction (MTJ) device within a spintronic memory by exploiting the novel voltage-gated spin Hall-effect driven magnetization switching mechanism. This proposed reconfigurable IML methodology can be implemented within either a typical memory array or a cross-point array architecture. The feasibility of the proposed approach is successfully demonstrated with hybrid MTJ/CMOS circuit simulations. We believe our work may promote the research and development of the revolutionary IML for future non-von Neumann architectures. [ABSTRACT FROM PUBLISHER]

Resistive switching memory (RRAM) features many optimal properties for future memory applications that make RRAM a strong candidate for storage-class memory and embedded nonvolatile memory. This paper addresses the cycling-induced degradation of RRAM devices based on a HfO2 switching layer. We show that the cycling degradation results in the decrease of several RRAM parameters, such as the resistance of the low-resistance state, the set voltage V\mathrm{ set} , the reset voltage V\mathrm{ reset} , and others. The degradation with cycling is further attributed to enhanced ion mobility due to defect generation within the active filament area in the RRAM device. A distributed-energy model is developed to simulate the degradation kinetics and support our physical interpretation. This paper provides an efficient methodology to predict device degradation after any arbitrary number of cycles and allows for wear leveling in memory array. [ABSTRACT FROM AUTHOR]

In spite of the apparent simplicity of the system under study, compact modeling of complementary resistive switching (CRS) devices, i.e., two antiserially connected memristive structures, is by no means straightforward. This requires a deep understanding of the voltage drops occurring across the circuit elements and correct treatment of the so-called snapback (SB) effect typical of the breakdown process of a thin dielectric film in an MIS or a MIM structure. The SB effect fundamentally consists in a sudden reduction of the device resistance caused by the formation of a filamentary path spanning the insulator. Beyond this point, the filament widens keeping the voltage drop across its extremes constant. The consequence of disregarding this effect is clearly distinguishable in the simulated curves: progressive openings of the on-state windows for both positive and negative voltages instead of abrupt ones. In this paper, a modification is introduced in the original memdiode model for memristive devices in order to account for this remarkable feature. Ta2O5-based CRS devices are considered to demonstrate the suitability of our approach. [ABSTRACT FROM AUTHOR]

Resistive random access memory (ReRAM), a new emerging nonvolatile memory technology based on changes in electrical resistivity of a dielectric film, offers promising advantages such as scalability, fast switching, and low operation voltage. However, for ReRAM to become a successful technology, it is necessary to accurately control the stochastic nature of the conductive nanoscale filaments (CNFs) that governs the resistive switching (RS) behavior of the device and limits its long-term stability and reliability. In this paper, we developed a highly scalable nanostructured/textured electrode that is composed of an array of Al nanotips based on an anodic aluminum oxide template. The nanotips improve the RS characteristics by intensifying the electric field at the apex of each nanotip which is demonstrated using numerical simulations. The localized electric field induces the repetitive nucleation/ formation/rupture of the CNFs in a more controlled fashion compared to a flat Al electrode. As a result, the nanotip sample exhibits uniform and reduced forming/reset voltages as low as 4.70 ± 0.98V/1.00 ± 0.19 V, stable endurance, and long-term retention. As a result, we were able to achieve ultralow-power and error-free operation of 100 cells covering a large area, significantly demonstrating improved uniformity and reliability compared to devices made using flat Al electrodes. This universal bottom-up strategy of self-organized nanostructured-electrodes provides a pathway toward large-scale, highly reliable, and RS memory devices. [ABSTRACT FROM AUTHOR]

Resistive switching memory (RRAM) has been proposed as an artificial synapse in neuromorphic circuits due to its tunable resistance, low power operation, and scalability. For the development of high-density neuromorphic circuits, it is essential to validate the state-of-the-art bistable RRAM and to introduce small-area building blocks serving as artificial synapses. This paper introduces a new synaptic circuit consisting of a one-transistor/one-resistor structure, where the resistive element is a HfO2 RRAM with bipolar switching. The spike-timing-dependent plasticity is demonstrated in both the deterministic and stochastic regimes of the RRAM. Finally, a fully connected neuromorphic network is simulated showing online unsupervised pattern learning and recognition for various voltages of the POST spike. The results support bistable RRAM for high-performance artificial synapses in neuromorphic circuits. [ABSTRACT FROM AUTHOR]

Resistive-switching memory (RRAM) is attracting a widespread interest for its outstanding properties, such as low power, high speed, and good endurance. A crucial concern for RRAM is the current fluctuation, which induces significant broadening of resistance levels in single-bit and multilevel applications. This paper addresses low-frequency fluctuations focusing on $1/f$ and random telegraph noise contributions in intrinsic, i.e., typical, cells. The current fluctuations are studied in both the time and frequency domains, and the analytical models are presented to predict the resistance broadening for different RRAM states. Finally, the resistance dependence of noise and broadening is studied with the support of a 3-D finite-element model. [ABSTRACT FROM AUTHOR]

This paper provides new insights into the effect of device characteristics on multilevel-cell (MLC) operation, aiming at potential benefits, such as the reduction of write latency and peripheral circuit design overhead. A general categorization of the MLC-operating schemes in storage-class memory (SCM) is proposed to connect the total number of write inputs with fundamental device properties. The categorization method is validated using two resistive random access memory devices based on different switching mechanisms. Favorable device characteristics and the corresponding simplified MLC operating schemes are addressed to facilitate future development of MLC SCM. [ABSTRACT FROM AUTHOR]

All resistive switching memory devices face a critical voltage-time dilemma, as they require fast write at moderate voltage together with disturb immunity at lower (read) voltage. In this paper, excellent voltage-time characteristics are demonstrated on a 90-nm CMOS-friendly W/Al2O3/TiW/Cu conductive-bridging memory cell. The switching voltage was evaluated in the large write pulsewidth range between 10 ns and 10 s, from which a very low slope of $\sim 75$ mV/decade was extracted. These characteristics allow, on the one hand, a fast switching (10 ns) at <3 V, and, on the other hand, excellent voltage-disturb immunity extrapolated to ±0.5 V for 10 years. Both constant-voltage-stress and read-endurance tests supported these predictions. By means of conductive-atomic-force microscopy tomography, the hourglass shape of the Cu filament was evidenced. Both the more distributed electrical field induced by this shape along the filament and the analysis of a charge-transfer (redox) reaction as rate-limiting mechanism in the switching process are discussed as the origins of this excellent disturb immunity. [ABSTRACT FROM AUTHOR]

Two types of 4H-silicon carbide (SiC) MOSFETs are proposed in this paper. One is the novel designed V-groove trench MOSFET that utilizes the 4H-SiC (0-33-8) face for the channel region. The MOS interface using this face shows the extremely low interface state density ( D\mathrm {\mathbf {it}} ) of 3\times 10^11 \mathrmcm^-2~\mathrmeV^-1 , which causes the high channel mobility of 80 \mathrmcm^2~\mathrmV^-1~\mathrms^-1 results in very low channel resistance. The buried p+ regions located close to the trench bottom can effectively alleviate the electric field crowding without the significant sacrifice of the increase of the resistance. The low specific ON-state resistance of 3.5 m \Omega ~\mathrmcm^\mathrm \mathbf 2 with sufficiently high blocking voltage of 1700 V is obtained. The other is the double implanted MOSFET with the carefully designed junction termination extension and field-limiting rings for the edge termination region, and the additional doping into the junction FET region. With a high-quality and high-uniformity epitaxial layer, 6 mm $\times 6$ mm devices are fabricated. The well balanced specific ON-state resistance of 14.2 m \Omega ~\mathrm{cm}^{2} and the blocking voltage of 3850 V are obtained for 3300 V application. [ABSTRACT FROM AUTHOR]

Bipolar redox-based resistive random-access memory cells are intensively studied for new storage class memory and beyond von Neumann computing applications. However, the considerable variability of the resistance values in ON and OFF state as well as of the SET voltage remains challenging. In this paper, we discuss the physical origin of the significant reduction in the switching variability of HfO2-based devices achieved by the insertion of a thin TiOx layer between the HfO2 layer and the oxygen exchange metal layer. Typically, HfO2 single layer cells exhibit an abrupt SET process, which is difficult to control. In contrast, self-compliance effects in the HfO2/TiOx bilayer devices lead to an increased stability of SET voltages and OFF-state resistances. The SET process is gradual and the RESET becomes abrupt for higher switching currents. Comparison of the experimental data with simulation results achieved from a physics-based compact model for the full description of the switching behavior of the single layer and bilayer devices clearly reveal three major effects. The TiOx layer affects the temperature distribution during switching (by modifying the heat dissipation), forms an additional series resistance and changes the current conduction mechanism in the OFF state of the bilayer device compared to the single layer device. [ABSTRACT FROM AUTHOR]

Resistive switching memory (RRAM) is among the most mature technologies for next generation storage class memory with low power, high density, and improved performance. The biggest challenge toward industrialization of RRAM is the large variability and noise issues, causing distribution broadening which affects retention even at room temperature. Noise and variability can be addressed by enlarging the resistance window between low-resistance state and high-resistance state, which requires a proper engineering of device materials and electrodes. This paper presents an RRAM device technology based on silicon oxide (SiOx), showing high resistance window thanks to the high bandgap in the silicon oxide. Endurance, retention, and variability show excellent performance, thus supporting SiOx as a strong active material for developing future generation RRAMs. [ABSTRACT FROM AUTHOR]

A key concern for resistive-switching random access memory (RRAM) is the read noise, due to the structural, chemical, and electrical modifications taking place at the localized current path, or conductive filament (CF). Read noise typically appears as a random telegraph noise (RTN), where the current randomly fluctuates between ON and OFF levels. This paper addresses RTN in RRAM, providing physical interpretations and models for the dependence on the programming and read conditions. First, we explain the RTN dependence on the compliance current during set transition in terms of the size-dependent depletion of carriers within the CF. Then, we discuss the bias dependence of the RTN switching times and amplitude, which can be explained by Joule heating and Poole-Frenkel barrier modifications arising from the electrostatics of the RTN fluctuating center. [ABSTRACT FROM AUTHOR]

A highly transparent resistive random access memory with a configuration of multilayer graphene (MLG)/ Dy2O3 /indium tin oxide (ITO) structure is demonstrated in this paper. The fabricated device is transparent, with 80% transmittance at 550 nm. The MLG/ Dy2O3 /ITO device shows unipolar resistance switching with a low operation current (<100~\muA) , low operation voltage (<1~V) , low power consumption (<100~\muW) , high resistance ratio (>10^4) , fast switching speed (<60~ns) , reliable data retention, and promising cycle endurance properties (>200~cycles) , which makes a step toward the realization of low-power transparent electronics for next-generation nonvolatile memory application. The MLG/ Dy2O3 /ITO device exhibited typical filamentary-conduction-type resistive random access memory behavior and no forming process is required. High resistance state (HRS) increases with a reduced device area while low resistance state (LRS) is insensitive to the device sizes. Moreover, Raman spectra obtained in pristine state, HRS, and LRS indicate that the lower power consumption of MLG/ Dy2O3 /ITO device is attributable to the formation of oxygen graphene layers. [ABSTRACT FROM AUTHOR]

A comprehensive array operation scheme for a multilayer stacked 3-D vertical resistive random access memory (RRAM) cross-point array architecture is developed. Based on the proposed READ/WRITE scheme, each memory cell in the 3-D array can be randomly accessed. The fabricated AlO\oldstyle{y}/HfO\oldstyle{x} -based bilayer vertical RRAM array with excellent device-to-device and layer-to-layer uniformity is applied to demonstrate the feasibility of the proposed operation scheme. [ABSTRACT FROM PUBLISHER]

In this paper, we show performance and reliability improvement of Ag-GeS2-based conductive bridge RAM (CBRAM) devices by addition of a 2-nm-thick HfO2 layer between the electrolyte and the W bottom electrode. Our optimized dual-layer electrolyte stack (2-nm HfO2\--30\-nm~GeS2) leads to a resistance ratio (ROFF/RON) higher than 10^6 and projected 10 years read disturb immunity at 0.04 V. The improved memory resistance ratio is explained by means of physical modeling. Using compact modeling and circuit level simulations, we show that our optimized CBRAM device, integrated in a 1T-2R architecture, fits well with the aggressive requirements of field programmable gate array-type reconfigurable applications. Nonvolatility, back-end-of-line compatibility, and 1.3-nA leakage current during continuous reverse read operation at 1 V are strong benefits demonstrated on our device for such applications. [ABSTRACT FROM AUTHOR]

In this paper, indium-tin-oxide (ITO) was used to act as both insulator and top electrode in resistive random access memory (RRAM) on identical bottom substrates. This is achieved by cosputtering an ITO target with nitride (N2) or oxygen (O2) gas as the insulator; then capping by an ITO electrode, such that both the rectifier and RRAM characteristics can be achieved before and after a forming process, respectively. In contrast, using pure ITO as an insulator does not exhibit RRAM behavior. To verify the rectifier and RRAM characteristics, material analyses and electrical measurements at various temperatures were conducted. Reliability tests including retention and endurance were also applied to verify the resistance switching stability. Finally, the rectifier and RRAM conduction models were proposed to examine the resistance switching behaviors. By applying the ITO material as both electrode and insulator, the resistance switching characteristic with high reliability is thus obtained. [ABSTRACT FROM AUTHOR]

Using the model developed in Part I of this two-part paper, the simulated dc sweep and pulse transient characteristics of a metal oxide resistive random access memory cell are corroborated with the experimental data of \HfOx memory. Key switching features such as the abrupt SET process, gradual RESET process, current fluctuation in the RESET process, and multilevel resistance state distributions are captured by the simulation. The current fluctuation in the RESET process is caused by the competition between the simultaneous oxygen vacancy recombination and generation processes. The origin of the high-resistance state variation and the tail bit problem are attributed to the variation of the tunneling gap distances and the stochastic nature of new Vo generation in the tunneling gap region, respectively. The use of the write–verify technique and a bilayer oxide structure are proposed to achieve a tighter resistance distribution. [ABSTRACT FROM AUTHOR]

There has been a strong demand for developing an ultradense and low-power nonvolatile memory technology. In this paper, we present a carbon-based resistive random access memory device with a carbon nanotube (CNT) electrode. An amorphous carbon layer is sandwiched between the fast-diffusing top metal electrode and the bottom CNT electrode, exhibiting a bipolar switching behavior. The use of the CNT electrode can substantially reduce the size of the active device area. We also demonstrate a carbon-based complementary resistive switch (CRS) consisting of two back-to-back connected memory cells, providing a route to reduce the sneak current in the cross-point memory. The bit information of the CRS cell is stored in a high-resistance state, thus reducing the power consumption of the CRS memory cell. This paper provides valuable early data on the effect of electrode size scaling down to nanometer size. [ABSTRACT FROM PUBLISHER]

Spin-transfer torque magnetic tunnel junction (MTJ) is a promising candidate for nonvolatile memories thanks to its high speed, low power, infinite endurance, and easy integration with CMOS circuits. However, a relatively high current flowing through an MTJ is always required by most of the switching mechanisms, which results in a high electric field in the MTJ and a significant self-heating effect. This may lead to the dielectric breakdown of the ultrathin ( $\sim 1$ nm) oxide barrier in the MTJ and cause functional errors of hybrid CMOS/MTJ circuits. This paper analyzes the physical mechanisms of time-dependent dielectric breakdown (TDDB) in an oxide barrier and proposes an SPICE-compact model of the MTJ. The simulation results show great consistency with the experimental measurements. This model can be used to execute a more realistic design according to the constraints obtained from simulation. The users can estimate the lifetime, the operation voltage margin, and the failure probability caused by TDDB in the MTJ-based circuits. [ABSTRACT FROM AUTHOR]

A model of resistive random access memory (RRAM) cells aimed at providing an optimal programming/erase scheme in which the timing and biasing can be accurately optimized is proposed and implemented. To expedite technology development with an emphasis on ICs, a predictive model to capture the physical operation of every memory cell is needed. Although a number of compact RRAM models have been developed, this paper further considers the time-dependent reset process and the heat transfer in the conductive filaments. These phenomena are becoming critical in scaled memory cells and need to be carefully addressed. Due to the physical nature of the model, model parameters can be straightforwardly calibrated, relying on limited measurement data. The compact model is implemented using Verilog-A, and it is flexible for different circuit simulators. [ABSTRACT FROM PUBLISHER]

To extend the scaling of digital integrated circuits, beyond-CMOS approaches based on advanced materials and novel switching concepts are strongly needed. Among these approaches, the resistive switching random access memory (RRAM) allows for fast and nonvolatile switching at scalable power consumption. This work presents functionally complete logic gates based on RRAM technology. Logic computation is obtained through conditional switching in RRAM circuits with serially connected switches. AND, implication, NOT, and bit transfer operations are demonstrated, each using a single clock pulse, while other functions (e.g., OR and XOR) are achieved in multiple steps. The results support RRAM logic for normally-off digital circuits with extremely high density. [ABSTRACT FROM AUTHOR]

We demonstrate the ink-jet printed fabrication technique for TiO2-based memristor, followed by detailed analysis of electrical characteristics and development of a new model that considers observed phenomena of quantized conductance steps. The existence of pinched hysteretic current–voltage characteristics is evidence of memristive behavior, provided by the reversible atomic rearrangement taking place in the functional layer. For the first time, performed electrical measurement on the micrometer thickness devices based on TiO2 active layer has captured the plateaux steps of the conductance at integer multiples of elementary quantum conductance. This behavior is consistent with the assumption that transport from electrode to electrode emerges through confined paths of conductive filaments with radius in the nanometer size range. Moreover, we introduce a novel model, based on the diffusion equation for ballistic transport in memristive devices, which considers the conductance plateaux steps. [ABSTRACT FROM AUTHOR]

Recently, spin-transfer torque magnetic random access memory (STT-MRAM) has been considered as a promising universal memory candidate for future memory and computing systems, thanks to its nonvolatility, high speed, low power, good endurance, and scalability. However, as technology scales down, STT-MRAM suffers from serious process variations and thermal fluctuations, which greatly degrade the performance and stability of STT-MRAM. In general, the optimization and robustness of STT-MRAM under process variations often require a hybrid design flow and multilevel codesign strategies. In this paper, we quantitatively analyze the impacts of process variations and thermal fluctuations on the STT-MRAM performances from physics, technology, and circuit design point of views. Based on the analyses, we found that readability is becoming the newest challenge for deeply scaled STT-MRAM due to the conflict between sensing margin and read disturbance. To deal with this problem, a novel reconfigurable design strategy from device, circuit, and architecture codesign perspective is then presented. Finally, a conceptual hybrid magnetic/CMOS design flow is also proposed for STT-MRAM in deeply scaled technology nodes. [ABSTRACT FROM AUTHOR]

This paper proposes a domain-wall-coupling-based magnetic device for high-speed and robust on-chip cache applications. The read and write current paths are magnetically coupled and electrically isolated, which significantly improves the reliability of the read and write operations. Our proposed device makes use of fast and energy-efficient domain wall motion for write operation. A complementary polarizer structure is used to achieve low-power, high-speed, and high-sensing margin read operations. A device-to-circuits simulation framework was also developed to evaluate our proposed multiterminal domain-wall-coupling-based spin-transfer torque (DWCSTT) magnetic random access memory (MRAM) cell. Compared with the conventional 1T-1MTJ STT-MRAM bit cell, the proposed DWCSTT bit cell achieves >3.5\times improvement in write power under iso-area and iso-write margin conditions, and $>\!\!3\times $ better sensing margin with low read power consumption and higher read disturb margin. [ABSTRACT FROM AUTHOR]

An intentionally introduced interface layer in the resistive random-access memory (RRAM) devices play an important role in the improvement of resistive switching characteristics. In this paper, the resistive switching characteristics of ZrO2-based RRAM devices by inserting a thin TiO2 interface layer between electrodes and ZrO2 resistive switching layer were investigated. Compared with the Cu/ZrO2/Pt and Cu/ZrO2/TiO2/Pt devices, the Cu/TiO2/ZrO2/Pt and Cu/TiO2/ZrO2/TiO2/Pt devices showed much improved programing voltages, including lower forming voltage and lower set voltage. Moreover, the reset current was also improved. These results indicate that the TiO2 interface layer between the anode electrode and the resistive switching layer plays an important role in improving device performance. [ABSTRACT FROM AUTHOR]

Enlargement of memory window through forming compliance current was demonstrated in Gd:SiO2 resistive random access memory (RRAM) with a gadolinium (Gd) electrode. Lower forming compliance current for Gd:SiO2 RRAM with a Gd electrode results in larger memory window as compared with the RRAM with a Pt electrode. Through analyses on the current conduction mechanism, we demonstrate that a lower forming compliance current leads to a thinner conductive filament forming and less oxygen ions penetrating into Gd electrode, which caused higher on current and lower off current. Furthermore, a possible resistive switching model was proposed to explain the effect of Gd electrode on RRAM device. [ABSTRACT FROM AUTHOR]

The resistive random access memory (RRAM) crossbar array has been extensively studied as one of the most promising candidates for future high-density nonvolatile memory technology. However, some problems caused by circuit and device interaction, such as sneak leakage paths, result in limited array size and large power consumption, which degrade the array performance significantly. Thus, the analysis on circuit and device interaction issue is imperative. In this paper, a simulation method is developed to investigate the critical issues correlated with the interaction between devices and the circuit. The simulations show that a large off/on ratio of resistance states of RRAM is beneficial for large readout margin (i.e., array size). The existence of the selector connected in series with an RRAM device can eliminate the need for high Ron resistance, which is critical for the array consisted of only RRAM cells. The readout margin is more sensitive to the variation of Ron and is determined by the nonlinearity of the I–V characteristics of RRAM, whereas the nonlinear characteristics of the selector device are beneficial for a larger readout margin. An optimal design scheme for turn-on voltage and conductance of the selector is proposed based on the simulation. [ABSTRACT FROM PUBLISHER]

Solid-state memory technology is undergoing a renaissance of new materials and novel device concepts for higher scalability as the mainstream technology, i.e., Flash, is approaching physical limits. Emerging memory technologies, which have unique characteristics not available in Flash, are leading transformations in the design of the memory hierarchy. Phase change memory (PCM) is a promising candidate for the next-generation nonvolatile-memory technology. It has been extensively studied for its electrical properties and material scalability. Yet, questions remain unanswered as to what extent a functional PCM cell can be ultimately scaled to and what properties a PCM cell has at the single-digit nanometer scale. In this paper, we demonstrated a fully functional cross-point PCM cell working close to its ultimate size-scaling limit by using carbon nanotubes (CNTs) as the memory electrode. The utilization of CNT electrode brings the lithography-independent critical dimension down to 1.2 nm and contributes to a large reduction of the reset programming current to 1.4 \mu\A and the programming energy to 210 fJ using a 10 ns reset pulse. Measured electrical characteristics validate the advantage of further device area scaling on reducing the programming current of PCM cells and confirm the potential viability of a highly scaled ultradense PCM array down to the bottom electrode contact area that corresponds to a 1.8 nm node technology. [ABSTRACT FROM AUTHOR]

The variation of switching parameters is one of the major challenges to both the scaling and volume production of metal-oxide-based resistive random-access memories (RRAMs). In this two-part paper, the source of such parameter variation is analyzed by a physics-based simulator, which is equipped with the capability to simulate a large number (\sim1000) of cyclic SET–RESET operations. By comparing the simulation results with experimental data, it is found that the random current fluctuation experimentally observed in the RESET processes is caused by the competition between trap generation and recombination, whereas the variation of the high resistance states and the tail bits are directly correlated to the randomness of the trap dynamics. A combined strategy with a bilayer dielectric material and a write-verification technique is proposed to minimize the resistance variation. We describe the simulation methodology and discuss the dc results in Part I. The corroboration of the model and the device optimization strategy will be discussed in Part II. [ABSTRACT FROM AUTHOR]

In this paper, we investigated the forming-free resistive-switching (RS) behavior in the \Ru/REOx/\TaN (\RE =\break \Ce, Pr, Sm, and Eu) memory device using \CeOx, \PrOx, \SmOx, and \EuOx thin films fabricated in a full-room-temperature process. The dominant conduction mechanism of \Ru/REOx\/ \TaN memory devices in the low-resistance state is ohmic behavior, whereas the high-resistance state is space-charge-limited conduction. The \Ru/CeOx \/\TaN devices show a high resistance ratio of > \10^4, reliable data retention for \10^5 \ \s, and stable endurance characteristics for up to 1000 cycles. This result suggests the high concentration of the cerium ions and the low density of chemical defects (oxygen vacancies) in the \CeOx film. The \Ru/CeOx\/\TaN structure memory is a very promising candidate for future nonvolatile RS memory applications. [ABSTRACT FROM AUTHOR]

This paper estimates the temperature distribution within a spin-torque-transfer RAM (STTRAM) cell due to self-heating using a thermal simulation based on the finite volume method. The analysis shows that, due to high switching current and small volume of the magnetic tunnel junction (MTJ), there can be significant rise in temperature in the MTJ as well as the silicon transistor. The impacts of the increased temperature on operational reliability metrics of the STTRAM cell, i.e., read disturb, write failure, and sensing accuracy, are evaluated. It is shown that, due to the self-heating effect, the operational reliability of an STTRAM cell depends on the read–write history of that cell. [ABSTRACT FROM AUTHOR]