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This paper deals with the design of an ac switch structure for specific ac mains applications 230 V–50 Hz. The targeted power level is about a hundred watts, and the currently used converter circuits make use of bidirectional switches that are realized using anti-series connected MOS transistors. Despite the improvements in performance provided by some of these structures, their fabrication cost is still high and limits their widespread diffusion in a market shared with the triac. To replace the triac, an original current and voltage bidirectional bipolar device called a Bipolar ac (Bipac) is proposed, designed, realized, and characterized. It can be controlled both to turn-on and turn-off with respect to a single reference electrode. It exhibits a very low ON-state voltage drop that makes it interesting for specific mains applications with low load current (0.5 $\text{A}_{{\text {rms}}}$). The study of the Bipac structure is carried out using 2-D Sentaurus physical simulations. The Bipac structure is realized on n-type and on p-type substrates for two different wafer thicknesses. The operating modes of the monolithic bidirectional Bipac switch were validated through electrical characterizations. [ABSTRACT FROM AUTHOR]

In this paper, the requirements of device cross section and aspect ratio (AR) are examined to facilitate steep switching in heavily doped 3-D multiple gate junctionless (JL) transistors. It is shown through well-calibrated simulations and physical insights that the sharp OFF-to- ON switching action is predominantly governed by the area of cross section (${A} _{\textsf {cross}}$) instead of the gate length. A 3-D JL architecture preferably oriented toward a planar topology, i.e., with wider fin and low AR, is conducive for steep switching as a greater bulk area is available for impact ionization. On the contrary, narrow vertical architectures with AR > 1 suppress ${A} _{\textsf {cross}}$ in the bulk and are less likely to support the steep current transition. Steep switching specific scaling methodology is showcased to attain a sharp increase in drain current with a sub-60 mV/decade swing in a tri-gate JL transistor along with an associated negative value of total gate capacitance. [ABSTRACT FROM AUTHOR]

Due to outstanding properties of silicon carbide (SiC) and unipolar current conduction mechanism, the active chip size of SiC metal–oxide–semiconductor field-effect transistors (MOSFETs) is significantly shrunk, which significantly improves switching performance. However, the termination region cannot be scaled down due to the existence of high breakdown electric field enclosing active region. Therefore, a SiC MOSFET switching loss model considering termination region effect is proposed in this paper with revealing physical insights into termination region during switching process. Furthermore, through theoretical analysis, model establishment, and simulation results, the loss breakdown under various blocking voltages (800, 1000, and 1200 V) for 1-, 3-, and 6-A current rated devices is obtained. ${E}_{\textsf {term}}$ and ${E}_{\textsf {acti}}$ as intrinsic loss of turn-on process make a significant contribution to the total switching loss under fast gate drive condition. The model shows that the turn-on and turn-off losses are under and overestimated, respectively, by using the commonly used electrical measurement. The loss from termination region aggravates the underestimation of turn-on loss and overestimation of turn-off loss further. The proposed loss estimation equation could provide accurate loss to help choose device and design power circuit for power electronic community. The results also raise new perspective to edge termination of efficient/reliable SiC MOSFET for device people. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel technique of realizing discrete-time (D-T) signal amplification using Nano-Electro-Mechanical systems (NEMS). The amplifier uses mechanical switches instead of traditional solid-state devices and acts as an inherent sample and hold amplifier. The proposed NEMS D-T amplifier operates on a wide dynamic range of signals without consuming the dc power. Moreover, the proposed amplifier does not suffer from the leakage current and the nonlinearity associated with the sampling ohmic switch. As a proof of concept, the proposed NEMS D-T amplifier is demonstrated in circuit simulations using the calibrated verilog-A models of the NEMS device. The simulated amplifier achieves a gain of ~5, handles the maximum differential input signal of 0.65 V, and consumes only $0.6~\mu \text{W}$ of power for a sampling frequency of 100 kHz. The nonidealities present in the proposed amplifier are highlighted and possible ways to overcome them are discussed. Finally, the design considerations required for the NEMS D-T amplifier are described. [ABSTRACT FROM AUTHOR]

The figure of merit (FOM) of a semiconductor device represents an important quality as it pertains to its performance limits and is often used to drive the technology development in a specific direction. Comparing the performances of switching power MOSFETs using their FOMs has become ubiquitous practice in power semiconductor and power electronics industries. In this paper, a critical review of the proposed power MOSFET FOMs is presented, and key limitations are discussed. It is shown that the quality factor ${Q}_{F2}={(}{\lambda {E}_{c}}/{R_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}}{)}$ along with ${Q}_{G}$ and ${T}_{j\textsf {max}}$ may be used to guide the development of future generations of power semiconductor device technologies for power electronics switching applications, where $\lambda $ and ${E}_{c}$ are the thermal conductivity and critical electric field strength for the avalanche breakdown of the semiconductor material, respectively, ${R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ is the specific on-state electrical resistance, ${Q}_{G}$ is the gate charge, and ${T}_{j\textsf {max}}$ is the maximum junction temperature of the semiconductor power device, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a detailed numerical analysis of work-function modulated cylindrical gate metal–oxide–semiconductor field-effect transistor (MOSFET)-based CMOS inverter. Introduction of work-function modulation in the control gate of dual-material cylindrical gate MOSFET exhibits significant reduction in short-channel effects (SCEs) and threshold voltage. The analytic potential-based model of this device is developed by considering 2-D Poisson’s equation in the cylindrical coordinate system. Development of the numerical model is based on certain boundary conditions to study the electrostatic behavior effectively. The results thus obtained from the analytical model are in good agreement with the model developed in the TCAD simulator. Improved drain current, reduced threshold voltage, immunity against SCEs, lower circuit delay, and high-speed switching have made this device a leader in CMOS logic family. [ABSTRACT FROM AUTHOR]

This paper presents low insertion loss, high isolation, ultra-wideband double-pole-double-throw (DPDT) switch matrix designed in a 0.13- \mu \textm commercial high resistivity trap-rich silicon-on-insulator (SOI) CMOS process for the first time. The switches are designed using series–shunt–series configuration in a ring-type structure with input and output matching networks. Transistor width and transistor channel length effects on the wideband DPDT switch performance are thoroughly investigated. The designed switches achieve widest bandwidth from dc to 30 GHz with a low insertion loss of 2.5 dB and a high isolation of 32 dB up to 30 GHz. The measured input P1dB of designed switches is higher than 18 dBm. It was found both second and third harmonics can be improved by widening switch transistor channel width, and third harmonic can be improved by shortening channel length. The active chip area of designed $2 \times2$ switch matrix is very small size of only 0.28 mm $\times0.21$ mm. [ABSTRACT FROM PUBLISHER]

Current collapse is a phenomenon that increases the channel resistance during the switching process when the high gate and drain voltages are applied. The effect can be found from GaN-based high-electron mobility transistors (HEMTs) and is an obstacle for their applications to power electronics. There have been numerous reports on suppressing current collapse using semiconductor process technologies. In this paper, an enhancement mode (E-mode) AlGaN/GaN/AlGaN double heterostructure was proposed. The current collapse phenomena were studied on devices of E-mode MIS and Schottky gate HEMTs. The results indicate the suppression of current collapse for devices with double heterostructure. [ABSTRACT FROM AUTHOR]

Disordered ionic-bonded transition metal oxide thin-film transistors (TFTs) show promise for a variety of dc and RF switching applications, especially those that can leverage their low-temperature, substrate-agnostic process integration potential. In this paper, enhancement-mode zinc-oxide TFTs were fabricated and their switching performance evaluated. These TFTs exhibit the drain-current density of 0.6 A/mm and minimal frequency dispersion, as evidenced by dynamic current–voltage tests. A high-frequency power switch figure of merit $R_{{\mathrm{\scriptscriptstyle ON}}}Q_{G} of 359 \textm\Omega \,\cdot \, nC was experimentally determined for 0.75- \mu \textm long-channel devices, and through scaling 45.9 \textm\Omega \,\cdot \, nC is achievable for 11 V-rated devices (where R\mathrm{\scriptscriptstyle ON} is ON-state drain–source resistance, and QG is gate charge). An RF switch cutoff frequency fc of 25 GHz was measured for the same 0.75- \mu \textm TFT, whereas fc exceeding 500 GHz and power handling in the tens of watts are projected with optimization. [ABSTRACT FROM AUTHOR]

GaN-based devices are seen as ideal candidates for power-switching applications. For the acceptance of GaN-based devices by module designers, obtaining enhancement-mode (e-mode) behavior in GaN-based heterostructure field-effect transistors (HFETs) has long been in the focus. Although the gate-injection approach appears to be the most promising one to achieve e-mode devices, using a double heterostructure in conjunction with a gate insulator has still its advantages, such as steeper turn-ON characteristics and lower leakage currents. An analytical expression to predict the threshold voltage V\mathrm {th} for a given double heterostructure device has not yet been derived. Moreover, neither an evaluation of the tradeoff between V\mathrm {th} and ON-state resistance $R_{{\text {ds}},\mathrm {\scriptstyle {{ON}}}} has been performed to date. This paper addresses these two aspects. We will show an analytical expression for a metal–insulator–semiconductor double HFET (MIS-DHFET), which in certain cases is also valid for the gate-injection transistor. On the basis of this, we will discuss the actual influence of the Al concentration in the backbarrier on V\mathrm th . We will further employ technology computer aided design (TCAD) device simulations to evaluate the impact on R{\text {ds},\mathrm {\scriptstyle {{ON}}}} when using MIS-DHFETs. It will be shown that by implementing a double heterostructure in MIS devices, it is possible to suppress the typically observed negative V\mathrm {th} –oxide thickness relationship while maintaining a constant $R_{{\text {ds}},\mathrm {\scriptstyle {{ON}}}}$ . [ABSTRACT FROM AUTHOR]

In this paper, we investigate the influence of the drain electrode on the dynamic switching behavior of AlGaN/GaN high-electron-mobility transistors on Si substrate. By adding a field plate to the drain electrode, a dramatic increase in the dynamic ON-resistance dynR \mathrm{\scriptscriptstyle ON} was identified. The dispersion effect is correlated with the high electric field below the drain field plate (DFP), the onset of which is caused by the full electron depletion from both the channel and the GaN cap layer. We show that the electron distribution is modified by the passivation method, backside bias, or surface charges and, hence, shifts the onset voltage of the trapping effect. Trapped electrons underneath the DFP are thought to be responsible for the measured rise of the dynR \mathrm{\scriptscriptstyle ON} . With the introduction of an extended ohmic drain contact, the influence of a metallization overhang at the drain edge can be suppressed. The detrapping energies associated with the surface defects were determined to 0.2, 0.3, and 0.7 eV, respectively. Simulations and measurements indicate that charges inside the passivation below the DFP worsen the switching behavior. [ABSTRACT FROM AUTHOR]

Logic gates based on the resistive switching random access memory (RRAM) allow normally-off digital computing because of the nonvolatile nature of the RRAM switch [1]. An extremely small area consumption can be achieved because of the 2–terminal structure of the RRAM switch and its capability of 3-D stacking. However, the details of RRAM organization within the array must be thoroughly investigated. This paper discusses the array organization and the select/unselect schemes of the RRAM logic circuits. We demonstrate a 1-bit adder to support the high functionality of RRAM logic. These results support RRAM as a promising technology for nonvolatile logic circuits beyond CMOS. [ABSTRACT FROM AUTHOR]

In this paper, we compare the performances of FinFETs, lateral gate-all-around (GAA) FETs, and vertical GAAFETs (VFETs) at 7-nm node dimensions and beyond. Comparison is done at ring oscillator level accounting not only for front-end of line devices but also for interconnects. It is demonstrated that FinFETs fail to maintain the performance at scaled dimensions, while VFETs demonstrate good scalability and eventually outperform lateral devices both in speed and power consumption. Lateral GAAFETs show better scalability with respect to FinFETs but still consume 35% more energy per switch than VFETs if made under 5-nm node design rules. [ABSTRACT FROM AUTHOR]

This paper presents an extensive investigation of the properties of the trap with activation energy equal to 0.6 eV, which has been demonstrated to be responsible for current collapse (CC) in AlGaN/GaN HEMTs. The study was carried out on AlGaN/GaN HEMTs with increasing concentration of iron doping in the buffer. Based on pulsed characterization and drain current transient measurements, we demonstrate that for the samples under investigation: 1) increasing concentrations of Fe-doping in the buffer may induce a strong CC, which is related to the existence of a trap level located 0.63 eV below the conduction band energy and 2) this trap is physically located in the buffer layer, and is not related to the iron atoms but—more likely—to an intrinsic defect whose concentration depends on buffer doping. Moreover, we demonstrate that this level can be filled both under OFF-state conditions (by gate-leakage current) and under ON-state operation (when hot electrons can be injected to the buffer): for these reasons, it can significantly affect the switching properties of AlGaN/GaN HEMTs. [ABSTRACT FROM AUTHOR]

A compact microelectromechanical (MEM) switch design and associated family of logic gates, memory cells, and other basic very-large-scale integration (VLSI) digital circuit sub blocks are proposed to ensure zero crowbar current in addition to zero leakage current while minimizing mechanical delay. The circuit design methodology introduced in this paper also provides for lower device count and hence lower operating power consumption. A prototype of the MEM switch design is demonstrated. [ABSTRACT FROM PUBLISHER]

This paper presents a novel 2-D–3-D switchable gate driver circuit for active-matrix liquid crystal displays (AMLCDs) applications using the hydrogenated amorphous silicon (a-Si:H) technology. While consisting of 12 thin-film transistors (TFTs), the proposed gate driver circuit includes a pull-up circuit, two alternative circuits, and a key pull-down circuit. To provide a stable output waveform for switching between the 2-D and 3-D modes in AMLCD panel, the proposed circuit can improve the threshold voltage shift of a-Si:H TFT using reversed bias stress. Based on a real circuit integrated on glass with a standard five-mask process applied to a large-sized FHD TFT-LCD panel, the layout area of each gate driver circuit is 359.25 \mum\times\, 2296.25 \mum . In addition, the power consumption of a 12-stage gate driver circuit is 3.25 and 7.21 mW, while operating at 2-D and 3-D modes, respectively. Measurement results indicate that the output waveform, including output voltage, rising time, and falling time can be stabilized and made almost equal to the initial state after the reliability test at 100 ^\circC over 240 h. [ABSTRACT FROM AUTHOR]

In this paper, unclamped inductive switching (UIS) performance of the novel silicon–oxide–nitride–oxide–silicon (SONOS) gate power MOSFET (SG-MOSFET) is analyzed. The avalanche energy absorption of the SG-MOSFET at UIS is 5.2 times that of the conventional power MOSFET. Analysis shows that the improvement is due to the heavily doped p-body used in the device. Moreover, the influence of the structural parameters on the UIS performance of the device is experimentally characterized. Measurement results show that the UIS performance is not sensitive to the \p^+ contact width and slightly degrades with a larger gate length. Furthermore, the results show that it is promising to further improve the UIS performance of the device by using a more efficient charge trapping material in the gate dielectric to allow further increase in the p-body doping concentration. [ABSTRACT FROM PUBLISHER]

One of the most important degradation modes in CMOS technologies, the bias temperature instability (BTI) has been known since the 1960s. Already in early interpretations, charge trapping in the oxide was considered an important aspect of the degradation. In their 1977 paper, Jeppson and Svensson suggested a hydrogen-diffusion controlled mechanism for the creation of interface states. Their reaction–diffusion model subsequently became the dominant explanation of the phenomenon. While Jeppson and Svensson gave a preliminary study of the recovery of the degradation, this issue received only limited attention for many years. In the last decade, however, a large number of detailed recovery studies have been published, showing clearly that the reaction–diffusion mechanism is inconsistent with the data. As a consequence, the research focus shifted back toward charge trapping. Currently available advanced charge-trapping theories based on switching oxide traps are now able to explain the bulk of the experimental data. We give a review of our perspective on some selected developments in this area. [ABSTRACT FROM PUBLISHER]

This paper presents an evaluation of laterally double-diffused MOS transistors in synchronous dc–dc buck converters using a physical-based mixed device and circuit simulation. It is observed that impact ionization of the low-side transistor can be very high after the dead-time drain overshoot voltage point. In addition, heavy ion irradiation degrades power MOSFET performance and may lead to a potential circuit malfunction due to a significant increase in transient current if heavy ions strike the dc–dc buck converter at a critical time during switching. [ABSTRACT FROM PUBLISHER]

In this paper, the unclamped inductive switching (UIS) behavior of an inverted L-shaped source trench power MOSFET is numerically analyzed and experimentally characterized. The measured avalanche energy absorption at UIS of the new trench power MOSFET is 2.1 times that of the conventional trench power MOSFET. This is explained by numerical simulation, which shows that the voltage drop across the emitter/base junction in the parasitic bipolar junction transistor of the new structure is smaller than that of the conventional structure. The influence of structural and device size variation of the new trench power MOSFET on UIS performance is also investigated. Results show that the avalanche current density at UIS is a strong function of the \p^+-region width and the device size. Furthermore, the effect becomes very significant as the device size becomes very small. [ABSTRACT FROM PUBLISHER]

In this paper, the effect of various device design engineerings such as channel engineering, i.e., graded channel (GC), gate stack (GS) engineering (high-\kappa), and dual-material gate (DMG) on double-gate MOSFET (DG MOSFET) have been analyzed using ATLAS device simulator. Furthermore, the combinations of these technologies i.e., GC, along with GS engineering, i.e., GCGSDG, and GS together with DMG, i.e., GS dual-material DG (GSDMDG), have been taken into consideration. The simulation results demonstrate that, out of the several design engineerings, the GCGSDG is the most suitable for high-speed switching applications. However, the GSDMDG provides superior performance as an amplifier. [ABSTRACT FROM PUBLISHER]

This paper presents, for the first time, the study of the application of a lateral diffused metal–oxide–semiconductor field-effect transistor (LDMOSFET) in a common-gate configuration to radio-frequency (RF) transmit/receive (T/R) switching circuits. A single-pole double-throw (SPDT) 900-MHz T/R switch is implemented using 0.25-\mu\m LDMOSFET foundry technology. Measured results show that our switching circuit can achieve a low insertion loss of 0.82 dB and a high power handling capability of 27 dBm. This result is promising in integrating power management integrated circuits, RF power amplifiers, and switching circuits in a single chip, based on LDMOSFET technology, to realize an RF transmit front-end system-on-chip solution. [ABSTRACT FROM AUTHOR]