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The first part of this paper presented mymargin the device-level comparison of emerging materials (In0.53Ga0.47As and 2-D materials) and device architecture (NW FETs) with s-Si FinFETs. In order to further understand the performance and energy efficiency of these device options for future technology nodes, it is required to go beyond the device-level comparison by accounting for not only intrinsic but also the extrinsic parasitic elements. In this paper, we present the comparison of s-Si, In0.53Ga0.47As, and 2-D material-based n-type MOSFETs using the circuit-level figure of merits across three successive future technology nodes. The analysis incorporates both device characteristics obtained from an advanced quantum mechanical simulation tool and circuit-level comparison, which accounts for device parasitic elements and wiring load. The results show that 2-D material DG MOSFETs present a more energy-efficient device option than s-Si and In0.53Ga0.47As FinFETs in sub-0.7-V supply voltage regime and In0.53Ga0.47As nanowire (NW) FETs can outperform s-Si multi-gate (MuG) FETs and 2-D material FETs, but when considering non-idealities, s-Si NW FETs remain both faster and more energy-efficient device option. [ABSTRACT FROM AUTHOR]

In this paper, an analytical model has been developed to observe the recombination losses involved in a tunnel oxide passivated contact solar cell with a carrier-selective layer constituting polycrystalline silicon (poly-Si). The main focus of this paper is to observe the contribution of each component of recombination current density and its effect on open-circuit voltage, Voc. The effect of emitter saturation current density (Joe), surface recombination velocity, substrate thickness, and doping density of carrier-selective layer on Voc has been presented. The analysis indicates that Voc = 766 mV can be achieved for Joe = 2 fA/cm2, and a doping density of poly-Si > 1021cm−3 in a c-Si/SiO2/poly-Si contact for a 50- $\mu \text{m}$ -thick substrate in case of ideal surface passivation. For identical conditions, Voc attains a lower value of 750mV for a 180- $\mu \text{m}$ -thick substrate. The dependence of Voc on bandgap of tunnel layers has also been observed by considering other materials like Si3N4 and SiC. These results from the analyticalmodel have been compared with results froma simulation using automat FOR simulation of HETerostructures v2.5 and have been found to be in good agreement with each other. [ABSTRACT FROM AUTHOR]

In negative capacitance field-effect transistors (NCFETs), drain current may decrease with increasing ${V}_{\mathrm {ds}}$ in the saturation region, leading to negative differential resistance (NDR). While NDR is useful for oscillator design, it is undesirable for most analog circuits. On the other hand, the tendency toward NDR may be used to reduce the normally positive output conductance ( ${g}_{ \mathrm {ds}}$ ) of a short-channel transistor to a nearly zero positive value to achieve higher voltage gain. In this paper, we analyze the NDR effect for NCFET in the static limit and demonstrate that it can be engineered to reduce ${g}_{\mathrm {ds}}$ degradation in short-channel devices. Small and positive $g_{\mathrm{ ds}}$ is achieved without compromising the subthreshold gain, which is crucial for analog applications. The 7-nm ITRS 2.0 FinFET with 0.7 V ${V}_{\mathrm {dd}}$ is used as the baseline device in this paper. [ABSTRACT FROM AUTHOR]

A comprehensive study of dielectric modulated (DM) drift regions for power devices is presented in this paper. The performance of this structure is theoretically analyzed and compared with both conventional and superjunction (SJ) structures. In this paper, an analytical model for DM drift regions with cylindrical cells is proposed and compared with linear cells. An optimal tradeoff between breakdown voltage (BV) and specific ON-resistance ( R\scriptscriptstyle ON,sp) is obtained by a methodology developed in this paper. 3-D simulations of DM structures with hexagonal cells approximated by cylindrical cells are conducted to verify the analytical model. Optimal BV– R\scriptscriptstyle ON,sp tradeoffs for devices with conventional and SJ drift regions are also obtained through the same methodology and verified by 3-D simulations. Static characteristics of these three different drift region structures in both Si and SiC power devices are compared. [ABSTRACT FROM AUTHOR]

In this paper, we have developed a physics-based analytical model for the electrical characteristics of passivated silicon carrier-selective contact (CSC) solar cells and validated it with numerical simulations. The model comprises analytical solutions of: 1) the Poisson equation, accurately capturing the level of inversion and accumulation at the crystalline silicon (c-Si) layer interfaces, and 2) the recombination current capturing the various recombination mechanisms at work in the solar cell. The calculations establish that CSC solar cells have the potential to achieve an efficiency greater than 26% even when both c-Si interfaces have realistic SRV values of 100 cm/s. The model helps illustrate the physics underlying the performance of CSC solar cells for variation in key device parameters such as surface recombination velocities, bulk lifetime, contact layer doping, and amorphous silicon (a-Si) thickness amongst others. By circumventing the need for resource-intensive numerical simulations, the analytical model described in this paper can assist in the design and development of high-performance CSC solar cells. [ABSTRACT FROM AUTHOR]

In this paper, the pinning process of pinned photodiodes (PPDs) is described by a new analytical model, assuming the PPD to be composed of inner and junction regions. There are two definitions of the pinning potential: maximum conduction band potential variation ($\Delta \varphi _{M}$) and maximum electron quasi-fermi level potential variation ($\Delta $ FP $_{M}$). The output of the previous pinning potential models is only an approximation of $\Delta \varphi _{M}$. In this paper, a comprehensive model is proposed in which both aforementioned definitions of pinning potential can be achieved analytically. The proposed model is a system of equations relating PPD’s main characteristics such as $\Delta \varphi _{M}$ and equilibrium full-well capacity to other main PPD parameters such as PPD spatial dimensions, impurity dopant concentrations, maximum inner region potential, and remnant carrier population at $\Delta \varphi _{M}$. The proposed model is verified by two previously reported experiment-based data. [ABSTRACT FROM AUTHOR]

This paper reports on the design optimization of double gate (DG) tunnel FET (TFET) for dynamic memory applications in sub-100-nm regime. It is shown that incorporation of lateral spacing ( L_ \text gap) between the gates, and an underlap region ( L\text {un}) between drain and back gate reduces state “0” degradation, which along with optimal biases, results in an improved Retention Time (RT) at 85 °C. The systematic design optimization increases RT from ~80 to ~300 ms with the use of L\text {gap} at 85 °C, which can be further improved to ~600 ms with the introduction of L\text {un} . The careful investigation shows the back gate scaled down to 25 nm with a front gate region of 100 nm, and operation even at elevated temperatures (125 °C). The insights into DG TFET DRAM operation in terms of individual as well as total lengths highlights the RT enhancement by a factor of 3 with constant total length (200 nm) and an improved scalability with total length scaled down to 160 nm. This paper provides new opportunities to realize TFET-based DRAM with improved RT, scalability, and high temperature operation. [ABSTRACT FROM PUBLISHER]

Confocal gyrotron traveling-wave tube (gyro-TWT) is capable of operating in higher order modes, so it is attractive in high-frequency (> 100 GHz) band. However, the reported experimental and simulation results of confocal gyro-TWT usually operated at fundamental harmonic, so high external magnetic field was essential. In this paper, a second harmonic 220-GHz confocal gyro-TWT was designed through linear and nonlinear theory and particle-in-cell (PIC) simulation. The key problem of suppressing the backward-wave oscillations (BWOs) of both fundamental and second harmonics was solved by limiting the cavity length of the first section less than the critical BWOs length. In PIC simulations, the gyro-TWT operates at HE07 mode with an output power of 4.55 kW, the efficiency of 2.2% gain of 21.8 and the −3 dB bandwidth of 6 GHz. The calculated results from the nonlinear theory are in good agreement with the results from PIC simulation. [ABSTRACT FROM AUTHOR]

In this paper, we present a surface potential-based explicit continuous model for a metal-ferroelectric-insulator-semiconductor (MFIS) type gate-all-around negative capacitance transistor (GAA-NCFET). Unlike previously reported models, an explicit formulation to calculate the electrical characteristics of GAA-NCFET is proposed. Our model includes the radial dependence of the electric field in the ferroelectric, ignored in the previous works and accurately captures ferroelectric material parameter variations in the nonhysteretic regime. In contrast to bulk NCFETs, GAA-NCFET characteristics show different bias dependence due to the absence of bulk charge. We also present analytical expressions for the terminal charges which are essential to obtain the trans-capacitances for transient simulations. We find that, compared with conventional MOSFETs, the gate charge saturates to a different fraction of its maximum value. Furthermore, the modeling of quantum mechanical effect and overlap capacitances in an MFIS NCFET structure is discussed. Finally, the proposed model has been implemented in Verilog-A and tested for the transient response of ring oscillator in a commercial circuit simulator. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel compact statistical model for the low-frequency noise (LFN) of MOS devices with halo implants. The compact model is suited for the incorporation in modern models, such as BSIM, PSP, and EKV, and can be used to predict the dependence of the LFN of halo-implanted MOSFETs with bias, temperature, geometry, and technological parameters. This compact model is based on the physics-based random telegraph noise (RTN) model, previously published by our group. The previous model was simplified in analytical expressions dependent on parameters and on physical quantities already calculated in modern compact models. Following the physics-based model, the LFN compact model predicts the large bias dependence of the LFN statistics induced by the halo implants in long-channel devices. Moreover, we show for the first time that the halo implants also induce a large temperature dependence of the LFN statistics for devices operated near the weak inversion or saturation, and the proposed compact model predicts this dependence. [ABSTRACT FROM AUTHOR]

In this paper, we develop an accurate analytical electrostatic potential model for both the n-type and p-type double-gate heterostructure tunnel field-effect transistors (H-TFETs). We solve the Poisson’s equation in four distinct regions inside the device, the depletion regions of the source, channel, and drain, and the drift-diffusion region of the channel, where the mobile charge carriers should be taken into account. It is shown that the model predicts the electrostatic potential profile of the various heterostructure devices with different material systems in all regions of the device operation accurately. The potential model is used for developing a model for the tunneling distance at the given energy level. Due to the physical nature of the models, the influence of the transistor parameters on the electrostatic characteristics of H-TFETs with desired heterojunction materials may be easily pursued. We show that the model results accurately predict the numerical simulation results for different device parameters. [ABSTRACT FROM AUTHOR]

In this paper, the read margin (RM) and write power (WP) of 3-D vertical resistive random access memory (VRRAM) are analyzed by considering the variation in RRAM cell (self-rectifying cell) characteristics. To demonstrate the cell variation effect on a large 3-D VRRAM array, we develop a modified lumping method in HSPICE simulator and show that this method substantially reduces the computation time while maintaining high accuracy. Read and write performances including cell variation are investigated according to various array sizes and RRAM characteristics. A large distribution of cell current reduces the RM but hardly affects the WP. Moreover, in 3-D VRRAM with a small number of wordline (WL) layers, a large on/off ratio (RHRS/RLRS) is advantageous for improving the RM and reducing the variation effect. In contrast, a large on/off ratio has little effect on the RM in 3-D VRRAM with many WL layers. This difference occurs because the increased leakage induced in the half-selected cells mainly affects the RM, and the half-selected cells are located in the selected vertical pillar in 3-D VRRAM. [ABSTRACT FROM AUTHOR]

In this paper, a universal analytical current model for a double-gate Si-based tunnel field-effect transistor (TFET) is presented considering the effects of charges in source depletion region and channel. An accurate surface potential model is developed first by solving the pseudo-2-D Poisson equations in the depletion regions, and then is used to calculate the drain tunneling current. The modeling results match well with that obtained from the Technology computer-aided design simulations under various biasing conditions, which indicate that the analytical current model would be very helpful for the further TFET-based circuits design. Furthermore, the influence of the source depletion is also studied, and the presented model with considering the source depletion region and the channel inversion charges is proved to be much more accurate than that ignoring the source depletion. [ABSTRACT FROM AUTHOR]

With the aid of an analytical and general model, this paper investigates the intrinsic difference in the negative-capacitance (NC) effect and design space between semiconductor-on-insulator (SOI) and double-gate (DG) metal–ferroelectric–insulator–semiconductor-type NC field-effect transistors (NCFETs) with a 2-D semiconducting transition-metal-dichalcogenide channel (2-D NCFET). By examining the distributions of internal charge, voltage gain, and capacitance matching over the whole bias range, the intrinsic difference in NC effects between these two topologies is pointed out and explained. Our study indicates that for an intrinsic DG 2-D NCFET, it is difficult to achieve sub-2.3 kT/q average subthreshold swing (SS). By contrast, the bias-dependent subthreshold internal charge and larger curvature of ferroelectric capacitance due to the independent backgate in the SOI 2-D NCFET enable larger design space and sub-2.3 kT/q average SS, making it more suitable for low-power applications. [ABSTRACT FROM AUTHOR]

In this paper, we report on the assessment of self-amplified silicon–oxide–nitride–oxide–silicon (SONOS) memory device architecture for sub-50-nm gate length (${L}_{g}$) through calibrated simulations. Self-amplification (SA) effect in tunnel field-effect transistor-based SONOS (T-SONOS) memory device has been analyzed. Results show that memory window ($\Delta {W}$) in T-SONOS cell increases as buried oxide thickness increases due to capacitive coupling between the front and back gates. Although the enhanced $\Delta {W}$ can also be achieved in inversion-mode SONOS (I-SONOS) device, its performance is deteriorated when the gate length is scaled down. We have compared the performance of I-SONOS and T-SONOS memory devices for ${L}_{g}$ varying from 100 to 25 nm. Results highlight that I-SONOS device cannot be programmed at ${L}_{g} ={25}$ nm and thus deteriorate the memory operation. However, SA T-SONOS at ${L}_{g} = {25}$ nm achieves ${W} \sim {6}$ V. In addition, the effect of underlap on the performance of T-SONOS cell has been analyzed, and it is shown that memory operation of 25-nm T-SONOS device can further improved with a drain side underlap of 20 nm. This paper provides new opportunities to design SA T-SONOS memory device for the next-generation nonvolatile memories. [ABSTRACT FROM AUTHOR]

This paper presents a comparison of switching performances between the in-situ oxide, gallium nitride (GaN) interlayer FET (OG-FET) and the conventional GaN metal–oxide–semiconductor FET (MOSFET), and explores the influence of the channel electron mobility on the device switching performance. GaN OG-FET is a novel structure with a pristine GaN layer grown between the gate oxide and the p-GaN enhancing the channel mobility up to 185 cm2/ $\text {V}\cdot \text {s}$ , which is over $3{\times}$ larger than that of the typical reported value (50 cm2/ $\text {V}\cdot \text {s}$) in GaN MOSFET. Owing to the high channel electron mobility, the GaN OG-FET showed a switching loss 30% lower than that of the conventional GaN trench MOSFET. Our results indicate that GaN OG-FET has the potential to attain greater efficiency, particularly at higher frequencies, showing a possible patch toward megahertz range conversions. [ABSTRACT FROM AUTHOR]

In our earlier work, we presented a percolation theory-based analytical model to estimate FinFET’s VT distribution due to fin edge roughness. The earlier models in the literature were based on minimum fin width, the limitations of which were discussed in detail. In this paper, we advance the percolation theory-based model to capture the variability in all key-device parameters, viz. I \mathrm{\scriptscriptstyle ON} , I \mathrm{\scriptscriptstyle OFF} , subthreshold slope, and VT . The entire distribution of these parameters obtained by the model is presented and compared against stochastic TCAD to demonstrate excellent match. The model reduces rms error in $\mu $ of various parameters by 5%–60%, and 20%–50% in $\sigma $ with respect to the minimum fin width-based models present in the literature. [ABSTRACT FROM PUBLISHER]

An analytical model for junctionless double-gate FETs (JLDGFETs) in the subthreshold region is proposed in this paper. As the analytical models based on Young’s approximation demonstrate certain limitations due to the heavily doped channel of the JLDGFET, it is essential to model the electrical characteristics of a JLDGFET using alternative methods. Therefore, in this paper, by using the Fourier series and Green’s function, the potential distribution ( \phi ( {x} , {y} )) in the channel is solved, and the hot-carrier effects and random dopant fluctuation are modeled using localized trap charges and macroscopic analysis. Using the calculated \phi (x, y), {I} _{{\mathsf {DS}}} and {V} _{{\mathsf {th}}} are solved analytically with respect to various L and t {\mathsf {ox}} variations, subthreshold swing, the drain-induced barrier lowering, the localized trap charges, and a single impurity dopant. All results from the analytical model are verified through comparisons with commercially available 2-D ATLAS numerical simulation results. [ABSTRACT FROM PUBLISHER]

The impact of triple metal with unalike work functions on the gate all around (GAA) tunnel FET is studied for the first time in this paper. An analytical model is introduced for surface potential and drain current of GAA triple metal tunnel FET with circular cross section, by using Poisson’s equation and Kane’s model. The modeling results are in good agreement with Synopsys 3-D TCAD results, thereby corroborating our analysis. The different metal work functions assist to create the potential barrier in the channel region to suppress the reverse tunneling from the drain side and also provides a more band bending at source end which revamp the drive current. [ABSTRACT FROM PUBLISHER]

In this paper, an n-p-n collector incorporated in the back side of a 4H-SiC trench IGBT is presented to reduce the turn-off energy loss. A comparative study between the proposed structure and the conventional structure is conducted through ATLAS. The simulation results have demonstrated that the turn-off energy loss is reduced by more than 82.96% with a slight degradation in the on-state voltage drop. [ABSTRACT FROM PUBLISHER]

A comprehensive study on the dielectric modulated (DM) drift region for power devices is presented in this paper. The performance of this drift region structure is theoretically analyzed and compared with other two structures: conventional and superjunction. In this paper, a study is focused on switching performance. The C – V relationships during switching are analytically derived, and the depletion widths predicted by the proposed analytical model agree well with simulation in a wide reverse bias region. The switching energy loss is evaluated based on the analytical model and its accuracy is verified by 2-D simulations. An effective depletion charge QD is defined as E\mathrm {loss} / breakdown voltage (BV), from which a figure of merit (FOM) of R\mathrm{\scriptscriptstyle ON,\mathrm {sp}}{}^\ast QD is proposed to compare the performances of these different drift region structures, considering both the conduction and switching losses. The discussions in part I on Si and silicon carbide device structures are extended in part II to include FOMs. It is found that the DM drift region structures show better R\mathrm{\scriptscriptstyle ON,\mathrm {sp}} -BV tradeoffs compared with the conventional structures, but slighter inferior FOMs. However, DM structures are still attractive for applications, where switching loss is less critical than the conduction loss, such as low frequency or soft switching. [ABSTRACT FROM PUBLISHER]

High-power, high-frequency gyrotrons are the only promising sources for the electron cyclotron resonance heating and current drive (ECRH&CD) in the present thermonuclear fusion plasma experiments and in future power plants. Compared to the hollow-cavity gyrotron design, the coaxial cavity gyrotron design facilitates improved mode competition control, which eventually increases the output power per tube. At KIT-IHM, the successful operation of a 170-GHz gyrotron has been demonstrated in the short-pulse regime, and the ongoing research activities are aiming to upgrade the existing coaxial cavity gyrotron from short-pulse (1–10 ms) to long-pulse (~ 1s) operation. In this paper, with the help of multiphysics simulations, the performance of the insert cooling system is verified for the continuous wave (CW) operation and the operating limits of the insert cooling systems are determined. The perfectly aligned coaxial Glidcop insert will be able to withstand operating conditions leading to a maximal heat flux of about 0.39 kW/cm2. The influence of insert misalignment on insert loading is also studied systematically in this paper. [ABSTRACT FROM AUTHOR]

A detailed presentation of the latest version of Leti-UTSOI compact model is provided. Leti-UTSOI2 is the first available model able to describe the behavior of ultrathin body and BOX fully depleted silicon-on-insulator transistors in all bias configurations, including strong forward back bias. In this paper, compact modeling of intrinsic currents and charges, including all physical effects required to describe decananometer transistors, is detailed. This model is valid for all independent double-gate architectures, very accurate and feature excellent predictability over technological parameters. [ABSTRACT FROM AUTHOR]

This paper presents the study of the chopper-stabilized magnetic field effect transistor (CHOPFET), a high-resolution silicon magnetic transducer. After a full description of its structure and operating principle, a 3-D multiphysics model is proposed. This model combines the electrical model of conventional silicon electronic devices (i.e., transistors) and the magnetic model in order to obtain accurate transduction effect prediction. Experimental results collected from a set of CHOPFET transducers fabricated in AMS $0.35~\mu \text{m}$ standard CMOS technology effortlessly match the simulations performed on the same process. Analysis and discussions reveal one key result: when the CHOPFET is appropriately biased, its channel current, ${I}_{\text {DS}}$ , can be lowered without magnetic sensitivity loss, i.e., the CHOPFET can achieve high-resolution performance even when operated in a low-power mode. [ABSTRACT FROM AUTHOR]

Performance of the crossbar memory array highly depends on the selector characteristics. In this paper, rigorous transient analyses are performed for a large-size crossbar memory array using novel NbO2-based selectors with a threshold switching behavior. To enable accurate and efficient array-level simulation, an electrostatic discharge-based compact model is employed to effectively describe the ${I}$ – ${V}$ characteristics of the selector. Multiple key design parameters of the selector are investigated, such as the threshold voltage, leakage current, and intrinsic switching speed. A sensitivity analysis is performed to evaluate the impact of hypothetical improvements in various selector parameters. In addition, the impacts of resistances of interconnect and memory element on the array-level access delay and energy dissipation are quantified. The results show that reducing the threshold voltage of selectors provides the most significant performance improvement, where up to 80% of the energy-delay product saving is observed if the threshold voltage is reduced by 50%. [ABSTRACT FROM AUTHOR]

Performance limitations of superjunction (SJ) devices due to charge imbalance (CI) are analyzed in this paper. It is demonstrated that in the presence of CI, the specific on-resistance has a quadratic dependence on blocking voltage, similar to a conventional drift region. We also show that by designing the SJ structure with an optimally modified pillar doping, we can achieve better performance under conditions of CI. The design guidelines presented in this paper are applicable to any semiconductor, although all calculations are based on silicon carbide. [ABSTRACT FROM AUTHOR]

This paper demonstrates the influence of nonuniform doping on the electrostatics of symmetric double-gate junctionless transistor using empirical modeling scheme. To present the clear insight into the device electrostatics of nonuniform doped channel, the peak of the doping concentration has been varied from Si/SiO2 interface of front gate to the back gate. The parameters explored in this paper are surface potential, electric field, drain current, threshold voltage, subthreshold slope, and drain-induced barrier lowering for different straggle factors and channel lengths. By properly optimizing the straggle value and peak of the doping concentration, device performance can be tuned accordingly. [ABSTRACT FROM AUTHOR]

Due to high surface-to-volume ratio, surface traps play crucial role in electronic properties of semiconductor nanowires and nanowire-based devices. Recently, it was experimentally demonstrated that surface traps even can induce conductivity type inversion in semiconductor nanowires. Here, we have performed theoretical and numerical analyses to investigate the influence of surface traps on semiconductor nanowire conductivity including possible inversion due to surface traps. The Poisson equation with consideration of both type of mobile charges and ionized donors was solved having surface trapped charges in Neumann boundary conditions. Different semiconductor materials and surface trap densities have been considered. Calculations were done considering single energy level of surface traps and then the results were generalized to exponential energetic distribution of surface states density. The effect of surface traps was analyzed both for low-doped and highly doped nanowires. It was shown that for moderate or lightly doped NWs, the conductivity type switching from n- to p-type can occur at small radii. The developed potential-based analytical model allows calculating the inversion charge raised due to surface traps. The accuracy of analytical calculations has been validated with TCAD simulations and qualitatively compared with published experimental data. This paper is useful for design optimization of nanowire-based photodetectors, sensors, and reconfigurable FETs. [ABSTRACT FROM AUTHOR]

In this paper, we develop a generic analytical model for 2-D electron gas (2DEG) density ( \mathrmn\mathrm{s}) and threshold voltage ( \mathrmV \mathrm{\scriptscriptstyle OFF}) of a fully strained graded ZnO-based heterostructure with a cap layer. The model is based on the continuity of electric field at the interfaces of different layers, dominant piezoelectric and spontaneous polarization components in different layers, Mg composition, and layer thickness. The generic model can be reduced to a simplified bilayer structure for calculating \mathrmn\mathrm{s} and \mathrmV \mathrm{\scriptscriptstyle OFF} . Results show that the graded heterostructure can result in higher values of 2DEG density and \mathrmV \mathrm{\scriptscriptstyle OFF} (absolute values) compared to the bilayer structure. A careful optimization of the structure is required to achieve a trade-off between \mathrmn\mathrm{s} and \mathrmV \mathrm{\scriptscriptstyle OFF} . An analytical expression of polarization charge density at buffer–barrier interface to better fit the experimental data available in the literature is also proposed. The model will be suitable for the design optimization of 2DEG density and \mathrmV \mathrm{\scriptscriptstyle OFF} for ZnO-based heterostructures. [ABSTRACT FROM PUBLISHER]

An equivalent-circuit model of shield differential through-silicon vias (SDTSVs) in 3-D integrated circuits (3-D ICs) is proposed in this paper. The proposed model is verified using the 3-D full-wave field solver High Frequency Simulator Structure, showing that it is highly accurate up to 100 GHz. Furthermore, a full-wave extraction method for the resistance–inductance–capacitance–conductance (RLCG) parameters of SDTSVs is also proposed in this paper, which can be applied to all of differential transmission lines. It is shown that the results of the RLCG parameters obtained from the full-wave extraction method agree well with that from the analytical calculation up to 100 GHz, further validating the accuracy of the proposed model. Finally, using the proposed model, a deep analysis of electrical characteristics of SDTSVs is carried out to provide helpful design guidelines for them in future 3-D ICs. [ABSTRACT FROM AUTHOR]

This paper presents an analytical model of the full well capacity (FWC) in pinned photodiode (PPD) CMOS image sensors. By introducing the temperature dependence of the PPD pinning voltage, the existing model is extended (with respect to previous works) to consider the effect of temperature on the FWC. It is shown, with the support of experimental data, that whereas in dark conditions the FWC increases with temperature, a decrease is observed if FWC measurements are performed under illumination. This paper also shows that after a light pulse, the charge stored in the PPD drops as the PPD tends toward equilibrium. On the basis of these observations, an analytical model of the dynamic behavior of the FWC in noncontinuous illumination conditions is proposed. The model is able to reproduce experimental data over six orders of magnitude of time. Both the static and dynamic models can be useful tools to correctly interpret FWC changes following design variations and to accurately define the operating conditions during device characterizations. [ABSTRACT FROM AUTHOR]

Ferroelectric FETs (FEFETs) are emerging devices with an immense potential to replace conventional MOSFETs by virtue of their steep switching characteristics. The ferroelectric (FE) material in the gate stack of the FEFET exhibits negative capacitance resulting in voltage step-up action which entails sub-60 mV/decade subthreshold swing at room temperature. The thickness of the FE layer ( T\textsf {FE}) is an important design parameter, governing the device-circuit operation. This paper extensively analyzes the impact of T\textsf {FE} on the device-circuit characteristics in conjunction with the interactions between FE and gate/drain capacitances. While it is well known that increasing T\textsf {FE} yields higher gain albeit with the possibilities of introducing hysteresis, our analysis points to other unconventional effects emerging in circuits as T\textsf {FE} is increased. Depending on the attributes of the underlying transistor, increasing T\textsf {FE} beyond a certain value may lead to loss in saturation and/or negative differential resistance in the output characteristics. While the former effect results in the loss in gain of a logic gate, the latter may yield hysteretic voltage transfer characteristics. We also discuss the effect of T\textsf {FE} on the circuit energy–delay. Our analysis shows that for high T\textsf {FE} , the delay of the circuit may increase with an increase in supply voltage. However, for voltages <0.25 V, FEFINFETs show an immense promise yielding 25% lower energy at iso-delay. [ABSTRACT FROM PUBLISHER]

With the aid of an analytical and scalable model, this paper explores the design space for negative-capacitance (NC) field-effect transistors (FETs) with a 2D semiconducting transition-metal-dichalcogenide channel. In addition, the impact of back-gate biasing on the design space and the body effect of 2D-NCFETs is also investigated. Our study indicates that, to mitigate the conflict between subthreshold swing and hysteresis and to maximize the design space for the 2D-NCFET, a thin buried oxide and an adequate reverse back-gate bias can be applied to achieve the optimum design. [ABSTRACT FROM PUBLISHER]

In this paper, we present a capacitance model for field-plate AlGaN/GaN High Electron Mobility Transistor (HEMTs) accounting for the contribution of substrate capacitances and cross-coupling between field plates. TCAD simulations are performed to analyze both these contributions and analytical expressions for charges corresponding to the cross-coupling and substrate capacitances are presented in terms of our existing surface-potential-based model. The modeled results are validated by comparing the time-domain waveforms of a test circuit using a mixed-mode simulation setup in which the impact of cross-coupling and substrate capacitances on accuracy of switching transients predicted by the model is discussed. [ABSTRACT FROM AUTHOR]

This paper proposes an analytical threshold voltage model for the dielectric pocket double gate (DP-DG) junctionless FETs (JLFETs). The channel potential function has been obtained by solving 2-D Poisson’s equation using an evanescent mode analysis with suitable boundary conditions. The potential function has then been used for modeling the threshold voltage to investigate the effects of the DP thickness and length on the short-channel effects of the structure. The effects of source and drain depletion regions have been included for improving the accuracy of the model. The model results of DP-DG JLFETs have been compared with the simulation data obtained from the 2-D TCAD ATLAS device simulator. [ABSTRACT FROM AUTHOR]

The global optimization of the balanced symmetric vertical superjunction (VSJ) device is proposed based on the R-well model for the first time to realize the unique minimum specific on-resistance $R_{{\mathrm{\scriptscriptstyle ON},\mathrm {min}}}$ . The R-well model, which is originated from our previous VSJ mode theory, shows the relationship between $R_{{\mathrm{\scriptscriptstyle ON}}} and the doping concentration N under the given pillar width W and breakdown voltage VB . The global R{\mathrm{\scriptscriptstyle ON}} optimization is realized to obtain the design formulas of N and the pillar length Ld . The calculated results are in good agreement with the simulations. It is demonstrated from the comparisons with the simulations and the existing experiments that the optimization in this paper realizes the unique $R_{{on,\mathrm {min}}}$ with a relationship of $R_{{\mathrm{\scriptscriptstyle ON}}}\propto V_{B}^{1.03}$ . The R-well model is also universal for other R_{on} optimizations. [ABSTRACT FROM AUTHOR]

This paper presents an analytical model of drain current in a silicon tunnel FET with a circular gate (CG TFET). The method involves the bifurcation of the complete geometry into a rectangular gate conventional TFET, and the CG TFET itself based on the number of solvable regions of the CG TFET. The 2-D Poisson equation is solved on the regions of focus of each structure, and both the substructures are mathematically connected through conditions of continuity to arrive at the solution for the original geometry. The effect of the circular gate is considered by segregating the circular region into a number of rectangular segments, and solving the Poisson equation on each of them. The model takes into account the effect of drain on channel potential, bandgap narrowing, and quantum correction. The model is validated by comparing the results with outputs from a TCAD simulation tool. [ABSTRACT FROM PUBLISHER]

In this paper, we propose an analytical model for the variable drift region width (VDRW) silicon-on-insulator lateral double-diffused MOS (SOI LDMOS) device. Using the proposed model, for example, the breakdown voltage 375 V of VDRW SOI LDMOS is obtained with a 18- \mu \textm drift region length, while the average value of the surface electric field can reach 20.8 V/ \mu \textm . A 3-D device simulator, Sentaurus, is used to investigate the performance of the VDRW structure. By analyzing the simulation results and the analytical values, it is proven that the proposed model can effectively optimize the doping profile and accurately forecast the breakdown voltage. [ABSTRACT FROM AUTHOR]

The modeling and analysis of recombination properties is one of the critical aspects in the design and development of high efficiency amorphous silicon (a-Si)/crystalline silicon (c-Si) heterostructure solar cell (SH-SC). In this paper, we have developed a recombination model pertinent for a-Si/c-Si SH-SC. Based on the model, an analytical expression for the relationship between effective carrier lifetime ( \tau \mathrm {eff} ) and excess carrier concentration ( \Delta n ), commonly termed as lifetime curve, is derived and the results are validated with the experimental data. The results show that the inverse of \tau \mathrm {eff} , after correcting for the contributions of Auger and radiative recombination in silicon, when plotted as a function of \Delta n$ , shows a linear characteristic, with each of the slope and the intercept, providing definitive details about the recombination processes occurring in the device. [ABSTRACT FROM PUBLISHER]

In this paper, we present analytical models which are valid in all regions of operation and can accurately predict the potential profile and the output, as well as the transfer characteristics of the gate-all-around heterojunction tunnel field-effect transistors. Our potential model takes into account the charge carriers in the channel, as well as the space charges in the depletion regions of the two reservoirs. Later, this potential model is utilized to calculate the band-to-band tunneling generation rates at any spatial coordinate in the tunneling volume. Next, these rates are integrated over tunneling volume to find the total tunneling current. This leads to an analytical model for the drain current. We validate our models against the data obtained via numerical simulations for several common heterojunction tunnel devices at various geometries and bias conditions. [ABSTRACT FROM AUTHOR]

To continue with the scaling of high-performance transistors, alternate materials and device architectures are being explored as replacements for contemporary strained-silicon (s-Si) FinFETs. While III–V materials, such as In0.53Ga0.47As, offer higher electron mobilities and injection velocities than s-Si, emerging 2-D materials and nanowire (NW) device architectures promise better immunity to short-channel effects. In this paper, we present a detailed device-level performance comparison of s-Si, In0.53Ga0.47As, monolayer black phosphorus (BP), and WS2-based planar and multigate (Fin and NW) n-MOSFETs across three successive future technology nodes. The analysis incorporates both intrinsic device characteristics obtained from an advanced quantum mechanical simulation tool and the effect of nonidealities using a physics-based analytical model. The results indicate that 2-D materials, such as monolayer BP, offers higher ON currents than s-Si and In0.53Ga0.47As for planar device architectures. However, compared to modern s-Si and In0.53Ga0.47As Fin and NW FETs, monolayer BP and WS2 double-gate MOSFETs are reported to offer lower ON currents due to the smaller footprint at scaled technology nodes. [ABSTRACT FROM AUTHOR]

The spin-transfer torque domain wall (DW) magnetic tunnel junction (MTJ) enables spintronic logic circuits that can be directly cascaded without deleterious signal conversion circuitry and is one of the only spintronic devices for which cascading has been demonstrated experimentally. However, experimental progress has been impeded by a cumbersome modeling technique that requires a combination of micromagnetic and SPICE simulations. This paper, therefore, presents a SPICE-only device model that efficiently determines the DW motion resulting from spin accumulation and calculates the corresponding MTJ resistance. This model has been validated through comparison to the authoritative micromagnetic-based model, enabling reliable prediction of circuit behavior as a function of device parameters with a 10 000 $\times $ reduction in the simulation time. This model thus enables deeper device and circuit investigation, advancing the prospects for nonvolatile spintronic computing systems that overcome the von Neumann bottleneck. [ABSTRACT FROM AUTHOR]

In this paper, we target the compact capacitance modeling of organic thin-film transistor (OTFTs) valid from depletion to accumulation regime taking into account the frequency dependence. The parameters used in the model are calculated through the unified model and parameter extraction method (UMEM). We include the effect related to the density of localizated states in the gate capacitance. Finally, we analyze the experimental derivative of the gate capacitance, and we demonstrate that our model predicts it with a high degree of accuracy. [ABSTRACT FROM AUTHOR]

In this paper, we develop an accurate compact model for work-function variation (WFV)-induced threshold voltage $({V}_{\textsf {th}})$ variations of various 5-nm candidates, in this case, Si SOI FinFETs, vertical gate-all-around nanowire FETs, and nanoplate FETs. Using the typical probability distribution function model to predict the effect of WFV, due to the ideal condition, an error occurs in ultrascaled devices. Therefore, to analyze the influence of WFV accurately, the error rate ($\alpha $) is corrected by considering irregular grain patterns (Voronoi method). In addition, the total number of grains on the metal surface can be calculated while considering the effective grain size and gate area due to the structural characteristics of the device. Finally, the model is benchmarked against 3-D TCAD simulations to demonstrate excellent accuracy [1.53% error in $\sigma $ (${V} _{\textsf {th}}$)]. Moreover, the accuracy is improved by more than 15 times compared with the existing analytical models. As a result, the proposed model based on binomial distribution is able to analyze the effect of WFV at a significantly lower computational cost than 3-D TCAD simulations. [ABSTRACT FROM AUTHOR]

Inverter delay is often evaluated as $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ , where ${C}$ is the load capacitance, ${V}_{\text {dd}}$ is the supply voltage, and ${I}_{\text {eff}}$ is the effective drive current derived by approximating the inverter switching trajectory with a linear model. The ${I}_{\text {eff}}$ model utilizes high and low drain currents conventionally measured in wafer acceptance tests and does not require extraction of any parameters. Ease of use combined with reasonable accuracy (~15%) is the main reason for wide application of $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ delay metrics. However, $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ expression produces large errors when applied to another two important basic circuits: NAND and NOR. This is because NAND and NOR circuits contain transistor series connections not accounted for in the inverter model. In this paper, an analytical solution for the transistor series connection influence on the discharge/charge operation in NAND/NOR circuits is provided. The model for NAND/NOR effective drive current (denoted as ${I}_{\text {stack}}$) developed in this paper maintains simplicity of the original ${I}_{\text {eff}}$ expression. It requires only one additional measurement of the linear current. Model accuracy was assessed by comparing to extensive SPICE delay simulations of NAND and NOR circuits designed using state-of-the-art MOS technologies. Comparison results show that $\textit {CV}_{\text {dd}}/{I}_{\text {stack}}$ equation provides ~15% accuracy for NAND/NOR circuits in line with $\textit {CV}_{\text {dd}}/{I}_{\text {eff}}$ accuracy for inverter. In an era of emphasis on low-power design, the developed model presents convenient means of exploring design space when optimizing circuit supply voltage for low-power operation. [ABSTRACT FROM AUTHOR]

We present a physics-based compact model that captures the behavior of phase-transition materials. The model includes a self-heating module that captures the change in temperature with device operation and the resulting phase change. This is the first compact model that captures the temperature-dependent multidomain switching and the hysteresis behavior seen in such devices. The model is implemented in Verilog-A and validated with experimental data for various geometries and temperatures. It is further coupled with industry standard BSIM-BULK, ASM-HEMT, and BSIM-CMG models for SPICE simulation and validated for various phase-transition FETs, illustrating the previously proposed steep switching effect and a subthreshold slope below the Boltzmann limit of 60 mV/decade. [ABSTRACT FROM AUTHOR]

A compact model for tunnel diode body contact (TDBC) silicon-on-insulator (SOI) n-MOSFETs was developed in this paper. The compact model is implemented in Verilog-A to simulate the dc and radio frequency (RF) performance of a TDBC SOI MOSFET. The TDBC SOI MOSFETs are successfully fabricated and are used to measure important transistor electrical parameters. The investigation results reveal that TDBC structure suppresses floating body effects (FBEs) as well as T-gate body (TB) contact structure and shows significant improvement in RF performance without introducing additional parasitic capacitances compared with the TB device. Kink phenomena and an abnormal subthreshold swing originating from FBEs are sufficiently suppressed. It is demonstrated that the TDBC SOI MOSFETs provide a promising concept for digital, analog, and RF applications. The outputs from this analytic model are in fair agreement with the TDBC experimental data, which validates the effectiveness and robustness of the compact model for TDBC SOI technology. Finally, good accuracy ensures that the proposed model is applicable for the implementation in circuit simulation tools. [ABSTRACT FROM AUTHOR]

In this paper, we will focus on the problem of modeling global or die-to-die variation in semiconductor devices. We will demonstrate that the process corner-based approach for modeling global variation, which has been the dominant approach for design validation, has fundamental limitations in predicting the circuit performance variation. We will then show how a full statistical model of variation can accurately predict circuit behavior and discuss some of the challenges in moving from a corner-based design to statistical simulations. [ABSTRACT FROM AUTHOR]

This paper presents a density functional theory-based first principle study to investigate the atomic-scale interactions of formaldehyde (H2CO) molecules with different oxygen containing functional groups of graphene oxide to identify which particular functional group possesses better adsorption capability toward H2CO molecule. The detailed study on formaldehyde adsorption has been conducted in terms of changes in structural, energetic, electronic, and transport properties of graphene oxides modeled with sp3 hybridized hydroxyl (-OH) and epoxy (C-O-C) groups on the carbon basal plane. Our computational results suggest that the graphene oxidized with only -OH group shows the highest affinity toward formaldehyde as compared with epoxy oxidized graphene and graphene oxide containing both the functional groups. The influence of vacancy defect on improving the sensing response of graphene oxide has also been studied. The results of current–voltage (${I}$ – ${V}$) characteristics reveal that graphene oxidized with only hydroxyl group can achieve an improvement in sensitivity by almost two times and five times as compared with graphene oxide containing both the functional groups and the pristine graphene sheet, respectively. Moreover, the selectivity test for some common indoor air pollutants was also carried out and the test results suggest that H2CO molecule is highly selective toward the -OH group of graphene oxide as compared with the epoxy group. [ABSTRACT FROM AUTHOR]

The field-plate (FP) technique suppresses the electric field crowding at the p-n junction by inducing the interface charges in the drift region. However, due to the modeling difficulty, the physical meaning cannot be elaborated via the conventional 2-D methods, not to mention the designing optimization. Therefore, the FP assistant reduced surface field effective concentration profile (ECP) is proposed in this paper to explore the physical insight of the FP assistant 2-D coupling. The ECP simplifies the sophisticated 2-D coupling by equating the FP assistant effect to the variation of the ECP. As a result, a simple and effective 1-D analytical model is presented to qualitatively and quantitatively explore the FP-induced surface field reshaping and its distinctive breakdown mechanism. The analytical solutions are found out to be consistent with the simulation results obtained from MEDICI, a commercial TCAD tool. [ABSTRACT FROM AUTHOR]