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Sb-rich GeSbTe-based phase-change memories (PCMs) were studied in the past years for their high switching speed to target storage class memory (SCM) applications. In this work, we show the advantages of an engineered multilayered Sb-rich GeSbTe stack compared with standard bulk reference materials. The studied multilayer-based PCM devices feature a lower programming current with respect to the equivalent bulk ones, preserving a high programming speed. Furthermore, multilayered Sb-rich GeSbTe brings better endurance performances for a wide programming current range and extremely reduced cycle-to-cycle (C2C) and device-to-device (D2D) variability along cycling verified in 4 kb PCM arrays. These results confirm improved yield and reliability obtained, thanks to multilayered PCM solution. [ABSTRACT FROM AUTHOR]

A gated diode with a charge trap insulator stack (Al2O3/Si3N4/SiO2) is proposed as a synaptic device and its potentiation and depression operations have been demonstrated. Using the band-to-band tunneling current, the gated diode operates with low current (in nanoampere range) and is suitable for low-power hardware-based neural networks. Since the proposed device has merits on simple and compact structure (half of a MOSFET) and compatibility with conventional CMOS technology, integration with CMOS peripheral circuits including neuron circuits and driving IC is possible. [ABSTRACT FROM AUTHOR]

Memory devices, such as the phase change memory (PCM), have recently shown significant breakthroughs in terms of compactness, 3-D stacking capability, and speed up for deep learning neural accelerators. However, PCM is affected by the conductance drift, which prevents a precise definition of the synaptic weights in artificial neural networks. Here, we propose an efficient system-level methodology to develop drift-resilient multilayer perceptron (MLP) networks. The procedure guarantees high testing accuracy under conductance drift of the devices and enables the use of only positive weights. We validate the methodology using MNIST, rand-MNIST, and Fashion-MNIST datasets, thus offering a roadmap for the implementation of integrated nonvolatile memory-based neural networks. We finally analyze the proposed architecture in terms of throughput and energy efficiency. This work highlights the relevance of robust PCM-based design of neural networks for improving the computational capability and optimizing energetic efficiency. [ABSTRACT FROM AUTHOR]

Commercial prospect of phase-change random access memory (PCRAM), considered as an encouraging option for future “universal” memory, is however challenged by its large programming current that severely impairs device scalability. The recent advent of the blade-type PCRAM configuration can effectively address this issue by shrinking the heated region. However, the thermoelectric (TE) effects that play a key role in write performances of conventional Lance-type PCRAM have not been systematically studied for this blade-type case to date. The influence of TE effects on the amorphization process of the blade-type PCRAM cell is therefore investigated here through the establishment of a comprehensive 3-D electrothermal and phase-transformation model. Two main typical TE effects, i.e., Thomson heat inside the Ge2Sb2Te5(GST) bulk region and Peltier heat at the GST-TiN heater interface, have been mimicked and discussed in detail. Simulation results show that both TE effects depend on the polarities of the programming currents, and the calculated Thomson heat is more than 20 times as much as Peltier heat. Accordingly, a novel skutterudite-based heater that exhibits more pronounced TE effects than TiN heater has been proposed. The practicality of reducing programming current by 13.8% and peak power by 17.9% is demonstrated using the improved version of the PCRAM cell. [ABSTRACT FROM AUTHOR]

Hardware acceleration of deep learning using analog non-volatile memory (NVM) requires large arrays with high device yield, high accuracy Multiply-ACcumulate (MAC) operations, and routing frameworks for implementing arbitrary deep neural network (DNN) topologies. In this article, we present a 14-nm test-chip for Analog AI inference—it contains multiple arrays of phase change memory (PCM)-devices, each array capable of storing 512 $\times $ 512 unique DNN weights and executing massively parallel MAC operations at the location of the data. DNN excitations are transported across the chip using a duration representation on a parallel and reconfigurable 2-D mesh. To accurately transfer inference models to the chip, we describe a closed-loop tuning (CLT) algorithm that programs the four PCM conductances in each weight, achieving <3% average weight-error. A row-wise programming scheme and associated circuitry allow us to execute CLT on up to 512 weights concurrently. We show that the test chip can achieve near-software-equivalent accuracy on two different DNNs. We demonstrate tile-to-tile transport with a fully-on-chip two-layer network for MNIST (accuracy degradation ~0.6%) and show resilience to error propagation across long sequences (up to 10 000 characters) with a recurrent long short-term memory (LSTM) network, implementing off-chip activation and vector-vector operations to generate recurrent inputs used in the next on- chip MAC. [ABSTRACT FROM AUTHOR]

The impact of phase change memory (PCM) device non-idealities on the deep neural network (DNN) inference accuracy is systematically investigated. Based on the experimental PCM data, statistical models of device non-idealities were extracted and incorporated into our PyTorch-based simulation framework for evaluations on the CIFAR-10 dataset. Our specific results include: 1) nonlinear ${I}$ – ${V}$ could incur a significant accuracy degradation, but it can be eliminated depending on how the input activations are encoded (e.g., no degradation with pulse-encoding schemes); 2) resistance variation and read noise induce a relatively mild accuracy degradation (< 1% with experimentally fit model), which can be further mitigated through variation-aware training (VAT); 3) maximizing accuracy over a given operating temperature range is attained through a “temperature-specific weight remapping” method developed in this work, accuracy variance of < 3% is demonstrated over a temperature range of ${T} \pm 15 ^{\circ }\text{C}$ ; and 4) resistance drift leads to a significant accuracy degradation over time and is the most challenging non-ideality to address by algorithmic means alone (drift coefficient < 0.015 is needed to achieve < 3% degradation in ten years). A “weight transfusion” (WT) method has been proposed to effectively recover the inference accuracy by incrementally activating additional pre-trained neurons over time. The main overhead is the additional area to store pre-trained weights beforehand, which is likely affordable given the high density of MLC PCM. [ABSTRACT FROM AUTHOR]

Phase change memory (PCM)-based “Analog-AI” accelerators are gaining importance for inference in edge applications due to the energy efficiency offered by in-memory computing. Nevertheless, noise sources inherent to PCM devices cause inaccuracies in the deep neural network (DNN) weight values. Such inaccuracies can lead to severe degradation in model accuracy. To address this, we propose two techniques to improve noise resiliency of DNNs: 1) drift regularization (DR) and 2) multiplicative noise training (MNT). We evaluate convolutional networks trained on image classification and recurrent neural networks trained on language modeling and show that our techniques improve model accuracy by up to 12% over one month. [ABSTRACT FROM AUTHOR]

We present a finite-element model for the confined-structure device integrating a phase change memory (PCM) and an ovonic threshold switch (OTS) selector. In this model, the threshold switching (TS) characteristics of the PCM and OTS were described by an embedded numerical model to simulate the operation of the integrated device. Both the SET and RESET processes have been well implemented in the integrated device by simulating. The electronic properties of the integrated device with various OTS material parameters have been investigated by simulating. Based on the simulated results, a moderate set-pulse has been obtained by optimizing only the OTS conductivity at a high-conductivity state. Further simulations for multilevel storage have been carried out in the integrated device based on the optimized OTS. The results indicate the confined-structure device with a larger length–diameter ratio will result in a more flexible operation window for multilevel storage. Particularly, when the length–diameter ratio of the confined-structure is 2:1 in the integrated device, five levels of device resistance could be obtained in the simulations of multilevel storage by applying multiple set-pulse or reset-pulse. This could guide further studies on the multilevel storage. [ABSTRACT FROM AUTHOR]

To understand the electrical switching behavior of Si15Te85-x Cux (1 ≤ x ≤ 10) series, I – V characterization has been performed on bulk as well as amorphous thin films of the as-prepared samples. Both the bulk glasses and amorphous thin films are found to manifest memory-type switching behavior. The threshold voltages of thin-film devices are found to be much lower than the bulk counterparts and hence could find application for phase change memory (PCM). The composition analyses of both have divulged the existence of intermediate phase (IP) in the composition range of 2 ≤ x ≤ 6. To examine the probability of the given glass for PCM application, Set–Reset studies have been performed on the glasses with a triangular pulse of 6 mA for set operation and rectangular pulse of 12 mA for the reset operation. The study has revealed a continuous repetition of few Set–Reset cycle by the Si–Te–Cu series. Raman studies carried out on the bulk glasses report the occurrence of blue shift over the composition in a regular manner. Further, SEM studies have been carried out on Si–Te–Cu samples to understand the morphological changes that would have occurred during switching. Additionally, thickness dependence of threshold voltage of representative Si15Te80Cu5 and Si15Te76Cu9 glasses has been carried out to reveal the relationship between threshold voltage and thickness. [ABSTRACT FROM AUTHOR]

The blade-type phase-change random access memory (PCRAM) has recently attained considerable interest due to its potential for providing low programming current, while its interfacial resistance (IR) characteristics that play an important role in temperature and programming current for conventional PCRAMs is yet to be deeply studied. To achieve this, a completely 3-D electro-thermal and phase-transformation model with inclusions of thermal boundary resistance (TBR) and electrical IR (EIR) at different layered interfaces were developed to assess the influence of the IRs on phase-transformation kinetics. It was found that the TBR at the chalcogenide/insulation interface as well as interfacial size dominates the resulting programming current that is almost independent of the TBR and EIR at chalcogenide/heater interface. In this case, an optimized blade-type device having platinum silicide heater and superlattice insulated encapsulation was proposed, allowing for a 38% reduction on “SET” current and a 40% reduction on “RESET” current, respectively. [ABSTRACT FROM AUTHOR]

A SPICE model for phase change memories (PCM) without relying on macro modules is developed in this work. The crystal fraction, physical geometry, and the conduction path of the amorphous region are treated as dynamic state variables to keep track of the memory cell status during SET and RESET. The memory cell resistance is calculated based on a detail 3-D resistance model to capture its transitional behavior during switching. The detail physical formulation correctly reproduced a recent observation of oscillation during the SET operation. The model has been implemented in SPICE, and the convergence of the model is demonstrated by simulations of a complete PCM array. The use of dynamic state variables also significantly reduces the number of internal nodes to one, which helps convergence and reduces the simulation time. [ABSTRACT FROM AUTHOR]

Using the reduced resistor network developed in Part I of this two-part article, we present practical design guidelines from device to architecture levels to achieve ultrahigh-density 3-D vertical resistive switching memory (VRSM). We first design both hexagon and comb arrays using 7-nm FinFET as pillar driving transistors (pillar drivers). Small-footprint pillar drivers are necessary for a high pillar areal density competitive to 3-D NAND. We then organize the arrays into an architecture using the compact staircase and highly conductive wordplane connection (WPC) to maximize array efficiency and chip density. We investigate the memory and selector requirements, tolerance of parasitic resistances, latency, and energy consumption for both hexagon and comb architectures. The results indicate that the hexagon array with large low-resistance state (LRS) and nonlinearity (NL) is required for ultradense 3-D VRSM. Compared to the comb array, the hexagon array benefits from a continuous WP pattern and yields a better tolerance of parasitic resistances and a smaller latency. The energy consumptions of both architectures are similar. Compared to the most advanced 3-D NAND, 3-D VRSM has higher chip density and shows better potential for future ultradense storage. [ABSTRACT FROM AUTHOR]

We propose energy bandpass filtering employed using the idea of antireflection heterostructures as means to reduce the energy requirements of a superlattice phase change memory (PCM) based on germanium telluride (GeTe) and Sb2Te3 heterostructures. Different configurations of GeTe/Sb2Te3 superlattices are studied using the nonequilibrium Green’s function approach. Our electronic transport simulations calculate the coupling parameter for the high-resistance covalent state, to 97% that of the stable low-resistance resonant state, maintaining the ON/OFF ratio of 100 for a reliable read operation. By examining various configurations of the superlattice structures, we conclude that the inclusion of antireflection units on both sides of the superlattice increases the overall ON/OFF ratio by an order of magnitude which can further help in scaling down of the memory device. It is also observed that the device with such antireflection units exhibits 32% lesser RESET voltage than the most common PCM superlattice configurations. Moreover, we also find that the ON/OFF ratio in these devices is also resilient to the variations in the periodicity of the superlattice. [ABSTRACT FROM AUTHOR]

A multilevel cell (MLC) memristor that provides high-density on-chip memory has become a promising solution for energy-efficient artificial neural networks (ANNs). However, MLC storage that stores multiple bits per cell is prone to device variation. In this paper, the device variation tolerance of ANN training is investigated based on our cell-specific variation modeling method, which focuses on characterizing realistic cell-level variation. The parameters of cycle-to-cycle variation (CCV) and device-to-device variation (DDV) are extracted separately from the experimental data of a 39-nm, 1-Gb phase-change random access memory (PCRAM) array. A quantized neural network designed for low bit-width (≥6-bit) training is used for simulations to demonstrate the potential of MLC storage. Our results demonstrate that training is more vulnerable to DDV than CCV, and CCV can even compensate for accuracy degradation caused by severe DDV. As a result, for a multilayer perceptron (MLP) on Modified National Institute of Standards and Technology (MNIST) database, 95% accuracy can be achieved with three MLC PCRAM devices per weight, which is a 40% reduction in the number of cells compared with using conventional single-level cells (SLCs). If the size of DDV is reduced by half, then only two cells, that is 60% fewer cells than using SLC, are needed. [ABSTRACT FROM AUTHOR]

Off-chip memory access is the primary bottleneck toward accelerating neural network operations and reducing energy consumption. In-memory training and computation using emerging nonvolatile memories (eNVMs) have been proposed to address this problem. However, a small number of conductance states limit in-memory online learning performance. Here, we introduce a device-algorithm co-design approach and its application to phase change memory (PCM) for improving learning accuracy. We present an adaptive quantization method, which compensates the accuracy loss due to limited conductance levels and enables high-accuracy unsupervised learning with low-precision eNVM devices. We develop a spiking neural network framework for NeuroSim platform to compare online learning performance of PCM arrays for analog and digital implementations and benchmark the tradeoffs in energy consumption, latency, and area. [ABSTRACT FROM AUTHOR]

High endurance ovonic threshold switch (OTS, here, TeAsGeSiSe-based) is integrated with phase change memory (PCM, here, doped Ge2Sb2Te5) to form a 3-D stackable pillar-type device. With the help of an etch buffer layer and a damage-free pillar reactive-ion etching process, we successfully demonstrate one-selector (OTS)/one-resistor (PCM) (1S1R OTS-PCM) pillar device without OTS/PCM composition modification. High temperature 400 °C annealing tests show this 1S1R OTS-PCM pillar device is back end of line compatible. We report the fundamental behavior of the OTS and the operation scheme of the 1S1R OTS-PCM device. The new Vth read scheme is proposed and excellent electrical performance is demonstrated. It provides the fast turn ON/ OFF speed which enables 10-ns fast RESET speed. Program endurance greater than 109 cycles is achieved, and read endurance is higher than 1011 cycles. [ABSTRACT FROM AUTHOR]

In this paper, a new continuous multilevel compact model for phase-change memory (PCM) is proposed. It is based on the modified rate equations with the introduction of a variable related to material melting. The model is evaluated using a large set of dynamic measurements and shows a good accuracy with a single model card. All fitting parameters are discussed, and their impacts are detailed. Full circuit simulation is performed. Good convergence and fast simulation time suggest that this new compact model can be exploited for PCM circuit design. [ABSTRACT FROM AUTHOR]

The high current density required by magnetic tunneling junction (MTJ) switching driven by the spin transfer torque (STT) effect leads to large power consumption and severe reliability issues, hindering the timetable for STT magnetic random access memory to mass market. By utilizing the voltage-controlled magnetic anisotropy (VCMA) effect, the MTJ can be switched by the voltage effect and is postulated to achieve ultralow power (fJ). However, the VCMA coefficient measured in experiments cannot meet the requirement for MTJ with dimensions below 100 nm. And an external in-plane magnetic field usually is demanded for precessional VCMA switching. Here, in this paper, a novel approach for the amplification of the VCMA effect, which borrows ideas from negative capacitance, is proposed. The feasibility of the proposal is proved by physical simulation and in-depth analysis. Since the amplified VCMA effect, the external magnetic field can be eliminated. A three-terminal novel MTJ memory cell is designed with which both low power and high speed can be achieved. [ABSTRACT FROM AUTHOR]

Stochastic behaviors of resistive random access memory (RRAM) play an important role in the design of cross-point memory arrays. A Monte Carlo (MC) compact model of oxide RRAM is developed and calibrated with experiments on various device stack configurations. With MC SPICE simulations, we show that an increase in array size and interconnect wire resistance will statistically deteriorate write functionality. Write failure probability (WFP) has an exponential dependence on device uniformity and supply voltage (VDD), and the array bias scheme is a key knob. Lowering array VDD leads to higher effective energy consumption (EEC) due to the increase in WFP when the variation statistics are included in the analysis. Random access simulations indicate that data sparsity statistically benefit write functionality and energy consumption. Finally, we show that a pseudo-subarray topology with uniformly distributed preforming cells in the pristine high-resistance state is able to reduce both WFP and EEC, enabling higher net capacity for memory circuits due to improved variation tolerance. [ABSTRACT FROM AUTHOR]

High reset energy is an ongoing issue for phase-change memory (PCM) devices. Prior work demonstrates that smaller PCM switching volume and thermal isolation can reduce the reset energy. In this paper, we fabricate and measure a planar confined PCM device with a multilayer dual-layer stack (D'S) of SiO2/Al2O3 insulator. Devices with contact area of 500 × 20 nm and lengths of 2 μm show exceptionally low reset energies of 18.25 ± 15.8 pJ and low reset current densities of 0.94 ± 0.51 MA/cm2. Implementing the D'S enables a 60% reduction in reset energy compared with SiO2-isolated devices. [ABSTRACT FROM PUBLISHER]

Phase-change memory (PCM) has undergone significant academic and industrial research in the last 15 years. After much development, it is now poised to enter the market as a storage-class memory (SCM), with performance and cost between that of NAND flash and DRAM. In this paper, we review the history of phase-transforming chalcogenides leading up to our current understanding of PCM as either a storage-type SCM, with high-density and better than NAND flash endurance, write speeds, and retention, or a memory-type SCM, with fast read/write times to function as a nonvolatile DRAM. Several of the key findings from the community relating to device dimensional scaling, cell design, thermal engineering, material exploration, and storing multiple levels per cell will be discussed. These areas have dramatically impacted the course of development and understanding of PCM. We will highlight the performance gains attained and the future prospects, which will help drive PCM to be as ubiquitous as NAND flash in the upcoming decade. [ABSTRACT FROM AUTHOR]

The stochastic nature of the switching mechanism of phase-change memory (PCM) arrays, which is a drawback for memory applications, can fruitfully be exploited to implement primitives for hardware security. By applying a set voltage pulse, whose amplitude corresponds to a switching probability of 50%, to a memory array initially placed in the full-reset state, half of the memory bits are statistically switched and programmed to state “1,” whereas the remainder of the bits persist in state “0.” Such a natural randomness can be exploited to create a true random number generator (TRNG), which is the building block of cryptographic applications. The feasibility of a TRNG by means of self-heating PCM cells is assessed and demonstrated through simulations based upon the random network model, i.e., a microscopic transport model previously developed and tested by the authors. [ABSTRACT FROM PUBLISHER]

Current large-scale implementations of deep learning and data mining require thousands of processors, massive amounts of off-chip memory, and consume gigajoules of energy. New memory technologies, such as nanoscale two-terminal resistive switching memory devices, offer a compact, scalable, and low-power alternative that permits on-chip colocated processing and memory in fine-grain distributed parallel architecture. Here, we report the first use of resistive memory devices for implementing and training a restricted Boltzmann machine (RBM), a generative probabilistic graphical model as a key component for unsupervised learning in deep networks. We experimentally demonstrate a 45-synapse RBM realized with 90 resistive phase change memory (PCM) elements trained with a bioinspired variant of the contrastive divergence algorithm, implementing Hebbian and anti-Hebbian weight updates. The resistive PCM devices show a twofold to tenfold reduction in error rate in a missing pixel pattern completion task trained over 30 epochs, compared with untrained case. Measured programming energy consumption is 6.1 nJ per epoch with the PCM devices, a factor of ~ 150 times lower than the conventional processor-memory systems. We analyze and discuss the dependence of learning performance on cycle-to-cycle variations and number of gradual levels in the PCM analog memory devices. [ABSTRACT FROM PUBLISHER]

Relatively large noise of phase change material is one of the obstacles for realization of multilevel cell (MLC) using phase change memory (PCM) technology. We experimentally verify that the noise in PCM can be lowered as much as $\sim 4$ times by a novel PCM cell which utilizes metal nitride liner to provide an alternative conductive path to the amorphous region with large noise. Program-and-verify (PNV) simulation based on noise measurement data confirms that the small noise of a PCM cell with metal nitride liner improves the MLC performance either by reducing number of PNV iterations or bit-error rate. [ABSTRACT FROM PUBLISHER]

Resistance drift of the amorphous states of multilevel phase change memory (PCM) cells is currently a great challenge for the commercial implementation of a reliable multiple-bit-per-cell memory technology. This paper reports observation of a stable intermediate state for a multilevel PCM cell that is achieved through nonuniform heating with a square current injection top electrode. Drift coefficient of the intermediate state is an order of magnitude lower than reset and has weaker temperature dependence. Using finite-element simulations and an analytical model for the subthreshold current–voltage characteristics, based on thermally activated hopping of charge carriers across Coulombic donor-like traps, we conclude that the defect density is two orders of magnitude larger in the intermediate state. We attribute the low drift coefficient of the intermediate state to a large number of stable interfacial defects which dominate the electron transport. Current findings give way to a more stable ultrahigh-density PCM device. [ABSTRACT FROM PUBLISHER]

For the first time, we comprehensively evaluate 6T SRAM stability and performance using monolayer and bilayer transition metal dichalcogenide (TMD) devices based on the ITRS 2028 (5.9 nm) node. Our study indicates that, with excellent device electrostatics and superior stability, the monolayer TMD is favored for low-power SRAM applications, while the bilayer TMD, with higher carrier mobility, is more suitable for relaxed channel length and high-performance SRAM applications. [ABSTRACT FROM AUTHOR]

Thermoelectric effects are envisioned to reduce programming currents in nanopillar phase-change memory (PCM) cells. However, due to the inherent symmetry in such a structure, the contribution due to thermoelectric effects on programming currents is minimal. In this paper, we propose a hybrid PCM structure, which incorporates a twofold asymmetry specifically aimed to favorably enhance the thermoelectric effects. The first asymmetry is introduced via an interface layer of low thermal conductivity and high negative Seebeck coefficient, such as polycrystalline SiGe, between the bottom electrode contact and the active region comprising the phase-change material. This results in an enhanced Peltier heating of the active material. The second one is introduced structurally via a taper that results in an angle-dependent Thomson heating within the active region. Various device geometries are analyzed using 2-D-axis-symmetric simulations to predict the effect on programming currents as well as for different thicknesses of the interface layer. A programming current reduction of up to 60% is predicted for specific cell geometries. Remarkably, we find that due to an interplay of Thomson cooling in the electrode and the asymmetric heating profile inside the active region, the predicted programming current reduction is resilient to fabrication variability. [ABSTRACT FROM PUBLISHER]

Using two phase-change memory devices per synapse, a three-layer perceptron network with 164 885 synapses is trained on a subset (5000 examples) of the MNIST database of handwritten digits using a backpropagation variant suitable for nonvolatile memory (NVM) + selector crossbar arrays, obtaining a training (generalization) accuracy of 82.2% (82.9%). Using a neural network simulator matched to the experimental demonstrator, extensive tolerancing is performed with respect to NVM variability, yield, and the stochasticity, linearity, and asymmetry of the NVM-conductance response. We show that a bidirectional NVM with a symmetric, linear conductance response of high dynamic range is capable of delivering the same high classification accuracies on this problem as a conventional, software-based implementation of this same network. [ABSTRACT FROM AUTHOR]

Joule heating in phase change memory (PCM) controls programming characteristics, read disturb, and programming disturb. To optimize the energy consumption and reliability of PCM, a thorough understanding of Joule heating as a function of the electrical operation of the device is thus strongly required. This paper presents a comprehensive characterization of thermoelectric (TE) effects in PCM operated at positive and negative voltage polarity. The impact of polarity was studied for all major temperature-dependent properties of the PCM device, namely, melting, crystallization, ion migration, threshold switching, and holding. It was demonstrated that heating is less efficient under negative voltage, compared with positive voltage. It was also shown that the positive and negative voltages needed to induce all above phenomena display a universal correlation. We propose a unified finite-element model for the PCM, which correctly accounts for the observed polarity-dependent heating and the universal voltage characteristics. The impact of isotropic scaling on TE is finally addressed. [ABSTRACT FROM PUBLISHER]

A novel one-transistor-n-resistors (1TnR) array architecture is demonstrated as a cost-effective solution to the sneak path problem in large-scale cross-point memory arrays. In a 1TnR array, a single transistor (1T) with a 1D channel effectively controls a number of resistive switching nonvolatile memory (NVM) cells (nR) while limiting the sneak leakage current within the 1D channel without sacrificing the device density. To maximize these benefits, a carbon nanotube FET (CNFET) is employed as the 1D selection device, due to its near-ballistic electrical transport properties even at a small device width. Experimental demonstrations of the CNFET-based 1TnR concept are presented with two promising resistive switching NVM candidates: 1) resistive random access memory (RRAM) and 2) phase-change memory (PCM). Here, we report that the integrated bipolar Al2O3-based RRAM consumes programming energies as low as 0.1–7 pJ per bit and has a high programming endurance of up to 10^6\vphantom \sum ^R^R cycles. The 1TnR RRAM cell also has self-compliance characteristics, because the semiconducting carbon nanotube (CNT) that serves as the bottom electrode limits the device current. The unipolar PCM cells integrated with CNFETs show uniform electrical characteristics with high ON-/OFF-resistance ratios of >10. Owing to the extremely small contact area between the phase change material, Ge2Sb2Te5, and the CNT, remarkably low programming currents of <1~\mu \textA are achieved. [ABSTRACT FROM PUBLISHER]

Data retention and its statistics are the key issues for the development of next generation phase-change memory (PCM) arrays. For this reason, the understanding and modeling of cell-to-cell and cycle-to-cycle variabilities of retention time are essential. This paper provides an extensive experimental characterization of retention statistics in 45-nm PCM technology and presents a Monte Carlo model for variability based on a Gaussian spread in the activation energy for crystallization. Results show that both cell-to-cell and cycle-to-cycle variabilities are well explained by a Gaussian spread in the activation energy for crystallization, due to local composition/structure changes in PCM active volume. [ABSTRACT FROM PUBLISHER]

Phase-change memory (PCM) is an emerging technology for faster nonvolatile memory where a small volume of phase-change material is switched between amorphous and crystalline states to provide distinct logic levels. A major difficulty with these devices is the high-power requirement for set and reset operations. In this brief, we computationally analyze a vacuum-insulated self-aligned Ge2Sb2Te5 nanowire (NW) PCM device and propose a way to control the placement and orientation of the NWs. The analysis is performed using 2-D rotationally symmetric finite-element simulations with temperature-dependent material parameters and accounting for thermoelectric effects. Simulation results predict a $\sim 10\times $ reduction in current required for reset operation and minimal thermal crosstalk when compared with a similarly sized conventional mushroom cell due to effective suppression of lateral heat loss. The operation of the vacuum-insulated NW devices is also almost independent of current polarity (unlike that of the mushroom cell), which can be advantageous for more flexible array programming schemes. These devices can be used to build densely packed PCM with lower power consumption and less thermal crosstalk. [ABSTRACT FROM AUTHOR]

We introduce a new technique to study the crystallization process in phase-change memory. By this technique, crystallization is characterized in the ON-state at extremely low currents, allowing to extend the time scale of crystallization times to more than two decades. To describe the pulse-induced crystallization in the set regime, we develop a finite-element method model based on localized conduction in the amorphous phase and non-Arrhenius crystallization kinetics. The range of crystallization times is then extended to even lower currents in the subthreshold regime, where the model allows describing the crystallization kinetics thus providing the physics-based prediction of read disturb. [ABSTRACT FROM AUTHOR]

In this paper, a 3-D resistance model is proposed for phase-change (PC) memory cell based on cell geometry and RESET current. Explicit expression is developed for PC radius in terms of RESET current, cell geometry, and material property. Conformal mappings are used for SET and RESET resistance calculation in 2-D models, which solve the problem of current crowding in structures with complex boundary condition. In the 3-D model development, additional spreading resistance is considered, together with the bulk resistance stemmed from 2-D model to form the eventual complete expression. Models show good consistency with finite element simulation and experimental data. [ABSTRACT FROM AUTHOR]

To satisfy the growing market demand for embedded nonvolatile memory, alternative solutions to Flash technology are currently under investigation. Among these, phase change memory (PCM) is attracting strong interest due to the low cost of integration with the CMOS front-end and good scalability. Embedded PCM, however, must feature high reliability during both packaging and functional stages. This paper studies reliability of PCM based on Ge-rich GeSbTe, providing evidence for resistance drift and decay in both the reset and set states. Set-state instability is attributed to grain-boundary relaxation and grain growth. A unified model is presented, capable of predicting the reliability of set/reset states at elevated temperature. [ABSTRACT FROM AUTHOR]

In this paper, we examine the problem of the drift of the low-resistance state (LRS) in phase change memories based on C or N doped and undoped Ge-rich Ge2Sb2Te5 . A novel procedure, named R–SET technique, is proposed to boost the SET speed of these innovative phase change materials by overcoming the decrease of crystallization speed caused by Ge enrichment. The R–SET technique allows, at the same time, an optimized SET programming of the memory cell and the reduction of the LRS drift with respect to standard SET procedures. A circuit that generates the desired R–SET pulse based on a time reference scheme is proposed and discussed. [ABSTRACT FROM PUBLISHER]

Phase change memory (PCM) is the most mature among the novel memory concepts. Embedded PCM technology can be a real breakthrough for process cost saving and performances. Nevertheless, for specific applications some improvement in high temperature data retention characteristics is needed. In this paper, we present an optimized Gex\rm Sby\rm Tez phase change material, able to guarantee code integrity after soldering thermal profile and data retention in extended temperature range. In particular, extrapolation of data retention at 10 years for temperatures higher than 150^\circC cell level has been demonstrated, thus enabling automotive applications. Despite the tradeoff between the SET speed and RESET data retention, competitive performances with respect to present floating gate memories have been confirmed. Finally, solid data collection based on a 4-Mb test chip integrated in a standard 90-nm CMOS technology platform has been performed. Functionality and performances are well in line with today industrial targets. [ABSTRACT FROM PUBLISHER]

Conduction and switching in the phase-change memory (PCM) strongly depend on the transport mechanisms in the disordered amorphous phase. To predict the programming characteristics and the scaling behavior of PCM, accurate models for transport in the amorphous phase considering the local disorder are essential. This paper presents a numerical model to study the subthreshold conduction in the amorphous state of PCM. The nonhomogeneous active material is described through a potential energy landscape, dictating the local barrier for electron hopping. The model shows strong percolation effects in the amorphous cap of the high resistance state, thus accounting for the observed relationship between the electrical and physical thicknesses of the amorphous cap and for the observed thickness dependence of resistance. The model is finally used to describe the programming characteristics with better accuracy in the transition regime from set to reset, which is critical for multilevel cell applications. [ABSTRACT FROM PUBLISHER]

The programming speed in a phase change memory (PCM) relies on the kinetics of crystallization in the pulsed regime. To predict the programming speed and retention of a PCM, a careful understanding and modeling of crystallization in the phase change material is essential. In this paper, we study crystallization kinetics directly in PCM devices. From thermal annealing and pulsed-set experiments, we extract the temperature dependence of the crystallization in a wide temperature range between 170^\circC and the melting point (about 620^\circC). Our results indicate two markedly different activation energies below/above 300^\circC, thus providing evidence for a non-Arrhenius crystallization kinetics in PCM. [ABSTRACT FROM PUBLISHER]

The potential of rupture-oxide mushroom phase-change memory cells is assessed through 2-D finite element analysis using electro-thermal models with temperature-dependent material parameters, coupled with a circuit model for access transistors. The mushroom cell structure used for the simulations consists of a 100-nm thick Ge2Sb2Te5 layer separated from a 20-nm wide TiN bottom heater by a 3-nm thick SiO2 rupture-oxide layer. The ruptured oxide is modeled as a conductive filament through the oxide layer at the center of the heater. The effects of supply voltage, gate voltage, access transistor width, filament diameter and resistivity are studied using a read/reset/read sequence enabled by a dynamic amorphization model. The simulation results show that rupture-oxide cells can be operated with smaller voltages, currents and transistor widths compared to their conventional counterparts for the same resistance contrast. Moreover, it is shown that the cell performance is further improved for narrower and more resistive filaments. [ABSTRACT FROM AUTHOR]

The electrical resistivity of liquid \Ge2\Sb2 \Te5 (GST) is obtained from dc–voltage measurements performed on thin GST films as well as from device-level microsecond-pulse voltage and current measurements performed on two arrays (thicknesses: 20 \pm 2 nm and 50 \pm 5 nm) of lithographically defined encapsulated GST nano-/microwires (length: 315 to 675 nm; width: 60 to 420 nm) with metal contacts. The thin-film measurements yield \1.26 \pm \0.15\ \m\Omega\cdot\cm (thicknesses: 50, 100, and 200 nm); however, there is significant uncertainty regarding the integrity of the film in liquid state. The device-level measurements utilize the melting of the encapsulated structures by a single voltage pulse while monitoring the current through the wire. The melting is verified by the stabilization of the current during the pulse. The resistivity of liquid GST is extracted as 0.31 \pm 0.04 and \0.21 \pm \0.03\ \m\Omega\cdot\cm from 20- and 50-nm-thick wire arrays. [ABSTRACT FROM AUTHOR]

The amorphous phase of the chalcogenide material in phase-change memory (PCM) devices is sensitive to temperature-activated crystallization and structural relaxation (SR). The latter leads to a change of device/material properties, such as the mobility band gap, the resistance, and the threshold voltage VT for threshold switching. In this paper, we present a VT drift model based on physical descriptions of the electrical transport, the threshold switching, and the SR. We introduce an analytical formula describing the relation between the drift slopes of resistance and VT via the subthreshold slope STS of the I– V curve. A numerical model predicting the time evolution of VT for different programmed states in the PCM multilevel cell is finally presented and compared with experiments. [ABSTRACT FROM PUBLISHER]

This paper investigates the multilevel behavior of phase-change random access memory devices with a dual phase-change material (PCM) stack, i.e., two PCMs stacked on one another. The dual PCM stack comprises of a \Ge2\Sb2\Te5 (GST) layer and a top PCM layer sandwiching a SiN barrier layer. The top PCM layer was varied in three different splits: \Ag0.5\In0.5\Sb3\Te6 (AIST), \Ge1\Sb4\Te7 (GST147), and nitrogen-doped GST (NGST). Extensive electrical characterization and statistical analysis were performed. The intrinsic properties of AIST, GST147, and NGST were used to explain the differences in electrical performances of the three multilevel device splits. The AIST/SiN/GST device split was found to have had the best electrical performance. The difference in electrical resistivities and thermal conductivities played a major role in the power consumption as well as the resistance values of the three multilevel states in these dual PCM multilevel devices. [ABSTRACT FROM PUBLISHER]

We introduce a novel energy-efficient methodology “2-PCM Synapse” to use phase-change memory (PCM) as synapses in large-scale neuromorphic systems. Our spiking neural network architecture exploits the gradual crystallization behavior of PCM devices for emulating both synaptic potentiation and synaptic depression. Unlike earlier attempts to implement a biological-like spike-timing-dependent plasticity learning rule with PCM, we use a simplified rule where long-term potentiation and long-term depression can both be produced with a single invariant crystallizing pulse. Our architecture is simulated on a special purpose event-based simulator, using a behavioral model for the PCM devices validated with electrical characterization. The system, comprising about 2 million synapses, directly learns from event-based dynamic vision sensors. When tested with real-life data, it is able to extract complex and overlapping temporally correlated features such as car trajectories on a freeway. Complete trajectories can be learned with a detection rate above 90 \%. The synaptic programming power consumption of the system during learning is estimated and could be as low as 100 nW for scaled down PCM technology. Robustness to device variability is also evidenced. [ABSTRACT FROM AUTHOR]

Solid-state memory technology is undergoing a renaissance of new materials and novel device concepts for higher scalability as the mainstream technology, i.e., Flash, is approaching physical limits. Emerging memory technologies, which have unique characteristics not available in Flash, are leading transformations in the design of the memory hierarchy. Phase change memory (PCM) is a promising candidate for the next-generation nonvolatile-memory technology. It has been extensively studied for its electrical properties and material scalability. Yet, questions remain unanswered as to what extent a functional PCM cell can be ultimately scaled to and what properties a PCM cell has at the single-digit nanometer scale. In this paper, we demonstrated a fully functional cross-point PCM cell working close to its ultimate size-scaling limit by using carbon nanotubes (CNTs) as the memory electrode. The utilization of CNT electrode brings the lithography-independent critical dimension down to 1.2 nm and contributes to a large reduction of the reset programming current to 1.4 \mu\A and the programming energy to 210 fJ using a 10 ns reset pulse. Measured electrical characteristics validate the advantage of further device area scaling on reducing the programming current of PCM cells and confirm the potential viability of a highly scaled ultradense PCM array down to the bottom electrode contact area that corresponds to a 1.8 nm node technology. [ABSTRACT FROM AUTHOR]

The variation of switching parameters is one of the major challenges to both the scaling and volume production of metal-oxide-based resistive random-access memories (RRAMs). In this two-part paper, the source of such parameter variation is analyzed by a physics-based simulator, which is equipped with the capability to simulate a large number (\sim1000) of cyclic SET–RESET operations. By comparing the simulation results with experimental data, it is found that the random current fluctuation experimentally observed in the RESET processes is caused by the competition between trap generation and recombination, whereas the variation of the high resistance states and the tail bits are directly correlated to the randomness of the trap dynamics. A combined strategy with a bilayer dielectric material and a write-verification technique is proposed to minimize the resistance variation. We describe the simulation methodology and discuss the dc results in Part I. The corroboration of the model and the device optimization strategy will be discussed in Part II. [ABSTRACT FROM AUTHOR]

In this paper, we analyze the read current shifts that have been observed after the erase operations in phase change memory arrays. Experimental data analyses allow detecting statistical features of the current shifts in terms of their occurrence and magnitude, which are consistent with the physical interpretation attributed to the presence or absence of secondary percolation path in parallel to the main one created during the crystallization process. Based on the statistical characterization, we develop a model for the read current that reproduces the measured read current distributions after erase, during cycling, and for different erase pulse durations. [ABSTRACT FROM AUTHOR]

The operation of a phase-change memory cell is studied, with special regard to programming performance, by means of analytical and TCAD numerical modeling and experimental characterization. Dependence of the reset current on geometrical properties of the heater element is analyzed through the study of heat flux from the heater element to the phase-change material. A simple electrothermal analytical model is implemented, which allows the prediction of the cell reset current value as a function of heater geometrical parameters. Analytical predictions are compared with good agreement to extensive experimental measurements. The effects of power dissipation are studied, showing that cell power efficiency strongly depends on its geometrical properties. [ABSTRACT FROM AUTHOR]

A phase-change (PC) memory model that keeps track of the detailed cooling profile in the RESET process is described in this brief. By physically calculating the final crystal fraction resulting from the thermal dynamic of the PC material during the RESET process, the final resistance of the memory cell can be more accurately determined. The proposed model has been implemented in Verilog-A language and verified by experimental data. [ABSTRACT FROM AUTHOR]