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In this paper, we optimize the stack of a 90-nm CMOS-friendly W\backslashAl2O3\backslashCu conductive-bridging random access memory cell integrated in the one-transistor/one-resistor configuration. We show that the excellent Cu buffering properties of a TiW layer inserted at the Al2O3\backslashCu interface make it possible, on one hand, to ensure cell integrity after back-end-of-line processing at 400^\circC and, on the other, to obtain excellent memory performances. After optimization of the Al2O3 layer thickness, the cell exhibits highly controlled set and reset operations, a large memory window, fast pulse programming (10 ns) at low voltage (<3~V), and low-current (10 \muA), and multilevel operation. Finally, 10^6 cycles of write endurance lifetime with up to a three-decade memory window is demonstrated, and state stability is assessed up to 125^\circC. [ABSTRACT FROM AUTHOR]

This paper presents a physical model for program and retention transients in ferroelectric (FE) and charge hybrid nonvolatile memory. A region-by-region statistical model for domain switching in polycrystalline FEs was incorporated with the tunneling current simulations to predict the memory window (\Delta VTH) evolution during program and retention operations. The simulations validated the two-step program mechanism experimentally observed in such memories: rapid initial domain switching on account of high fields in the FE layer followed by field enhancement in the tunneling dielectric which initiates electron injection into the storage nodes. Further, these simulations were shown to accurately account for individual \Delta VTH from the two additive memory mechanisms at all program times. The depolarization effect was shown to be dominant for \Delta VTH loss at short and moderate retention time scales (<100~s). This model was further used to provide realistic estimates in achieving dual speed program and the corresponding dual mode retention characteristics akin to a DRAM and flash hybrid operation. [ABSTRACT FROM AUTHOR]

Understanding the physical mechanisms for resistance change in metal oxides is a key challenge to assess the scalability of resistive-switching random access memory (RRAM) devices. From this standpoint, the time dependence of filament formation and dissolution in metal oxides can provide a useful insight into the fundamental mechanism of resistive switching. In this paper, we show an experimental study of the time-dependent filament growth and of the voltage dependence of set/reset times in \HfOx-based RRAM devices. The voltage across the device is shown to be regulated at any given time irrespective of the compliance current and the applied voltage, evidencing that voltage is the controlling parameter for the filament formation and dissolution during switching. These results are explained in terms of a thermally-activated ion migration model for filamentary switching. The model allows for an analytical calculation of the scaling dependence of set/reset times and energies in RRAM. [ABSTRACT FROM AUTHOR]

In this brief, for the first time, an Euler–Lagrange equation oriented solution for minimizing the operation energy of state-of-the-art spin-transfer-torque magnetoresistance random access memory (STT-MRAM) is proposed. Utilizing the derived analytical solvable Landau–Lifshitz–Gilbert (LLG) model and Euler–Lagrange equation, a calculable method for minimizing the dynamic energy of STT-MRAM is founded. Experimentally, a write energy reduction by 30% is demonstrated in the context of a certain write error rate. This brief provides a pragmatic method for achieving high energy-efficiency and reliable STT-MRAM operations. [ABSTRACT FROM AUTHOR]

Endurance reliability at the array level of resistive random access memories (RRAMs) is addressed. Both oxide based RAM and conductive bridge RAM stacks are extensively characterized, presenting various measurements over resistive layers, memory stacks, and programming conditions. These measurement results allow to extract the maximum number of cycles before breakdown $\text {N}_{c\,\text {max}}$. It is found that this quantity follows a log-normal law. According to this first significant result, the impact of SET and RESET conditions on $\text {N}_{c\,\text {max}}$ statistics is studied. Using tailored ramp voltage stress (RVS) measurements, the minimum RRAM switching voltage is extracted along the endurance cycles and then correlated with the memory degradation. To explain and better understand all these experimental results, a stochastic model based on defect generation in a constriction zone of the resistive layer during cycling is proposed. After exploration of the size, geometry, and shape of such constriction zone, as well as different probability laws governing breakdown, modeled $\text {N}_{c\,\text {max}}$ distributions fitting the experimental ones are successfully generated and deeper explanations about the origin of the maximum number of cycles variability are inferred. [ABSTRACT FROM AUTHOR]

3-D numerical technology computer-aided design simulations, based on experimental results, are performed to study the origin of the large Z2-FET dynamic random access memory (DRAM) memory cell-to-cell variability on fully depleted silicon-on-insulator (FD-SOI) technology. The body width, cross section shape, and the passivation-induced lateral and top interface state density impacts on the device dynamic memory operation are investigated. The width and body shape arise as marginal metrics not strongly inducing fluctuations in the device triggering conditions. However, the interface state (${D}_{\text {it}}$) control, especially at the top of the ungated section, emerges as the main challenge since traps significantly increase the ON-voltage variability threatening the capacitor-less DRAM operation. [ABSTRACT FROM AUTHOR]

We propose SRAMs and DRAM with independent read–write paths employing phase transition material (PTM) in the read port to enable a more compact design compared to standardmultiport cells. Our technique employs 1) the orders of magnitude difference in the resistances of the insulating and metallic phases of the PTM and 2) regulated phase transitions to design a 7T single-ended SRAM, an 8T differential SRAM, and a 2T DRAM. Compared to previously proposed 8T SRAM, our 7T design achieves 9.1% less cell area and our 8T design achieves differential read without area penalty. We extensively analyze the material requirements for PTM to enable the proposed cell operation. We show that the read performance of the proposed 7T cell is only 5% worse than previously proposed standard 8T, while the proposed 8T design shows a 38% improvement. Similarly, our 2TDRAM cell achieves 20% less cell area than 3T DRAM, with less than 6% read time penalty. The benefits for all the designs come at no write overheads. [ABSTRACT FROM AUTHOR]

Resistive switching memory (RRAM) devices generally rely on the formation/dissolution of conductive filaments through insulating materials, such as metal oxides and chalcogenide glasses. Understanding the mechanisms for filament formation and disruption in resistive switching materials is a critical step toward the development of reliable and controllable RRAM for future-generation storage. In particular, the capability to control the filament resistance and the reset current through the compliance current during filament formation may provide a key signature to clarify the switching mechanism. This paper provides a physically based explanation for the universal resistance switching in bipolar RRAM devices. A numerical model of filament growth based on thermally activated ion migration accounts for the resistance switching characteristics. The same physical picture is extended to numerically model the reset transition. The impact of migration parameters and experimental setup on the set/reset characteristics is discussed through numerical simulations. [ABSTRACT FROM AUTHOR]

In this paper, we present tri-mode independent-gate (IG) FinFETs for dynamic voltage/frequency scalable 6T SRAMs. The proposed design exploits the fact that the spacer patterning technology, used for FinFET fabrication, offers the same device footprint for two- and one-fin transistors. The access transistor is designed for operation in three on-state modes achieving simultaneous increase in the read stability and write-ability and enabling appropriate tradeoffs between read stability and access time depending on the frequency requirements. The proposed design achieves 40%–48% higher weak-write test voltage and 2%–34% lower cell write time across a range of voltages compared with a conventional FinFET-based 6T SRAM under iso-leakage. During the read operation at high workload conditions (VDD = \0.7\ \V), 8% improvement in read static noise margin (SNM) is achieved with only 7% access time penalty. During the read operation at low workload conditions, 54%–75% improvement in the read SNM enables low voltage operation under process variations. The proposed IG FinFET SRAM achieves 125–136 mV lower VMIN across different global process corners at the cost of 15-mV higher retention VMIN. Iso-leakage comparison of the proposed technique with the previously proposed IG FinFET 6T SRAM is also performed. An increase in the cell area by 35% is observed compared to the minimum-sized conventional FinFET SRAM. However, there is no cell area penalty compared to the previously proposed IG FinFET SRAM. [ABSTRACT FROM PUBLISHER]

This paper introduces a novel structure for filamentary-conduction-type resistance change memory. The new structure utilizes the fringing field from the top metal electrode to effectively confine the position of the filaments in the cell. Nanoscale (100–50 nm) memory cells are fabricated using nickel oxide (NiO) thin film as the resistance-switching layer to demonstrate the feasibility and functionality of the new structure. The fabricated nanoscale memory cells achieved low reset current (100–200 \mu\A), narrower distribution in low-resistance states, and higher on/off ratio than those of the standard structure. In addition, good scalability down to 50 nm was demonstrated. [ABSTRACT FROM AUTHOR]

In this paper, the application of an asymmetric independent-gate MOSFET (IG-MOSFET) to the bit-cell structures of the SRAM schemes that were previously proposed using the symmetric IG-MOSFET is analyzed. In addition, a novel SRAM scheme with the asymmetric IG-MOSFET is proposed to improve read stability and writeability by controlling the back gates of pass-gate and pull-up transistors. New array architecture is also suggested to prevent read stability degradation in the half-selected cell, where word line is selected but bit line is unselected. The previous SRAMs with IG-MOSFET (IG-SRAMs) fail to simultaneously improve read stability and writeability compared to the SRAM with the tied-gate MOSFET. The proposed IG-SRAM significantly improves both read stability and writeability at the cost of slightly increased bit-cell area and read delay, as compared to the previous IG-SRAMs. [ABSTRACT FROM PUBLISHER]

Moore's law technology scaling has improved performance by five orders of magnitude in the last four decades. As advanced technologies continue the pursuit of Moore's law, a variety of challenges will need to be overcome. One of these challenges is the management of process variation. This paper discusses the importance of process variation in modern transistor technology, reviews front-end variation sources, presents device and circuit variation measurement techniques, including circuit and memory data from the 32-nm node, and compares recent intrinsic transistor variation performance from the literature. [ABSTRACT FROM PUBLISHER]

Introducing a threshold switching selector in a resistive random access memory (RRAM) is essential for implementing a crossbar array that accurately accelerates neuromorphic computations. But, at an expense, a read voltage (${V}_{\text {read}}$) to be used for inference tasks is inevitably boosted. Therefore, this brief shows the effect of the enlarged ${V}_{\text {read}}$ on the stability of conductance states of the RRAM relevant to the inference robustness. The multiple conductance states of the analog RRAM achieved by a SPICE simulation are stable under consecutive 106 cycles of nominal ${V}_{\text {read}}$. However, each state of the one selector and one RRAM begins to be disturbed at ~104 cycles due to the boosted ${V}_{\text {read}}$. More importantly, when a certain state exceeds to the next state due to the accumulated ${V}_{\text {read}}$ stress, a classification accuracy of the neural network is significantly degraded. We, thus, introduce a two-step read scheme that separates the roles of turning on the selector and reading the states. As the selector is turned on rapidly with an additional large pulse, the following ${V}_{\text {read}}$ can be lowered. As a result, the read disturbance is minimized, and the optimized two-step pulse scheme allows 106 MNIST images to be recognized with >95% accuracy in the neural network. [ABSTRACT FROM AUTHOR]

In the development of dynamic random access memory (DRAM) with a device size of 20 nm or less, the leakage current of a capacitor with high-k dielectrics is one of the main factors causing the failure of a device. To reduce the failure rate of the device, we conducted experiments to reduce the boron impurities, which form defect sites in the dielectrics of the capacitor. The boron source flux was reduced during the deposition process of the capping layer after the formation of the capacitor, and the actual boron concentration in the capping layer was measured by an atom probe tomography. The leakage current characteristics of the samples were confirmed through the dielectric leakage failure test, which is a mass production test technique. In addition, the resistance failure test was performed to measure the risk of increased resistance. From these results, it was confirmed that the failure rate due to the leakage current of the capacitor decreased linearly with reduced boron concentration and the increase in failure rate due to the cell node resistance was negligible. In addition, the results show that the failure rate of mass-produced DRAM products can be significantly reduced without any change in the structure or materials of the capacitor. This is expected to contribute greatly to the development of DRAM with dimensions on the scale of 20 nm or less. [ABSTRACT FROM AUTHOR]

An electric molecular dynamics (MD) method is proposed, where an electroheat solver is introduced into a traditional MD simulation to perform a coupled calculation. The switching mechanism of carbon-based resistive random access memory is studied through this method, and the heat generation and propagation driven by an electric current pulse are simulated during the switching process. Graphitic filament breakage and growth are responsible for resistance switching. The simulation shows that a short and strong voltage pulse induces graphitic filament breakage, resulting in a high-resistance state, whereas a moderate but much longer pulse is required to enable filament growth, resulting in a low-resistance state. Key factors such as the bias condition and the power supply for such switching process are also studied. The results are quantitatively consistent with experimental measurements. [ABSTRACT FROM AUTHOR]

This paper presents a new class of charge-trap Flash memory device with resistive switching mechanisms. We propose a fused memory scheme using a structure of metal/\Pr0.7 \Ca0.3\MnO3 (PCMO)/nitride/oxide/silicon to graft fast-switching features of resistive random access memory onto high-density silicon/oxide/nitride/oxide/silicon memory structures. In this scheme, both program and erase (P/E) are performed by the conduction of the carriers that are injected from the gate into the nitride layer through the PCMO, which is a resistive switching material; the resistance state determines whether a program or erase function is performed. In the proposed memory devices, we observed improved memory characteristics, including the current–voltage hysteresis having a resistive ratio exceeding three orders of magnitude at a set voltage of \pm4.5 V, a memory window of 2.3 V, a P/E speed of 100 ns/1 ms, data retention of ten years, and endurance of \10^5 P/E cycles. This approach will offer critical clues about how one can best implement universal features of nonvolatile memories in a single chip. [ABSTRACT FROM PUBLISHER]

The effects of vanadium doping on resistive switching (RS) characteristics and mechanisms of RF-sputtered SrZrO3 (SZO)-based thin films are investigated in this paper. The physical and electrical properties of SZO-based thin films are modulated by vanadium doping due to the Zr4+ ion replaced by V5+, further affecting the RS parameters of SZO-based thin films. The conduction mechanisms of SZO-based thin films are dominated by ohmic conduction (hoping conduction) and Frenkel--Poole emission for the low resistance state (LRS) and the high resistance state (HRS), respectively. The turn-on process might be attributed to the formation of conducting filaments consisting of oxygen vacancies with the effective barrier height (φB,eff) in the range of 0.10-0.13 eV, whereas the turn-off process might result from thermally assisted oxidation of oxygen vacancies by the Joule heating effect. Furthermore, the introduction of the high valence cation (V5+) in a Zr4+ site of SZO crystalline structure can suppress the formation of oxygen vacancies due to the charge neutrality restriction. Such suppression leads to the changes in the forming voltage, turn-on voltage, HRS resistance, dielectric constant, and φB,eff with vanadium doping concentration up to 0.2 mol%, which is within the solid solubility limit based on our measured lattice constants and Vegard's law. [ABSTRACT FROM AUTHOR]

In this paper, we study the operation mode and the scalability of the second generation (type II) of double--gate capacitorless one transistor dynamic random access memory (1T-DRAM) cells. We find that the memory operates by accumulating charge at the gate interfaces, not in the body of the cell. The type-II configuration allows an infinitely long retention of state "1," whereas the total retention time is limited by the leakage associated with state "0" due to band-to-band tunneling (BTBT) at the source/drain to bulk junctions. Extensive and careful scaling analysis shows that longitudinal scaling is limited by short-channel effects related to source/drain to bulk barrier lowering, whereas transverse scaling is limited by BTBT. We conclude that type-II 1T-DRAM is somewhat more scalable than type-I 1T-DRAM (i.e., 15 nm versus 25 nm). The better scaling perspective of type-II 1T-DRAM cells is ascribed to the higher READ sensitivity, programming window, and retention time. [ABSTRACT FROM AUTHOR]

This paper investigates how gate height (Hg), which refers to the size of a floating-body, affects the program efficiency and retention characteristics of one-transistor DRAM (1T-DRAM) and nonvolatile memory (NVM) for a FinFET SONOS device that has a partially depleted silicon-on-insulator (PDSOI) region as a charge storage node for a 1T-DRAM operation. A device with a lower Hg yields enhanced program efficiency due to the higher impact ionization rate caused by the enlarged PDSOI region for both 1T-DRAM and NVM operations. The device with the lower Hg shows slightly poor retention characteristics in the NVM unlike the 1T-DRAM. [ABSTRACT FROM AUTHOR]

This paper addresses the numerical modeling of re- set programming in NiO-based resistive-switching memory. In our model, we simulate electrical conduction and heating in the conductive filament (CF), which controls the resistance of the low resistive (or set) state, accounting for CF thermal-activated dissolution. Employing CF electrical and thermal parameters, which were previously characterized on our NiO-based samples, our calculations are shown to match experimental reset and retention characteristics. Simulations show that reset transition is self-accelerated as a consequence of a positive feedback between the thermal dissolution of the CF and local Joule heating in the CF bottleneck, which can account for the abrupt resistance transition. in experimental data. Finally, the model is used to investigate the reduction of the reset current, which is needed for device application. [ABSTRACT FROM AUTHOR]

This paper presents a new physics-based statistical model for random telegraph noise in Flash memories. From the probabilistic superposition of elementary Markov processes describing the trapping/detrapping events taking place in the cell tunnel oxide, the model can explain the main features of the random telegraph noise threshold-voltage instability. The results on the statistical distribution of the threshold-voltage difference between two subsequent read accesses show good agreement between measurements and model predictions, even considering the time drift of the distribution tails. Moreover, the model gives a detailed spectroscopic analysis of the oxide defects responsible for the random telegraph noise, allowing a spatial and energetic localization of the traps involved in the threshold-voltage instability process. [ABSTRACT FROM AUTHOR]

In this paper, we develop a detailed physical model to interpret the dependence of the stress induced leakage current (SILC) distributions on the nature and position of the generated defects, and we exploit it to reconsider in detail previously published experimental data on the statistical distribution of the SILC in Flash arrays. We found that a unique symmetrical spatial distribution of traps, which is rapidly decreasing from the Si-SiO2 interfaces toward the center of the oxide, can explain the oxide-thickness and stress-level dependence of the measured SILC distributions. The generation of cooperating defects with increasing stress time is also analyzed and discussed. [ABSTRACT FROM AUTHOR]

With technology scaling, there is a strong demand for smaller cell size, higher speed, and lower power in SRAMs. In addition, there are severe constraints for reliable read-and-write operations in the presence of increasing random variations that significantly degrade the noise margin. To understand these trade-offs clearly and find a power-delay optimal solution for scaled SRAM, sequential quadratic programming is applied for optimizing 6-T SRAM for the first time. We use analytical device models for transistor currents and formulate all the cell-operation requirements as constraints in an optimization problem. Our results suggest that, for optimal SRAM cell design, neither the supply voltage (Vdd) nor the gate length (Lg) scales, due to the need for an adequate noise margin amid leakage and threshold variability and relatively low dynamic activity of SRAM. This is true even with technology scaling. The cell area continues to scale despite the nonscaling gate length (Lg) with only a 7% area overhead at the 22-nm technology node as compared to simple scaling, at which point a 3-D structure is needed to continue the area-scaling trend. We also find that the suppression of gate leakage helps to reduce the power in ultralow-power SRAM, where subthreshold leakage is minimized at the cost of increase in cell area. [ABSTRACT FROM AUTHOR]

This paper presents a compact and accurate analytical model for evaluating the programming behaviors of the drain-coupling source-side injection (SSI) split-gate Flash memory. Starting with the bias-dependent and time-varying drain coupling ratio, a programming model is developed on the basis of the constant barrier height approximation and Lucky-electron model to express the full transient injection current, peak lateral electric field, and storage charge as functions of technological, physical, and electrical parameters. The extracted re-direction mean-free path of the SSI device is smaller than that of the channel hot-electron counterpart by one order of magnitude, which provides the physical intuition for the derived high injection efficiency of around 2/1000. The intrinsic coupling ratio depends only on technological parameters and is presented as the design index of the device. The usefulness of this model is its ability of constructing the complete operation plot of the time-to-program versus the programming voltage for various reliability windows and tunable technological parameters. Besides, the variance of the read current distribution of a memory array is also analytically predicted. [ABSTRACT FROM AUTHOR]

In this paper, the short-channel effect in ultrathin body (UTB) SOI Flash memory cell induced by the floating-gate is investigated by a newly developed two-dimensional analytical model. A concept of effective natural length (&lamda;eff) is introduced as a measure of the impact of the floating-gate on the scaling limit. Even though scaling the channel thickness can significantly reduce SCE in UTB MOSFETs, it becomes less effective in floating-gate device due to the floating polysilicon induced gate coupling. To minimize the floating-gate induced SCEs, the drain to floating-gate coupling has to be minimized. [ABSTRACT FROM AUTHOR]

This paper presents a gain-cell solution in which a novel ultrathin polysilicon . film transistor provides the basis for dense and low-power, embedded random-access memory (RAM). This is made possible by the new transistor's 2-nm-thick channel, which realizes a quantum-confinement effect that produces a low leakage current value of only 10-19 A at room temperature. The memory has the potential to solve the power and stability problems that static RAM (SRAM) is going to face in the very near future. [ABSTRACT FROM AUTHOR]

In this paper, through the use of a recently proposed statistical model of stress-induced leakage current, we will investigate the reliability of actual Flash memory technologies and predict future trends. We investigate either program disturbs (namely gate and drain disturbs) and data retention of state-of-the-art Flash memory cells and use this model to correlate the induced threshold voltage shift to the typical outputs coming from oxide characterization, that are density, cross section, and energy level of defects. Physical mechanisms inducing the largest threshold voltage (VT) degradation will be identified and explained. Furthermore, we predict the effects of tunnel oxide scaling on flash memory data retention, giving a rule of thumb to scale the tunnel oxide while maintaining the same retention requirements. [ABSTRACT FROM AUTHOR]

Presents a study which described a dynamic random-access memory technology which provides a cost-effective means of delivering high bandwidth, low power consumption, noise immunity and a small print chip. Integration technology; Results and discussion.

Discusses two aspects which have to be included in the storage time analysis of the article `A Numerical Analysis of the Storage Times of Dynamic Random-Access Memory Cells Incorporating Ultrathin Dielectrics.' Estimation of the diffusion current's value; Schematic measurement configuration of the junction leakage current at the memory node.

It is shown that replacing a TiN effective work function metal by TaN results in a pronounced reduction of the low-frequency noise power spectral density (PSD) of thick-SiO2 input/output (I/O) DRAM peripheral pMOSFETs. The 1/ $f$ noise is originating from carrier number fluctuations, suggesting that the observed reduction results from a decrease of the oxide trap density in the SiO2. On the other hand, I/O pMOSFETs with a TiN gate deposited by different methods or used as a sacrificial gate in a gate replacement integration scheme yield a similar high 1/ $f$ noise PSD and corresponding oxide trap density. [ABSTRACT FROM AUTHOR]

Recently, new dynamic random-access memory (DRAM) structures have been used to sharply reduce chip size. One of these is vertical-cell DRAM that has the advantage of reducing the chip area by 33% compared with the conventional cell DRAM. However, since the bitline is made in Si trenches, it can cause a floating-body effect, which increases the OFF current. Here, we suggest the buried body engineering method as a simple way to deal with these disadvantages without changing the materials. This method significantly improved the electrical performance in comparison with the conventional buried contact. Especially, the OFF current, which is the most important factor influencing the refresh time, was dramatically reduced by a factor of 63. The reason for this dramatic decrease in the OFF current is that the holes accumulated in the body are removed immediately, and they do not generate a parasitic bipolar junction transistor (BJT) action. We also calculated the hole density using simulations and obtained the junction depth that suppresses the floating-body effect. Above all, we provide advanced insight into the mechanism of the parasitic BJT action due to the floating-body effect that occurs at the bottom contact region of vertical-cell DRAM. [ABSTRACT FROM AUTHOR]

To combat the large variability problem in resistive random access memory, current compliance elements are commonly used to limit the in-rush current during the forming operation. Regardless of the compliance element (1R-1R or 1T-1R), some degree of current overshoot is unavoidable. The peak value of the overshoot current is often used as a predictive metric of the filament characteristics and is linked to the parasitic capacitance of the test structure. The reported detrimental effects of higher parasitic capacitance seem to support this concept. However, this understanding is inconsistent with the recent successes of compliance-free ultrashort pulse forming which guarantees a maximum peak overshoot current. We use detailed circuit analysis and experimental measurements of 1R-1R and 1T-1R structures to show that the peak overshoot is independent of the parasitic capacitance while the overshoot duration is strongly dependent on the parasitic capacitance. Forming control can be achieved, in ultrashort pulse forming, since the overshoot duration is always less than the applied pulse duration. The demonstrated success of ultrashort pulse forming becomes easier to reconcile after identifying the importance of overshoot duration. [ABSTRACT FROM AUTHOR]

2-D numerical simulations are used to demonstrate the Z2-FET as a competitive embedded capacitor-less dynamic random access memory cell for low-power applications. Experimental results in 28-nm fully depleted-silicon on insulator technology are used to validate the simulations prior to downscaling tests. Default scaling, without any structure optimization, and enhanced scaling scenarios are considered before comparing the bit cell area consumption and integration density with other eDRAM cells in the literature. [ABSTRACT FROM AUTHOR]

Intrinsic properties of magnetic tunnel junctions (MTJs) are exploited for low-power security electronics. The combination of: 1) fast and nonvolatile storage; 2) stochastic nature of subcritical switching; and 3) random variation in the magnetic anisotropy of MTJ make MRAM array ideal for implementing physically unclonable function (PUF). We develop two bit-pattern randomization procedures, one of which can be exercised at wafer level in process line, while the other can be completed in the in-line tester. The procedures generate unpredictable and unclonable bit patterns in a spin-transfer torque (STT)-MRAM array and store them securely in the array. We show the resistance of MTJ is stable through rounds of thermal baking, the readback from the PUF shows no ambiguity from 25 °C to 75 °C. A single embedded STT-MRAM PUF can cover many needs of security electronics. [ABSTRACT FROM PUBLISHER]

The Z2-FET operation as capacitorless DRAM is analyzed using advanced 2-D TCAD simulations for IoT applications. The simulated architecture is built based on actual 28-nm fully depleted silicon-on-insulator devices. It is found that the triggering mechanism is dominated by the front-gate bias and the carrier's diffusion length. As in other FB-DRAMs, the memory window is defined by the ON voltage shift with the stored body charge. However, the Z2-FET's memory state is not exclusively defined by the inner charge but also by the reading conditions. [ABSTRACT FROM AUTHOR]

Discusses the development of an experimental performance 16 Mb Dynamic Random Access memory (DRAM) having a design rule for gigabit DRAM. Why the local oxidations of silicon (LOCOS) is no longer useful; How to realize a fast data access time even at low operation voltage; Problems of back-end metallization processes.

We study the heat transport in filamentary resistive random access memory nanosized devices by comparing the accurate results of COMSOL Multiphysics modeling with simplified analytical models for two complementary mechanisms: one neglecting the radial heat transfer from the filament to the insulating host, while the other describing the radial transport through the dielectric in the absence of the filament heat transfer. For the former, we find that the earlier assumed simplification of the electrodes being ideal heat conductors is insufficient; a more adequate approximation is derived where the heat transport is determined by the adjacent proximities of the filament tips in the electrodes. We find that both complementary mechanisms overestimate the maximum temperature yet offering acceptable results. However, the two in parallel provide a better analytical approximation. In addition, we show that the Wiedemann–Franz–Lorenz law helps the analysis when the Lorenz parameter is chosen from the actual data. We present an approximate relation between device SET voltage and SET temperature possessing a high degree of universality and predicting that filament materials with low Lorenz numbers can be good candidates for the future low set voltage devices. [ABSTRACT FROM PUBLISHER]

A new impurity mobility model suitable for the TCAD simulation of the random discrete dopant (RDD) has been proposed. The proposed model has been applied to the DRAM cell transistor of the 20-nm technology generation. The RDD effect in the drain region of the cell transistor alone gives relative standard variation in the driving current of ~3%. [ABSTRACT FROM PUBLISHER]

Complementary resistive switches (CRS) based on back-to-back nanofilamentary resistive RAM devices have been fabricated by an all-solution-processed method, employing inkjet-printed Ag and Au contacts and a spin-coated sol–gel zirconium oxide dielectric layer. The devices demonstrate electrical switching behavior below 3 V, stable on-state windows, reasonable cycle lifetimes, and can be implemented in $2\times 2$ memory arrays with no crosstalk during addressing. For reliable operation and high yields of the CRS devices, printing and annealing processes were carefully optimized to eliminate the coffeering effect on the bottom electrode, and produce a pin-hole free dielectric. The arrays are fully pulse programmable and are able to retain their state for > 10^{4} s. Additionally, the arrays can be operated as associative or content addressable, memory for pattern matching applications, which is demonstrated through a basic hamming distance mapping measurement for different stored data states. [ABSTRACT FROM PUBLISHER]

The impact of the dielectric thickness, forming polarity, and current compliance on the self-rectifying current–voltage ( I – V ) characteristics of Ni/HfO2/n+-Si resistive random access memory (RRAM) devices was investigated. The obtained results indicate that these three aspects not only play a role in the postforming currents but also affect the switching properties of the devices. In the case of 5-nm-thick oxide devices, a self-rectifying ratio of about three orders or magnitude is observed after substrate injection forming (SIF) with current compliance below 500 $\mu$ A. However, similar devices subjected to gate injection forming (GIF) do not exhibit such rectifying feature. This distinctive behavior for SIF is ascribed to the formation of a Schottky-like contact in between the Ni-based conducting filament and the semiconductor electrode. For 20-nm-thick oxide devices, the forming voltage under GIF and the subsequent dielectric degradation are higher than for thinner oxide layers, resulting in a less resistive state, and a negligible role of the referred Schottky barrier. The effect of the temperature on the diffusion of the Ni ions that form the conducting path is also discussed. [ABSTRACT FROM PUBLISHER]

A set/reset switching model of Cu atom switch based on electrolysis is newly proposed. A nanometer-thick solid electrolyte gives a high electric field of ~3.3 MV/cm in the solid electrolyte at 2 V, enabling an ionization of Cu and a formation of Cu bridge. It is revealed that the switching voltage depends on the resistance of electrolyte, where the modified Faraday’s law of electrolysis with exponential factors on current and time well falls on the experimental on-resistance. The proposed simple compact model is useful for estimating the resistance of the Cu atom switch programmed by any conditions. [ABSTRACT FROM PUBLISHER]

A low-power 2-Mb Resistance random access memory (ReRAM) macro is developed in a 90-nm CMOS platform with a 3-nm-thick TaOx/Ta2O5 switching layer of the active area of 0.01~\mu \textm^2 . Instability of the ON-state minority bits degrades the high-temperature retention lifetime. The oxygen vacancies in the filament are annihilated by oxygen ions, which have been generated mainly by the OFF-write bias repeated in the ON/OFF switching cyclesbefore the retention. This instability is improved by decreasing the oxygen concentration near Ru bottom electrode as well as lowering the OFF-write bias. Instability of the OFF-state minority bits narrows the memory window by random telegraph noise (RTN). Setting a statistically derived guard band with a pulse-modulated verify sequence is able to handle RTN to ensure the memory window. The 2-Mb ReRAMmacro with 1-b error-correcting code is confirmed to ensure ten years’ retention from −40 °C to 85 °C after 1E3 ON/OFF cycles. [ABSTRACT FROM PUBLISHER]

The adoption of spin-transfer torque random access memory (STT-RAM) into nonvolatile memory systems faces three major obstacles: high write energy, low sensing margin, and high read disturbance. Many designs have been suggested to resolve each of these challenges separately and at the cost of significant overhead. We propose a single low-overhead solution to all these problems without changing the underlying memory architecture by using negative differential resistance devices like tunnel diodes or tunnel field-effect transistors to assist the STT-RAM write and read process. We show through simulations that the proposed designs can dramatically improve the write and read energy efficiency and sensing margins while minimizing the read disturbance, even after accounting for process variations. Our results open a design path for energy-efficient and reliable STT-RAM technologies. [ABSTRACT FROM PUBLISHER]

A high-K/metal gate (HKMG)-stack (TiN/Al-doped-HfOx/SiO2/Si)-based bipolar resistive random access memory (RRAM) cell is proposed and fabricated by 28/20-nm HKMG CMOS compatible technology. Robust reliability behaviors (retention at 200~ ^\circ \text C > 4 \times 10^4 s and endurance $> 10^{{{5^{\vphantom {\frac {}{,}}}}}} cycles) and ultralow switching current ( <0.1\mu \textA for RESET and <0.3\mu \textA for SET) are both demonstrated. The sub- \mu \textA switching current and self-selection nonlinear $I$ – V$ characteristics are attributed to the SiO2 interfacial layer rather than the decrease of conductive filament size and oxygen vacancy ( V_{O} ) density, which can be verified by HRTEM and measured conduction behavior. Therefore, robust reliability property is also achieved. The demonstrated excellent memory characteristics of HKMG stacked RRAM cell enable constituting 1-Mb workable crosspoint array even though the feature size scales down to 10 nm according to the HSPICE simulation. [ABSTRACT FROM AUTHOR]

A new two-transistor logic resistive random-access memory (RRAM) cell with a 16-nm standard FinFET CMOS logic platform that is fully compatible with the CMOS process is proposed and demonstrated in a 1-kb FinFET dielectric RRAM (FIND RRAM) array. The new 16-nm FIND RRAM comprises two logic standard FinFET transistors with a HfO2-based composite resistive gate dielectric film as the storage node in a cell. The set and reset characteristics of the FIND RRAM are largely improved by the locally enhanced field at fin corners, which results in low set voltage and low reset current in array operations. Due to adoption of a FinFET CMOS logic process without any additional masks or processing steps, FIND RRAM can be scaled aggressively with a cell size of 288~\text nm \times 265 nm. Low-voltage operation, excellent reliability, and stable low-resistance state/high-resistance state window are realized with the set and reset procedures based on the incremental step pulse programming algorithm, making FIND RRAM a promising embedded nonvolatile memory in the FinFET era. [ABSTRACT FROM AUTHOR]

We demonstrate nonvolatile and area-efficient ternary content-addressable memories (TCAMs) featuring amorphous indium–gallium–zinc–oxide (a-IGZO) ferroelectric field-effect transistors (FeFETs) with excellent electrical characteristics. An extremely large sensing margin of the TCAM array is achieved due to the large current ON/OFF ratio ($I_{ \mathrm{\scriptscriptstyle ON}}/I_{ \mathrm{\scriptscriptstyle OFF}})$ of the a-IGZO FeFETs. Our HfxZr $_{\text {1-x}}\text{O}$ 2 (HZO)-based a-IGZO FeFETs have a metal–ferroelectric–metal–insulator–semiconductor (MFMIS) structure. By engineering the area ratio of the ferroelectric layer (${A}_{Fe}$) and the metal–oxide–semiconductor layer (${A}_{MOS}$), a large memory window (MW) of 2.9 V is realized. Reliability test results, including retention, endurance, and positive bias temperature instability, show long-term retention of more than ten years and high endurance of 108 cycles. In addition, by scaling the channel length down to 40 nm, ON current of $77 ~\mu \text{A}/ \mu \text{m}$ (${V}_{\mathrm{GS}} - {V}_{\mathrm{TH}}$ = 5 V and ${V}_{\mathrm{DS}}$ = 2 V) and ${I}_{ \mathrm{\scriptscriptstyle ON}} / {I}_{ \mathrm{\scriptscriptstyle OFF}}$ of more than eight orders can be obtained for the ultrascaled a-IGZO FeFETs while maintaining an MW of 2.8 V. [ABSTRACT FROM AUTHOR]

In this work, we developed a nonvolatile ternary content addressable memory (TCAM) with a cell size of $0.01~\mu \text{m}^{{2}}$ utilizing the Ge-based memory diode (MD), which has the most area-efficient TCAM design reported. The MDs have a high current ratio between ON and OFF states and a large rectifying ratio, showing the potential usage in large-dimension TCAM arrays. Besides, the functionality of parallel search was demonstrated with a 2-bit MD-TCAM array by experiment, and the electrical characterization showed expected results. With the help of the sub-ns ultrafast measurement system, it is confirmed that the search energy of MD-TCAM could reach as low as 1.0 fJ/bit/mismatch, and one search operation can be performed within 200 ps. Furthermore, the circuit-level simulation results verified that the MD-TCAM developed in this study shows good performance in 128-bit parallel searching, which is promising for the ultrafast and low-power data search applications in the coming IoT era. [ABSTRACT FROM AUTHOR]

A statistical dependence of set voltage Vset on the preceding reset voltage $V_{{\rm {reset}}} is observed in resistive memory arrays and explained in terms of two interlocking mechanisms. This dependence can be replicated on a single device by intentionally varying the Vreset values by various linear voltage ramp rates. The latter mechanism is well modeled under the assumption that a critical heat deposited locally in the filament triggers the rupture of the filament. Mechanisms are proposed to explain the impact of different ramp rates of the reset operation on the ruptured gap in the filament that affect, in turn, the Vset value of the subsequent set operation. Based on these observations, a one-time tightening procedure is designed, leading to tightened Vset and V{\rm {reset}} distributions. [ABSTRACT FROM AUTHOR]

A static memory cell (SRAM) based on the field-effect diode (FED) is presented, and its operation is explained with the help of numerical device simulations. Although this new cell resembles the thin-capacitively coupled-thyristor (TCCT) SRAM cell in concept and operation, it is nevertheless characterized by significant advantages. These advantages derive from the fact that the thyristorlike mode of operation of the FED is gate induced, whereas the TCCT is an actual built-in thyristor. The operation of the cell is explained with the help of suitable timing diagrams, and the mechanisms of storing 1 and 0 are analyzed with detailed numerical simulations. In one operation scheme (where the cell could better be termed quasi-SRAM), a sequence of restore pulses is periodically applied after the cell is put on Hold, which ensures that the stored data remain valid for as long as the cell is powered ON. High read 0/1 current margin, fast write/read time, and densely packed cells are among the cell advantages obtained. [ABSTRACT FROM AUTHOR]

The operation of a capacitorless (1T) dynamic random access memory (DRAM) can be compromised if the storage region is located near metal–semiconductor junction in a reconfigurable field-effect transistor (RFET). Through subtle modifications, without affecting current drive, capacitance, and reconfigurable features, the present work showcases feasible 1T-DRAM operation in a RFET with an intentionally misaligned polarity gate. Analysis based on device physics and operation, highlights 1T-DRAM for standalone and embedded applications with impressive performance indicators: sense margin $\ge 6~\mu \text{A}/\mu \text{m}$ , retention time ≥16 ms (for embedded), and ≥64 ms (for standalone) at 85 °C, current ratio of ~104 along with a low write (~ 1 ns) and read (~ 2 ns) time. Guidelines in terms of scalability of total length and biases for implementing 1T-DRAM cell are presented. [ABSTRACT FROM AUTHOR]