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Error resilient applications benefit from the use of approximate computing techniques that enhance electrical performances while allowing a deviation from the exact result. Many operations in signal processing require the square of a signal. Despite the fact that the squaring operation can be regarded as a special multiplication case, it is often preferable to develop independent squaring circuits to exploit possible architectural symmetries. This paper proposes novel approximate binary squarers, obtained by recursively exploiting 4-bit approximate multipliers and squarers. The final designs cover a wide range of computing precision, providing the user with multiple choices of different cost vs. accuracy trade-offs. The proposed circuits, as well as competitive designs, are synthesized targeting a 14 nm FinFET technology to determine the electrical characteristics. It is demonstrated that the proposed squarers outperform the state-of-the-art in terms of power vs. precision. Compared to the exact 8-bit squarer, the least dissipative proposed design reduces silicon area by 76%, power consumption by 71%, and critical delay by 72%. The same circuit dissipates 2.4% less power than the least dissipative design found in literature, while providing 34% more accurate results. The behavior of the considered designs is also tested in common error resilient applications, like signal demodulation and image processing. • Approximate computing relaxes hardware cost, improving electrical performances. • Approximate recursive squarers employ small modules to scale up to their final size. • The proposed squarers are obtained by simplifying the exact Boolean expressions. • The proposed squarers outperform the state-of-the-art in terms of power vs precision. [ABSTRACT FROM AUTHOR]

In this paper, two improved structures and a truncation strategy with compensation for complex multiplication are proposed. Simulation in 28-nm CMOS for hardware performance is provided. Compared to the general complex multiplier, the two accurately improved structures realize 18.58% and 20.80% power consumption reduction, respectively. The truncation strategy with compensation reduces power consumption by 46.8% and controls Mean Relative Error Distance (MRED) at 0.54%. To verify the practicability of the proposed architecture, our designs are applied to the Fast Fourier Transform (FFT) processor to comprehensively evaluate the error characteristics and circuit performance. • An optimization for the partial product compression in the complex multiplier, reducing four carry propagation additions. • An optimization for subtraction in the process of complex multiplication, reducing the conversion of negative operands. • A truncation compensation strategy for fault-tolerant systems, and we evaluate its hardware benefits in the FFT system. [ABSTRACT FROM AUTHOR]

Energy efficiency has emerged as one of the most essential design parameters in contemporary computing system design. Approximate computing is a new computing paradigm to achieve energy efficiency by trading-off energy/area/latency improvements with accuracy for error-resilient applications. This paper proposes R econfigurable E nergy-efficient A pproximate D ivider (READ) that achieves several energy–quality configurable modes using fixed restoring array divider architecture. Conventional approximate binary dividers require various divider hardware configurations to achieve distinct energy–quality trade-off points, which decreases the hardware flexibility, especially for modern embedded systems. READ accomplishes energy efficiency while meeting the dynamically varying accuracy requirements of the targeted application. READ uses reconfigurable subtractor cells that can work in either accurate or approximate mode using a subtractor cell controller logic. The paper also introduces the design of overflow detector using minimal hardware resources. A comprehensive accuracy and hardware evaluation on CMOS 45-nm technology node are performed for the proposed dividers as well as other state-of-the- art divider designs. Compared to the accurate 16 ∕ 8 divider design, the proposed divider shows an improvement of 49% in terms of energy efficiency and is 1.26x faster, while introducing minimal errors. The proposed divider design is demonstrated for its efficacy in image processing tasks and shows nominal effect on the output quality. • A fixed restoring array based approximate divider is proposed and presented with detailed error and circuit analysis for CMOS-45 nm technology node. • The approximate divider presented is reconfigurable in runtime which enables accuracy configurability by varying the design parameter. • Reconfigurable half and full subtractor cells are designed and proposed which achieves dual mode of operation — accurate and exact with energy savings. • Overflow detector circuit for divider design is proposed and presented which is scalable and hardware efficient. • The approximate divider designs are evaluated for image processing applications and found to be satisfactory in terms of Quality of Services (QoS). [ABSTRACT FROM AUTHOR]

Approximate Computing techniques are finding a central role in modern applications, by optimizing architectures to relax some computation but with a constrained inaccuracy. In many applications, the FFT algorithm is invariably applied and there is a need for approximate low energy hardware solutions to the FFT. The paper thus proposes an approximate, fixed-point, in-place, shared memory architecture for FFT. It is well observed that the energy at FFT I/Os is not strictly contiguous, hence the proposed FFT exploits this window to tune the error. The proposed FFT and its associated butterfly unit is constructed to efficiently incorporate approximate Toom–Cook multiplication. As said, a supporting function in error correction based on the sparsity patterns, is a feature of this design. The design synthesized at 32 n m shows on average, a 48.6% and 52.8% improvement in consumption of area and energy, respectively, with as less error as 0.1% with pruning. • Approximate Computing can exploit error resilience of the applications to reduce chip resources. • FFT is a fundamental block on chip and approximating FFT can accelerate many applications. • The proposed FFT is based on approximate Toom-Cook multiplication that has a reduced number of sub-multiplications. • Pre-computing the evaluations in Toom-Cook multiplication of the twiddle factors in the butterfly provides additional savings. • This design allows a secondary mode of operation in FFT to trade-off sparsity in the FFT outputs with the error in the final FFT sequence. [ABSTRACT FROM AUTHOR]

In this paper, the authors present an investigation into the benefits of approximate computing in energy-efficient error-resilient applications. It proposes an approximate square root (SQR) circuit based on the modified restoring array square root (MRAS) architecture. The MRAS design incorporates strategic elimination, optimization, and simplification of restoring subtractor cells (SC) within a conventional restoring array SQR circuit. As a result, the proposed MRAS circuit efficiently computes the square root of a 2n-bit unsigned integer, offering a 27 percent reduction in area, 13 percent faster computation, and 50 percent lower power consumption compared to the exact SQR design. To introduce approximation, configurable SCs are integrated into the MRAS circuit, enabling dual operation modes for both accuracy and approximation. This feature allows the proposed approximate modified restoring array SQR (AMRAS) design to cater to both error-resilient and error-sensitive applications. The evaluation involves a thorough analysis of accuracy and design metrics for 16-bit unsigned exact, state-of-the-art, and proposed square rooters. The designs are implemented on Artix7 FPGA using Verilog-HDL and simulated in the Xilinx Vivado simulator. The results demonstrate that the proposed AMRAS achieves a good trade-off between accuracy and hardware, presenting an impressive 80 percent reduction in power consumption and a 36 percent faster computation. Additionally, the paper showcases the practical application of the proposed AMRAS square rooters in the Sobel edge detection for image processing. • A new modified restoring array square rooter is presented with 50% power savings. • Configurable subtractor cells are proposed for both accurate and approximate modes. • The proposed approximate square-rooter provides an 80% reduction in power consumption, 36% faster computation, and good energy-accuracy trade-off compared to the state-of-the-art. • An application of the proposed design for edge detector in image processing is also included. [ABSTRACT FROM AUTHOR]

The image processing can be implemented in an error-tolerant mode with acceptable accuracy. In digital image processing, the adders and multipliers are the most important components. In this paper, two approximate multipliers based on an approximate 4:2 compressor and two 4-bit full adders with minimizing computational costs are proposed. The first and second proposed approximate multipliers are designed by using the proposed imprecise 4-bit full adders and 4:2 compressor, respectively. In the structure of the proposed multipliers, we have adders for the addition of two multiple-bit numbers. In the adder structure, the full adders are designed based on two modified half adders and one NAND gate. The proposed approximate 4:2 compressor and two approximate 4-bit full adders are compared from hardware and accuracy point of view such as gate count, area-delay product (ADP), error rate (ER), mean error distance (MED), mean relative error distance (MRED), and normalized error distance (NED). The efficacy of proposed multipliers in image processing applications such as image multiplication is evaluated using MATLAB. The results show the proposed approximate multipliers are comparable in terms of area, delay, and mean structural similarity index metric (MSSIM) parameter with other works. • In this paper, two approximate multipliers based on an approximate 4:2 compressor and two 4-bit full adders with minimizing computational costs are proposed. • The first and second proposed approximate multipliers are designed by using the proposed imprecise 4-bit full adders and a 4:2 compressor, respectively. • In this structure, the full adders are designed based on two modified half adders and one NAND gate. [ABSTRACT FROM AUTHOR]

This paper proposes a configurable reduced worst-case error approximate adder, named BEAD (B ounded E rror A pproximate A d der). The proposed adder is based on segmentation and carry speculation methods to cut long critical paths. Furthermore, a high accuracy speculation method is proposed to calculate the sum bits. However, the data of real-world applications is often not uniformly distributed, which leads to taking values that result in a worst-case error of the approximate adder quite frequently; therefore, considerable distortion occurs at the output. To overcome this, the carry prorogation scheme of the BEAD is such that the error distance is bounded to a given value, which makes it more accurate rather than prior works. Specifically, the BEAD offers a smaller worst-case error in addition to improved mean relative error distance. The results show between 50% and 80% smaller maximum error compared to the related works. Also, by synthesizing the different adders using a 15-nm FinFET technology, the results demonstrate that the BEAD has at least 30% area saving compared to the exact adder in the various studied configurations. The proposed adder achieves the almost lowest figure of cost (FoC) compared to state-of-the-art approximate adders. Moreover, BEAD's evaluation in image processing and DCT applications shows its great superiority over recently proposed structures. • Porposing an approximate adder based on segmentation and carry speculation methods. • Proposing a high precision speculation method to calculate the sum bits. • Bounding the error distance achieving in a smaller worst-case error. • Achieving the lowest figure of cost compared with prior approximate adders. [ABSTRACT FROM AUTHOR]

As the number of transistors on a chip surface increases, power consumption becomes more and more a serious concern. A promising solution to bridge the gap between resource-constrained gadgets and computation-intensive applications could be the approximate computing paradigm. This paper presents four efficient approximate full adder cells based on dynamic logic and carbon nanotube field-effect transistors (CNFETs). To the best of our knowledge, dynamic logic has never been deployed in the design of approximate full adders before. Comprehensive simulations and analyses are conducted to study the efficacy of the new circuits. Simulation results indicate remarkable improvements compared to state-of-the-art circuits. For instance, at 0.9 V power supply, our final proposed design improves the power-delay-area product (PDAP) metric by at least 63% compared to its peers. Moreover, the applicability of the proposed adders in the image sharpening application is examined by measuring peak signal-to-noise ratio (PSNR) and structural similarity index measure (SSIM) using the MATLAB tool. The proposed designs have also a reasonable performance in this regard. • Deploying dynamic logic (DL) in the design of approximate full adders for the first time. • Designing ultra-low area and energy consumption full adder structures. • Applying the proposed adders in the image processing application. [ABSTRACT FROM AUTHOR]

Approximate computing has emerged as an efficient design methodology for improving the performance and power-efficiency of digital systems by allowing a negligible loss in the output accuracy. Dedicated hardware accelerators built using approximate circuits can solve power-performance trade-off in the computationally complex applications like deep learning. This paper proposes an approximate radix-4 Booth multiplier and hardware accelerator for deploying deep learning applications on power-restricted mobile/edge computing devices. The proposed accelerator uses approximate multiplier based parallel processing elements to accelerate the workloads. The proposed accelerator is tested with matrix–vector multiplication (MVM) and matrix–matrix multiplication (MMM) workloads on Zynq ZCU102 evaluation board. The experimental results show that the average power consumption of the proposed accelerator reduces by 34% and 40% for MVM and MMM respectively, as compared to the conventional multiply-accumulate unit that was used in the literature to implement similar workloads. Moreover, the proposed accelerator achieved an average performance of 5 GOP/s and 42.5 GOP/s for MVM and MMM respectively at 275 MHz, which are 14 × and 5 × respective improvements over the conventional design. • Low power and high speed approximate radix-4 Booth multiplier. • Approximate hardware accelerator for edge computing applications. • Simultaneous transfer of data from the on-chip memory to off-chip memory using multiple interconnects. • Packing of data for improving data communication bandwidth. [ABSTRACT FROM AUTHOR]

Recently, emerging "edge computing" moves data and services from the cloud to nearby edge servers to achieve short latency and wide bandwidth, and solve privacy concerns. However, edge servers, often embedded with GPU processors, highly demand a solution for power-efficient neural network (NN) training due to the limitation of power and size. Besides, according to the nature of the broad dynamic range of gradient values computed in NN training, floating-point representation is more suitable. This paper proposes to adopt a logarithm-approximate multiplier (LAM) for multiply-accumulate (MAC) computation in neural network (NN) training engines, where LAM approximates a floating-point multiplication as a fixed-point addition, resulting in smaller delay, fewer gates, and lower power consumption. We demonstrate the efficiency of LAM in two platforms, which are dedicated NN training hardware, and open-source GPU design. Compared to the NN training applying the exact multiplier, our implementation of the NN training engine for a 2-D classification dataset achieves 10% speed-up and 2.3X efficiency improvement in power and area, respectively. LAM is also highly compatible with conventional bit-width scaling (BWS). When BWS is applied with LAM in five test datasets, the implemented training engines achieve more than 4.9X power efficiency improvement, with at most 1% accuracy degradation, where 2.2X improvement originates from LAM. Also, the advantage of LAM can be exploited in processors. A GPU design embedded with LAM executing an NN-training workload, which is implemented in an FPGA, presents 1.32X power efficiency improvement, and the improvement reaches 1.54X with LAM + BWS. Finally, LAM-based training in deeper NN is evaluated. Up to 4-hidden layer NN, LAM-based training achieves highly comparable accuracy as that of the accurate multiplier, even with aggressive BWS. • Edge computing and wide-dynamic range instinct of gradients facilitate the demand for developing power-efficient floating-point (FP) neural network (NN) training. • We present LAM incorporating BWS to significantly reduce primary MAC computation in FP NN training up to 4-hidden layer NN. Besides, solo-LAM training is proved to be sufficiently accurate and there is no need to rely on the exact multiplier for our datasets. • Benchmarking results through our dedicated training hardware show that compared to the exact multiplier, LAM/LAM + BWS can reduce 2.5X/4.9X power while sustaining the accuracy. • We deploy an open-source GPGPU design with a programmable compiler to train LAM and LAM + BWS based NNs, and attain at 1.32X and 1.54X power efficiency through real-time measurement. [ABSTRACT FROM AUTHOR]

Conventional precise adders take long delay and large power consumption to obtain accurate results. Exploiting the error tolerance of some applications such as multimedia, image processing, and machine learning, a number of recent works proposed to design approximate adders that generate inaccurate results occasionally in exchange for reduction in delay and power consumption. However, most of the existing approximate adders have a large relative error. Besides, when applied to 2's complement signed addition, they sometimes generate a wrong sign bit. In this paper, we propose a novel approximate adder that exploits the generate signals for carry speculation. Furthermore, we introduce a low-overhead module to reduce the relative error and a sign correction module to fix the sign error. Compared to the conventional ripple carry adder and carry-lookahead adder, our adder with block size of 4 reduces power-delay product by 66% and 32%, respectively, for a 32-bit addition. Compared to the existing approximate adders, our adder significantly reduces the maximal relative error and ensures correct sign calculation with comparable area, delay, and power consumption. We further tested the performance of our adders with and without the sign error correction module in three real applications, mean filter, edge detection, and k -means clustering. The experimental results demonstrated the importance of reducing the relative error and ensuring the correct sign calculation for 2's complement signed additions. The outputs produced using our adder with the sign error correction module are very close to those produced using accurate adder. [ABSTRACT FROM AUTHOR]