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The role of universal memory can be successfully satisfied by magnetic tunnel junctions (MTJs) where the writing mechanism is based on spin-transfer torque (STT). An improvement in the switching properties (lower switching current density maintaining the thermal stability) has been achieved in MTJs with interfacial perpendicular anisotropy (IPA) at the interface between CoFeB and MgO. In this paper, micromagnetic simulations point out the influence of IPA and saturation magnetization (M \(_{\mathbf {S}}\) ) on the properties of fast magnetization reversal achieved in 5, 10, and 20 ns. Both cases of in-plane and out-of-plane free layer are considered. In addition, the thermal effect is included for the in-plane switching at 20 ns and a complete analysis of energy dissipation during the switching is illustrated. This paper can provide useful information for the design of STT-based memories. [ABSTRACT FROM PUBLISHER]

Distributed energy resources (DERs) are expected to provide ancillary functions including reactive power generation and harmonics compensation. Meanwhile, multilevel inverters and two-level converters with optimal pulsewidth modulation (OPWM) will be commonly used for DERs at high power levels. The challenge is to realize harmonic compensation with limited switching angles. This paper presents an online solution to realize the selective harmonics compensation (SHC), and power generation with DERs. For harmonics compensation, the selective harmonic components in the load current are detected. Then, the harmonic voltages are provided with DERs to cancel out these detected components. Since the power converter is requested to realize both harmonics filtering and power generation, limitations on harmonics compensation at the given power are discussed. Power hardware-in-the-loop-based online verifications are shown at the end of the paper. [ABSTRACT FROM AUTHOR]

Power switching devices based on wide bandgap semiconductor materials, such as silicon carbide (SiC) and gallium nitride (GaN) offer superior performance such as low switching and conduction losses, high voltage, high frequency, and high temperature operation. In this paper, a 600-V GaN switch and a 600-V GaN diode were tested in detail to understand the GaN device capabilities with respect to equivalent silicon-based devices such as IGBT and MOSFET. Detailed experimental loss models are developed and compared with datasheet models. Experimental setup of different power converters such as boost, buck-boost, and half-bridge inverter and associated comparative experimental results are presented. This paper also presents the investigations into the effectiveness of using GaN devices and higher switching frequencies in reducing the total size and cost of power conversion equipment such as an online UPS system. [ABSTRACT FROM AUTHOR]

This paper describes issues related to parallel connection of SiC bipolar junction transistors (BJTs) in discrete packages. The devices are applied in a high-frequency dc/dc boost converter where the switching losses significantly exceed the conduction losses. The design and construction of the converter is discussed with special emphasis on successful parallel-operation of the discrete BJTs. All considerations are experimentally illustrated by a 6-kW, 250-kHz boost converter (300 V/600 V). A special solution for the base-drive unit, based on the dual-source driver concept, is also shown in this paper. The performance of this driver and the current sharing of the BJTs are both presented. The power losses and thermal performance of the parallel-connected transistors have been determined experimentally for different powers and switching frequencies. An efficiency of 98.23% (±0.02%) was measured using a calorimetric setup, while the maximum temperature difference among the four devices is 12 °C. [ABSTRACT FROM AUTHOR]

In this paper, a design method is proposed for finding the equivalent inductance and capacitance of the single-ended primary-inductor converter (SEPIC). The relations of the output voltage ripple (OVR) of the SEPIC converter are obtained in complete inductor supply mode–continuous conduction mode (CISM-CCM), incomplete inductor supply mode-CCM (IISM-CCM), and IISM-discontinuous conduction mode (IISM-DCM). The maximum of OVR (MOVR) is investigated for a specified range of the input voltage and load resistance. This value of the MOVR is obtained for the minimum values of input voltage and load resistance. In this paper, the minimum values of the equivalent inductance and capacitance are calculated in obtaining the minimum value of the MOVR. One of the other performed studies in this paper is calculation of the switch peak current in CCM and DCM. In addition, the converter is designed based on the minimum values of the MOVR and stress of the switching current. Experimental and simulation results are used to prove the validity of the presented theoretical subjects. [ABSTRACT FROM PUBLISHER]

This paper presents a 32 b, 90 nm data flow processor capable of executing arbitrary DSP algorithms using fine grained Dynamic Voltage Scaling (DVS) at the component level with rapid V DD switching and V DD dithering for near-ideal quadratic dynamic energy scaling from 0.25 V–1.2 V. This is the first full processor with Panoptic (all-inclusive) DVS, single clock cycle V DD switching, V DD dithering, and the ability to switch between high performance DVS operation and a sub-threshold mode of operation. This paper also explores V DD header switching and voltage selection considerations for additional savings. Measurements show up to 80% and 43% energy savings of using PDVS over single V DD (SVDD) and multi-V DD (MVDD), respectively. Additionally, PDVS shows area savings of up to 65% over MVDD given the same energy consumption. [ABSTRACT FROM PUBLISHER]

The five-level active neutral-point-clamped (5L-ANPC) converter has been widely studied for its excellent performance in high-power medium-voltage applications. This paper analyzes the space vector pulse width modulation (SVPWM) strategy of the 5L-ANPC converter in the virtual coordinate, and presents an optimized control strategy which can balance the neutral point (NP) voltage and avoid the dead-time effects for the first time. In this strategy, on one hand, the 125 space vectors are combined by 96 triangles in the seven-segment vector synthesis method, then the triangles are divided into seven categories which have different characteristics of balancing the NP voltage, and every category has its own principles to choose the vector sequence and compute the vector durations. On the other hand, the dead-time effects of the 5L-ANPC converter are studied in detail and the transitions between different switching states are constrained in the optimized control strategy to avoid the dead-time effects that cannot be compensated by traditional pulse-based dead-time compensation methods. Finally, the optimized SVPWM strategy is experimentally verified in this paper. [ABSTRACT FROM AUTHOR]

During the switching of disconnectors in gas-insulated switchgear (GIS), repeated strikes occur in the contact gap and lead to very fast transient overvoltage (VFTO). Severe VFTO may bring damage to transformers and other equipment. The switching speed of the disconnector is one of the important factors which influences VFTO. There are still different opinions on this factor. Very little quantitative study was done before this paper. In this paper, the whole repeated strike process associated with the switching operation of the disconnector was simulated and analyzed. The polarity and the probability characteristics of breakdown voltage were analyzed. The impacts of the switching speed of the disconnector on VFTO were studied by statistical methods. Comparisons were made between simulated and measured results. The simulation result shows that within a certain range of speed, disconnectors with a lower switching speed generate lower trapped charge voltage after opening operation and lower VFTO magnitude during the opening and closing operations. [ABSTRACT FROM AUTHOR]

This paper features the projected cross point control (PCPC) approach which is a recent current-mode control (CMC) technique. PCPC benefits from several advantages including fixed switching frequency, wide stability range, high current loop gain, improved audio susceptibility, and simpler design procedure. An introduction of its principles of operation is followed by detailed discussions about its stability and dynamic response. This paper then describes the development of the small-signal model of PCPC and derives transfer functions, such as current loop gain, audio susceptibility, and output impedance. Finally, simulations and experimental results are presented. Peak, average, and hysteresis CMC schemes are used for comparison. [ABSTRACT FROM PUBLISHER]

Multilevel inverters with hexagonal and dodecagonal voltage space vector structures have improved harmonic profile compared to two-level inverters. Further improvement in the quality of the waveform is possible using multilevel octadecagonal (18-sided polygon) voltage space vectors. This paper proposes an inverter circuit topology capable of generating multilevel octadecagonal voltage space vectors, by cascading two asymmetric three-level inverters. By the proper selection of dc-link voltages and the resultant switching states for the inverters, voltage space vectors, whose tips lie on three concentric octadecagons, are obtained. The advantages of octadecagonal voltage space vector-based pulsewidth modulation (PWM) techniques are the complete elimination of fifth, seventh, eleventh, and thirteenth harmonics in phase voltages and the extension of linear modulation range. In this paper, a simple PWM timing calculation method is also proposed. Experimental results have been presented in this paper to validate the proposed concept. [ABSTRACT FROM PUBLISHER]

This paper proposes a soft switching technique for dc/ac inverters, by using duty cycle and frequency modulation. Zero voltage switching (ZVS) is achieved through controlling the inductor current bidirectional in every switching cycle. This technique requires no additional resonant components and can be employed for various low power applications on conventional full-bridge and half-bridge inverter topologies. Three different current mode control schemes are derived from the basic theory of the proposed technique. They are referred to as boundary current mode (BCM), variable hysteresis current mode (VHCM), and constant hysteresis current mode (CHCM) in this paper and their advantages and disadvantages are compared. Simulation and experimental results demonstrate the feasibilities of the proposed soft-switching technique and its control schemes. [ABSTRACT FROM PUBLISHER]

In this paper, a new control strategy for improving weighted efficiency in photovoltaic (PV) ac module-type interleaved flyback inverters (ILFIs) is proposed. The efficiency of the ILFI for PV ac modules has to be high, not only for the maximum power, but also for other power levels according to weather conditions. For PV power conversion efficiency improvement in all load ranges, a new control method for an ILFI according to the output of the PV module is proposed in this paper. The proposed method controls an active clamp circuit and each converter phase of an ILFI according to the output power of the PV module. Thus, the efficiency of an ILFI as a PV power conditioner can be improved in all power range of the PV module. Theoretical analysis, simulation, and experiment are performed in order to verify the proposed control method. [ABSTRACT FROM AUTHOR]

This paper presents the basic features of a software system developed to support the teaching of digital logic, as well as the experience of using it in the Digital Logic course taught at the School of Electrical Engineering, University of Belgrade, Serbia. The system has been used for several years, both by students for self-learning and laboratory work, and by teachers to automate the assessment and verification of students' work. The system allows users to design and simulate a switching circuit. It also collects data on all student activities and transfers these to the school's information system. Finally, the paper gives figures demonstrating the overall benefits of the system. [ABSTRACT FROM AUTHOR]

This paper explores the feasibility of active clamping techniques in isolated time-sharing (TS) multiple-input converters (MICs). Additional losses caused by energy transfer from the leakage inductance in the isolating coupled-inductor into the input switches are addressed with a common active clamping leg for all input legs. An active clamping technique is applied to isolated TS-MIC to minimize the additional switching losses and voltage stresses on input legs. This paper also conducts an operational analysis of an isolated time-sharing dual-input single-ended primary-inductor converter (I-TS-DI-SEPIC) with the discussed active clamping technique. Zero-voltage switching can be achieved on the first-turned-on input leg and the active clamping leg with a proper driving strategy and well-chosen circuit parameter settings. Discussions on the effect of the active clamping technique to an MIC and the components stresses of the I-TS-DI-SEPIC with the active clamping technique have also been made to assist in the design of TS-MICs. Prototypes of the I-TS-DI-SEPIC with the active clamping technique have been built to demonstrate the performance in the application of split-phase dc distribution systems. Converter efficiency and voltage stresses are experimentally verified, showing that the active clamping technique achieves noticeable efficiency gains and component stress reduction. [ABSTRACT FROM AUTHOR]

This paper deals with time domain simulation of common mode (CM) conducted disturbances in power electronics. This study proposes a proof of concept of a fast reconstruction method (FRM), which allows to compute the spectrum of a current based on the knowledge of a single pulse of current (i.e., the knowledge of the disturbances on a small fraction of time) and of the switching instants (i.e., the control strategy of the structure). The first parts of the paper demonstrate the reliability of the method using data measurements of a CM current generated by a PWM half-bridge converter and then by a three phase inverter. The simulation time saved thanks to the FRM is then quantified by comparing the simulation durations with or without using the FRM. In our example, the FRM allows to divide the simulation time by about 10. This analysis points out that the complex information of a CM current is contained in a small time interval. As a consequence the complete spectrum can be predicted with only a very fast simulation. The mathematical techniques developed here forecast promising reduction of simulation durations. [ABSTRACT FROM PUBLISHER]

Part I of this paper has proposed a duty-cycle-space-vector (DCSV)-based modulation strategy for three- and four-leg matrix converters (MCs). This paper develops a digital DCSV-based modulation strategy for the three- and four-leg MCs based on the results of Part I of this paper. The digital DCSV-based modulation strategy is implemented in a DSP–field programmable gate array (FPGA) platform. The objective is to reduce the calculation time of the modulation algorithm by performing the following: 1) reducing the total number of instructions needed to implement the modulation algorithm in the DSP and 2) implementing parts of the modulation algorithm in an FPGA to generate the switching pattern. Therefore, the calculation process of the modulation algorithm is split between the DSP and the FPGA. [ABSTRACT FROM PUBLISHER]

In this paper, we show a new bandstop filter circuit topology. Unlike conventional bandstop filter circuit topologies, the new circuit topology has inter-resonator coupling structures. The presence of these inter-resonator coupling structures enables convenient switching from a bandstop to a bandpass filter. Using the new bandstop filter topology, this paper demonstrates a design of a frequency-agile bandstop-to-bandpass switchable filter. The filter is composed of tunable substrate-integrated cavity resonators and can be switched to have either a bandstop or bandpass response. Switching is achieved by turning on and off switches placed within the filter structure. A prototype of the proposed design is fabricated and the concept is verified experimentally. [ABSTRACT FROM AUTHOR]

Switched boost inverter (SBI) is a single-stage power converter derived from Inverse Watkins Johnson topology. Unlike the traditional buck-type voltage source inverter (VSI), the SBI can produce an ac output voltage that is either greater or less than the available dc input voltage. Also, the SBI exhibits better electromagnetic interference noise immunity when compared to the VSI, which enables compact design of the power converter. Another advantage of SBI is that it can supply both dc and ac loads simultaneously from a single dc input. These features make the SBI suitable for dc nanogrid applications. In this paper, the SBI is proposed as a power electronic interface in dc nanogrid. The structure and advantages of the proposed SBI-based nanogrid are discussed in detail. This paper also presents a dq synchronous-reference-frame-based controller for SBI, which regulates both dc and ac bus voltages of the nanogrid to their respective reference values under steady state as well as under dynamic load variation in the nanogrid. The control system of SBI has been experimentally validated using a 0.5-kW laboratory prototype of the SBI supplying both dc and ac loads simultaneously, and the relevant experimental results are given in this paper. The low cross regulation and the dynamic performance of the control system have also been verified experimentally for a 20% step change in either dc or ac load of SBI. These experimental results confirm the suitability of the SBI and its closed-loop control strategy for dc nanogrid applications. [ABSTRACT FROM AUTHOR]

In this paper, we consider a network that supports multiple multicast flows with network coding. It is well-known that network coding can be used to increase the throughput of a delay-free network. However, as there are multiple multicast flows in the network, packets might be delayed due to contention. As packets from the same flow have to be synchronized for network coding, additional buffers, known as em synchronization buffers in the literature, are required. In certain networks, such as multistage interconnection networks in switch fabrics , the size of internal buffers could be quite limited. One of the key contributions of the paper is to propose a packet scheduling algorithm so that synchronization buffers can be bounded by a em finite constant that only depends on the maximum hop count of the flows. We also show that our scheduling algorithm does not cause any throughput degradation as it can stabilize the network for any em admissible traffic. Moreover, our algorithm is em universal and it does not require to know the rates of the flows in the network. The main idea of our algorithm is to introduce em fictitious packets in the dynamic frame sizing algorithm recently proposed in for stabilizing switches and em wired networks (without network coding). By so doing, packets that might be stalled in synchronization buffers can be flushed out. We show that the number of fictitious packets in each frame is also bounded by a finite constant that only depends on the maximum hop count. [ABSTRACT FROM PUBLISHER]

The recently proposed nand-based digitally controlled delay-lines (DCDL) present a glitching problem which may limit their employ in many applications. This paper presents a glitch-free nand-based DCDL which overcame this limitation by opening the employ of nand-based DCDLs in a wide range of applications. The proposed nand-based DCDL maintains the same resolution and minimum delay of previously proposed nand-based DCDL. The theoretical demonstration of the glitch-free operation of proposed DCDL is also derived in the paper. Following this analysis, three driving circuits for the delay control-bits are also proposed. Proposed DCDLs have been designed in a 90-nm CMOS technology and compared, in this technology, to the state-of-the-art. Simulation results show that novel circuits result in the lowest resolution, with a little worsening of the minimum delay with respect to the previously proposed DCDL with the lowest delay. Simulations also confirm the correctness of developed glitching model and sizing strategy. As example application, proposed DCDL is used to realize an All-digital spread-spectrum clock generator (SSCG). The employ of proposed DCDL in this circuit allows to reduce the peak-to-peak absolute output jitter of more than the 40% with respect to a SSCG using three-state inverter based DCDLs. [ABSTRACT FROM AUTHOR]

This paper studies the implementation of Boolean functions by lattices of four-terminal switches. Each switch is controlled by a Boolean literal. If the literal takes the value 1, the corresponding switch is connected to its four neighbors; else it is not connected. A Boolean function is implemented in terms of connectivity across the lattice: it evaluates to 1 iff there exists a connected path between two opposing edges of the lattice. The paper addresses the following synthesis problem: how should one assign literals to switches in a lattice in order to implement a given target Boolean function? The goal is to minimize the lattice size, measured in terms of the number of switches. An efficient algorithm for this task is presented—one that does not exhaustively enumerate paths but rather exploits the concept of Boolean function duality. The algorithm produces lattices with a size that grows linearly with the number of products of the target Boolean function in ISOP form. It runs in time that grows polynomially. Synthesis trials are performed on standard benchmark circuits. The synthesis results are compared to a lower-bound calculation on the lattice size. [ABSTRACT FROM PUBLISHER]

Variable-speed multiphase (more than three phases) drive systems are seen as serious contenders to the existing three-phase drives due to their distinct advantages. Supply to the multiphase drives is invariably given from a voltage source inverter. However, this paper proposes an alternative solution for supplying multiphase drive system using a direct ac–ac converter called a matrix converter. This paper proposes the pulsewidth modulation (PWM) algorithm for the matrix converter topology with three-phase grid input and five-phase variable-voltage and variable-frequency output. The PWM control technique developed and presented in this paper is based on space vector approach. This paper presents the complete space vector model of the three-to-five-phase matrix converter topology. The space vector model yield 2^15 total switching combinations which reduce to 243 states considering the imposed constraints, out of which 240 are active and 3 are zero vectors. However, for space vector PWM (SVPWM) implementation, only 90 active and 3 zero vectors can be used. The SVPWM algorithm is presented in this paper. The viability of the proposed solution is proved using analytical, simulation, and experimental approaches. [ABSTRACT FROM AUTHOR]

In this paper, a single-phase grid-connected transformerless photovoltaic inverter for residential application is presented. The inverter is derived from a boost cascaded with a buck converter along with a line frequency unfolding circuit. Due to its novel operating modes, high efficiency can be achieved because there is only one switch operating at high frequency at a time, and the converter allows the use of power MOSFET and ultrafast reverse recovery diode. It also features a robust structure because the phase leg does not have a shoot-through issue. This paper begins with theoretical analysis and modeling of this boost-buck converter-based inverter. And the model indicates that small boost inductance will lead to an increase in the resonant pole frequency and a decrease in the peak of Q, which results in easier control and greater stability. Thus, interleaved multiple phases structure is proposed to have small equivalent inductance; meanwhile, the ripple can be decreased, and the inductor size can be reduced as well. A two-phase interleaved inverter is then designed accordingly. Finally, the simulation and experiment results are shown to verify the concept and the tested efficiency under 1-kW power condition is up to 98.5%. [ABSTRACT FROM AUTHOR]

On-chip DC-DC converters have the potential to offer fine-grain power management in modern chip-multiprocessors. This paper presents a fully integrated 3-level DC-DC converter, a hybrid of buck and switched-capacitor converters, implemented in 130 nm CMOS technology. The 3-level converter enables smaller inductors (1 nH) than a buck, while generating a wide range of output voltages compared to a 1/2 mode switched-capacitor converter. The test-chip prototype delivers up to 0.85 A load current while generating output voltages from 0.4 to 1.4 V from a 2.4 V input supply. It achieves 77% peak efficiency at power density of 0.1 W/mm^2 and 63% efficiency at maximum power density of 0.3 W/mm^2. The converter scales output voltage from 0.4 V to 1.4 V (or vice-versa) within 20 ns at a constant 450 mA load current. A shunt regulator reduces peak-to-peak voltage noise from 0.27 V to 0.19 V under pseudo-randomly fluctuating load currents. Using simulations across a wide range of design parameters, the paper compares conversion efficiencies of the 3-level, buck and switched-capacitor converters. [ABSTRACT FROM PUBLISHER]

Beam diagnostics is important to guarantee good quality of beam in a particle accelerator. Both the electron and positron run in the tunnel in some modern electron–positron colliders such as circular electron–positron collider (CEPC) to be built and Beijing Electron–Positron Collider II (BEPC II). To measure the electron and positron beams, picking-up these two different bunches in real time is a notable concern. As the time interval between adjacent electron and positron bunches is quite small, for example, 6 ns in CEPC, high-speed switch electronics is required. This paper presents the prototype design of a high-speed radio frequency (RF) electronics that can pick up nanosecond positron–electron beam bunches with a switching time of fewer than 6 ns. Fast separation of electron and positron is achieved based on RF switches and precise delay adjustment of the controlling signals (∼10 ps). Initial tests have been conducted in the laboratory to evaluate the performance of electronics; the results indicate that this circuit can successfully pick up the bunch signal within a time interval of 6 ns, which makes it possible to further measure the electron and positron beams simultaneously. [ABSTRACT FROM AUTHOR]

This paper presents a 10.56-GHz transceiver with ultracompact transformer-based transmit/receive (T/R) switching via matching network reuse. The reused transformer can operate as T/R switch and impedance matching networks for a power amplifier (PA) and a low-noise amplifier (LNA) simultaneously. The T/R switch, PA, and LNA are fully codesigned, and the interstage matching networks of the PA and LNA are comatched with the T/R switch to improve the performance of the front end (FE). A three-coil transformer is introduced in the PA to improve the linearity and bandwidth of the FE in the transmit (TX) mode. A mode selection unit (MSU) is also utilized in LNA to improve the TX/RX isolation and the linearity of the FE in the TX mode. Utilizing the fully codesign technique in the FE, the bandwidth of the FE is extended to over 4.2 GHz in both the TX and RX modes. A novel “gm-cell-based” broadband programmable gain amplifier (PGA) and a third-order transconductance-capacitor (gm-c) low-pass filter (LPF) are used in analog baseband to provide over 24-dB gain and 1.8-GHz bandwidth adjustment range with ultralow dc power consumption. To prove the concept, the new architecture is implemented in 28-nm CMOS technology. Measurement results prove that the insertion loss of the proposed T/R switch introduced in both the TX and RX modes is ~0.5 dB, and benefiting from this, the RX obtained a 4.2-dB noise figure, and TX obtained 9.9- and 14.1-dBm OP1dB and Psat. The measured single sideband bandwidth of the transceiver is wider than 2.1 GHz in both the TX and RX modes. [ABSTRACT FROM AUTHOR]

A component-minimized and low-voltage-stress single-phase power factor correction rectifier without electrolytic capacitor is proposed in this paper. Component minimization is achieved by embedding an active pulsating-power-buffering (PPB) function within each switching period, such that typical add-on power electronic circuits for PPB are no longer needed. Additionally, with a three-level flying-capacitor configuration, the voltage stresses of switching devices can be reduced more than 50% as compared to existing solutions that are based on embedded PPB. The relationship between the inductance requirement and the patterns of the modulation carriers, and how it can be utilized to minimize the magnetics of the rectifier, is also discussed. A 110 W hardware prototype is designed and tested to demonstrate the feasibilities of the proposed rectifier. An input power factor of more than 0.97, peak efficiency of 95.1%, and an output voltage ripple of less than 4.3% across a wide load range have been experimentally obtained. [ABSTRACT FROM AUTHOR]

Many research works have been conducted on increasing the efficiency of interleaved boost converters (IBCs) applied for power factor correction (PFC) by using high-performance power electronic devices and soft switching circuits, which are not helpful in reducing the hardware cost and systematic complexity. In this paper, three intrinsic parameters affecting the efficiency of IBC PFC are found and analyzed, including the switching frequency value, boost inductor value, and output voltage value. Based on the findings, considering the limitations of current ripples, power factor, maximum magnetic flux density, and volume of a boost inductor, an optimization design method for high-efficiency IBC PFC is proposed. A 3.3-kW IBC PFC prototype is developed based on Si devices. The experimental result verifies that the proposed method can improve the efficiency of IBC PFC with low-cost low-performance devices in the full-load range. [ABSTRACT FROM AUTHOR]

This paper presents a new approach aiming at simulating the steady-state response of dc–dc switching power converters. The proposed method uses the main concept behind the harmonic balance (HB) to compute the amplitudes of the harmonic content in the steady-state waveform. The proposed approach extends the basic HB to enable its efficient implementation to the power converter circuits, through developing equivalent frequency-domain-based stamps for ideal switching elements. The new technique is formulated to yield, along with the amplitudes of the harmonics, the switching times in the ideal switching elements, resulting in the convergence of the Newton method being obtained within few iterations. A major advantage in the proposed method is that it enables removing the control circuitry, which reduces the size of the circuit and significantly contributes to the efficiency of the method. Experimental results show significant speedup over commercial SPICE-based simulators. [ABSTRACT FROM AUTHOR]

The multigap gas switch has been widely used in liner transformer drivers (LTDs), but there is still room for improvement on its self-breakdown and triggering characteristics. In this paper, based on the circuit model of the six-gap gas switch, the gap voltage distribution during the charging and triggering process is analyzed, and the optimization on self-breakdown and triggering characteristics by mounting resistors and capacitors in parallel with switch gaps are theoretically and experimentally investigated. The results indicate that compared with the original switch, when the self-breakdown voltage is about ±90 kV, the standard deviation is reduced from 7.5 to less than 3 kV; for a charging voltage of ±80 kV and by operating at 60% working coefficient, when the negative trigger voltage is 75 kV, the jitter of the switch is reduced from 6.1 to 1.4 ns. [ABSTRACT FROM AUTHOR]

This paper proposes a single-vector-based model predictive control (MPC) for an induction motor drive supplied by a three-level neutral-point-clamped inverter operating at a low switching frequency. Unlike the torque and flux control in the conventional MPC, the proposed MPC tries to minimize the error between the applied voltage vector and a reference voltage vector obtained based on the principle of deadbeat control, thereby reducing the number of weighting factors in the cost function. To reduce the computational burden and restrict the high jumps in both phase and line voltages, two switching tables are proposed and compared for the preselection of candidate voltage vectors. The neutral point potential fluctuation and switching frequency are also included in the cost function to achieve the balance between the upper and lower dc voltages and a relatively low switching frequency. Furthermore, a speed adaptive stator flux observer with a novel gain matrix is proposed to achieve speed-sensorless operation, which has a higher speed and flux estimation accuracy than conventional fixed gains. Finally, the proposed MPC is extended to the field-weakening operation by adjusting the torque and stator flux references online, which significantly widens the speed range and improves the practical value of the MPC. The effectiveness of the proposed method is confirmed by the experimental results obtained at an average switching frequency of less than 600 Hz. [ABSTRACT FROM AUTHOR]

Series–parallel forward dc–dc converter system is a good option in high-voltage high-power applications. A switch fault, in this converter, should be detected as soon as possible, to avoid further damage and save maintenance cost. In this paper, a new switch fault diagnosis method, which treats output inductor voltages as diagnostic criteria, is proposed for this system. With the proposed method, expensive sensors are needless, since diagnostic signal can be easily acquired by adding a small auxiliary winding into inductor magnetic core. Based on the feature of diagnostic signals in such a system, a low-cost diagnostic circuit is designed. The failed module caused by open-circuit fault or short-circuit fault could be detected within one switching period, allowing for an immediate fault-tolerant action. This method also shows generality for different connections and buck-type isolated topologies. Besides, it works reliably under input-voltage variation and load step, and no misdiagnosis will occur during normal dynamic process. Finally, experimental result verifies the effectiveness of this method. The proposed scheme has a good potential to be applied in real applications for its simplicity and robustness. [ABSTRACT FROM AUTHOR]

This paper presents the design, analysis, and verification of a novel reaching law for discrete-time sliding-mode control. The control gains of the reaching law are automatically regulated by the power function and the exponential term that dynamically adapts to the variation of the switching function. The reaching law also employs the perturbation estimation and the difference function to redefine the change rate as the second-order difference of the uncertainty. Compared with previous methods, the proposed reaching law has the capability to amend the control gains in a wise manner, further mitigate chattering, and guarantee a smaller width of the quasi-sliding-mode domain (QSMD). In order to describe the system dynamics in the reaching phase and the sliding phase with respect to control gain values, both the decrement band and the QSMD (ultimate band) of the proposed reaching law are theoretically analyzed. The reaching steps for the switching function to converge toward the sliding surface are also obtained. The effectiveness of the proposed method is verified through numerical simulations and experimental investigations on a piezoelectric actuator. [ABSTRACT FROM AUTHOR]

Two parallel interleaved two-level (2L) three-phase voltage source inverters (VSIs) can be analyzed as a single three-level (3L) VSI. A generalized carrier-based method is proposed in this paper for implementing different 3L pulsewidth modulation (PWM) techniques using two parallel interleaved 2L VSIs. The proposed method modifies the given three-phase reference signals of 3L VSI for implementation of the PWM technique using two parallel interleaved 2L VSIs. The influence of nonidealities on the equivalent 3L PWM switching sequences is also discussed. To overcome the effect of nonidealities, a new modified discontinuous PWM technique (MDPWM1) is proposed. The analysis of different performance indices is carried out for different 3L PWM techniques, and the key advantages of different PWM techniques are identified. Simulation and experimental results are also presented. [ABSTRACT FROM AUTHOR]

In this paper, a high step up converter consisting of an integrated quadratic-boost converter and a voltage doubler is proposed. The integration of the quadratic-boost converter makes the system easier to lift up its voltage gain through slightly increasing the duty ratio of the single switch. The voltage doubler further increases the voltage gain of the system as the turn ratio rises. The voltage stresses on the switch and the diodes are decreased for such cascaded topology. Different operation modes are analyzed and mathematical analysis of the converter is presented in detail. The leakage inductance contributes to realizing zero current switching of the diodes in the second boost stage and the doubler and the energy can be recycled to the load. A 38-W prototype is built to work as a vehicle LED driver. Experiments are conducted to verify the advantages of the proposed converter and the efficiency is 90% at the nominal operating point. [ABSTRACT FROM AUTHOR]

Active pulsating power buffering (PPB) function can effectively reduce the twice-line frequency energy storage requirement in a single-phase rectifier. Existing single-phase solutions with active PPB must utilize more than two active switches in their circuits. Compared with conventional single-active-switch solutions without active PPB (e.g., a boost power-factor-correction (PFC) rectifier), the cost of additional semiconductor switches and gate drive circuitry in an active PPB-based rectifier may not be justified for low-power applications. This paper presents a family of single-switch single-phase rectifier with active PPB. Taking advantage of the on-time and off-time of a single switch, the proposed rectifiers are formulated by merging two converters that are duty and frequency controlled. The steady-state characteristics of these converters are analyzed. A step-by-step design procedure is provided, and an active control method for limiting the maximum switching frequency for wide-load-range operation is presented. A 100-W prototype is built for the demonstration of the proposed single-switch rectifier concept. It is envisaged that this concept, when combined with other circuit formulation techniques, e.g., partial power processing, dc-voltage feedback, may lead to new derivatives of single-switch rectifiers with more advanced features. [ABSTRACT FROM AUTHOR]

In this paper, the requirements of device cross section and aspect ratio (AR) are examined to facilitate steep switching in heavily doped 3-D multiple gate junctionless (JL) transistors. It is shown through well-calibrated simulations and physical insights that the sharp OFF-to- ON switching action is predominantly governed by the area of cross section (${A} _{\textsf {cross}}$) instead of the gate length. A 3-D JL architecture preferably oriented toward a planar topology, i.e., with wider fin and low AR, is conducive for steep switching as a greater bulk area is available for impact ionization. On the contrary, narrow vertical architectures with AR > 1 suppress ${A} _{\textsf {cross}}$ in the bulk and are less likely to support the steep current transition. Steep switching specific scaling methodology is showcased to attain a sharp increase in drain current with a sub-60 mV/decade swing in a tri-gate JL transistor along with an associated negative value of total gate capacitance. [ABSTRACT FROM AUTHOR]

In this paper, a new modified single-switch single-ended primary inductor converter (MS2-SEPIC)-based high step-up dc–dc converter is presented. The proposed topology uses the coupled-inductor (CL) technique and a voltage tripler rectifier, which results in a high voltage gain for the converter. Here, the switching loss has been reduced significantly owing to the quasi-resonance operation of the circuit created by the leakage inductance of the CL along with circuit capacitors. The operational principles and steady-state analysis are discussed. Experimental results based on a 100 W laboratory prototype verify the validity of theoretical analysis. [ABSTRACT FROM AUTHOR]

In this paper, a fixed switching frequency model predictive current controller is designed and implemented on a sensorless five-level packed U-cell (PUC5) inverter interfacing the utility. The predictive control methodology is based on a voltage vector generation technique for the cost function optimization by nullifying its derivative. The aim of the controller is to allow a fixed-frequency operation with no iterations while operating as a utility line current regulator. A pulsewidth modulator based on employing PUC5 redundant switching states fixes the PUC5 auxiliary dc bus capacitor voltage to its desired level with no necessity of a regulator; the overall technique reduces system complexity with less sensors and no loops in the predictive algorithm making it suitable for industrial applications. System discrete model is developed and experimental results verify the performance of the designed controller in making a fast response in regulating the grid current and balancing the capacitor voltage. [ABSTRACT FROM AUTHOR]

When the selected harmonic elimination pulsewidth modulation (SHEPWM) is adopted to three-level neutral-point-clamped converters to reduce the switching frequency, the neutral-point potential (NPP) problem becomes more severe compared with other modulations. It is because there is no degree of freedom for SHEPWM to control the NPP. SHEPWM realizes a better harmonic performance by calculating the switching angles offline based on harmonic requirements. Since it is harsh to solve the angles online, we cannot change the angles to control the NPP. Aiming at the low-frequency NPP fluctuation minimum, a novel current harmonic minimum method based on the optimal third-order/ninth-order harmonic is proposed in this paper. The optimal third-order/ninth-order harmonic is derived based on the relationships among the third-order/ninth-order harmonic and the NPP. They can be utilized to realize the low-frequency NPP fluctuation minimum without changing any switching angle online. Moreover, some comparisons, such as the solution ranges, weighted total harmonic distortion, the initial value of iteration calculation, show that the proposed method has a good output performance. Finally, the experimental results are given to verify the validity of the proposed method. [ABSTRACT FROM AUTHOR]

In photovoltaic systems, dc–dc converters have been identified as one of the most critical and challenging subsystem in terms of failure rate. Thus, this paper proposes fault-tolerant operation of a two-stage buck/buck–boost converter under open-circuit switch failure. Remedial actions are efficient in any failure of one of the two switches of the converter. Here, a new unified approach is considered, for the overall fault-tolerant operation of the two stages of the converter. The fault-tolerant circuit we propose lies on performing redundancy by implementing the equivalent synchronous switch for the two main switches of the two stages, in offline mode. The fault-tolerant circuit results from the basic two-stage buck/buck-boost converter and its equivalent circuit with a synchronous switch, merged together to form the new dc–dc fault-tolerant circuit. Therefore, postfault operation at full power can also be performed. By using a switch fault management unit with reduced complexity, inserted between the control block and the switches, we have designed an unified, efficient, and optimized fault-tolerant control, suitable in both healthy and postfault operations. Some selected experimental tests, which all confirm the good performances of the proposed fault-tolerant approach, are presented and discussed. [ABSTRACT FROM AUTHOR]

Flyback converter has advantages of simple circuit configuration and easy control. However, it suffers two problems. One is the active switch is hard switching. The other is a very high voltage spike when the active switch is turned off. In order to solve these problems, this paper presents a novel dc-to-dc converter that mainly consists of two interleaved flyback converters. Both active switches can achieve zero-voltage switching on without the use of any active clamp circuit or snubber circuit. In addition, the leakage flux energy can be delivered to the output by using two added diodes. It helps to reduce the voltage spikes on the active switches and improve circuit efficiency. The steady-state analyses at different operation modes and the mathematical equations for parameters design are provided. Finally, a 200-W prototype circuit for driving high-brightness light-emitting diodes (LEDs) is built and tested to verify the feasibility of the proposed circuit. The LEDs are dimmed from 100% to 10% full power. Satisfactory performances are obtained from the experimental results. [ABSTRACT FROM AUTHOR]

This paper proposes a family of multiport switched-capacitor multilevel inverter (SCMLI) topologies for high-frequency ac power distribution. It employs asymmetric dc voltage sources with a common ground that makes it ideal to be employed in renewable energy farms and modern electric vehicles. The proposed family of step-up SCMLI attains higher number of output voltage steps with optimum component count in comparison to several existing topologies. The problem of capacitor voltage balancing is solved as the capacitors are inherently charged to a finite voltage every half cycle. In-depth study on two staircase modulation strategies, namely, selective harmonic elimination and minimum total harmonic distortion (THD) scheme is presented with study on the variation of switching angles and THD with modulation indices under both schemes. Working principle and analysis are presented for the proposed family of topologies. Simulation outcomes are validated with experimental results under both the aforementioned modulation schemes with equal and unequal output voltage waveform steps. [ABSTRACT FROM AUTHOR]

Switched-capacitor converter (SCC) features a compact solution due to its magnetic-less structure, which fulfills the high density requirement in low power applications. Compared to other SCC topologies, Fibonacci switched-capacitor converter (FSC) utilizes the least number of flying capacitors to perform any voltage conversion. This paper proposes a monolithic voltage-scalable FSC, which can be used in energy harvesting applications. The challenges to implement on-chip FSC are addressed. The parasitic charge loss is substantial in FSC. Therefore, a charge recycling technique exploiting the presence of parasitic capacitors in each other phase of FSC has been employed resulting in 27% reduction in the power loss, which improves the overall efficiency by 12.7%. For a proof of concept, the proposed converter is implemented in 0.5- $\mu \text{m}$ CMOS technology on 4-mm2 die area. The postlayout simulation is carried out using Virtuoso ADE. With 0.3-V input voltage, the system achieves 47.5% peak power efficiency with 5- $\mu \text{W}$ load. [ABSTRACT FROM AUTHOR]

Soft-switching inverters can achieve high efficiencies and low switchdv/dtanddi/dt, but often impose additional stress on the switches due to their resonant behavior. Multicell converters, on the other hand, can process high voltages by arranging the switches to share the stress. This paper proposes a buck–boost multicell soft-switching inverter with inherent cell voltage balancing. Both the current and voltage stresses are shared by the cells. Soft-switching conditions are achieved for all switching transitions without any need for auxiliary circuitry or clamps. A multiple-winding transformer transfers energy between the terminals and provides galvanic isolation. An analytical study and experimental results on a 1200-W prototype verify the operation of the inverter. [ABSTRACT FROM AUTHOR]

In this paper, a sequence switching control (SSC) scheme based on an auxiliary parallel inductor is proposed to improve the transient performance of buck converters. The proposed SSC scheme introduces a small controlled inductor in parallel with the output inductor, so as to increase the inductor-current slew rate when it is activated during a load transient. Furthermore, an “n+ 1” sequence switching strategy is proposed to control the auxiliary parallel inductor. The proposed scheme divides the transient event inton+ 1 periods. In the formernperiods, the same small output voltage deviations are designed, while in the last period, a smaller deviation is done for a smooth transition from the transient to the steady state. The switching sequence is derived applying the capacitor–charge balance principle for each ofn+ 1 periods. For a given buck converter in the experiment, the settling time and the output voltage deviation of the proposed SSC scheme enhance more than 50% and 67%, respectively, over those of the time-optimal control for a 3-A load step. [ABSTRACT FROM AUTHOR]

A new light emitting diode (LED) driver circuit is presented in this paper based on the buck converter with coupled inductors for automotive applications. Soft-switching condition is provided for the switch via a passive resonant circuit incorporating the leakage inductance of the coupled inductors. Also, the leakage inductance energy is recycled to the output. The proposed converter has a very simple structure as well as high efficiency, which makes it a good candidate for battery-operated applications. The proposed converter only applies one magnetic element and the leakage and magnetizing inductances are used as resonant elements. Also, during the resonance, a resonance capacitor is approximately charged to the input voltage, and therefore, the capacitor voltage stress and semiconductor devices voltage stress are low. These are the main advantages of the proposed converter over other similar converters. The theoretical analysis is provided and the operating principles and design considerations are explained. An 8 W laboratory prototype is implemented in order to prove the validity of the theoretical analysis. [ABSTRACT FROM AUTHOR]

Series connection of individual semiconductors is an effective way to achieve higher voltage switches. However, the inherent unequal dynamic voltage sharing problem needs to be solved, even when well-matched gate drivers and semiconductors are used. A majority of the existing voltage balancing schemes are developed for slow-switching silicon (Si)-based semiconductors, and are also associated with a significant amount of additional losses in the control circuit or on the switches. In this paper, a novel method is proposed for balancing the dynamic voltages among series-connected silicon carbide (SiC) MOSFETs with highdv/dtrates. The method takes advantage of a small capacitor to provide additional current to the gate of the MOSFETs at turn-off, meaning the switching speed (and thus, the device voltage after turn-off) is controlled. The proposed method generates negligible losses in the control circuit, and also does not significantly increase the switching losses of the semiconductors. Experimental results are provided to prove the effectiveness of the proposed voltage balancing scheme on two SiC MOSFETs inside a module connected in series. In order to do so, an active gate driver is designed embedding the activedv/dtcontrol scheme as well as other essential functionalities needed for operation of SiC MOSFETs. [ABSTRACT FROM AUTHOR]

This paper presents an active microchannel neural interface (MNI) using seven stacked application specific integrated circuits (ASICs). The approach provides a solution to the present problem of interconnect density in three-dimensional (3-D) MNIs. The 4 mm2 ASIC is implemented in 0.35 μm high-voltage CMOS technology. Each ASIC is the base for seven microchannels each with three electrodes in a pseudo-tripolar arrangement. Multiplexing allows stimulating or recording from any one of 49 channels, across seven ASICs. Connections to the ASICs are made with a five-line parallel bus. Current controlled biphasic stimulation from 5 to 500 μA has been demonstrated with switching between channels and ASICs. The high-voltage technology gives a compliance of 40 V for stimulation, appropriate for the high impedances within microchannels. High frequency biphasic stimulation, up to 40 kHz is achieved, suitable for reversible high frequency nerve blockades. Recording has been demonstrated with mV level signals; common-mode inputs are differentially distorted and limit the CMRR to 40 dB. The ASIC has been used in vitro in conjunction with an oversize (2 mm diameter) microchannel in phosphate buffered saline, demonstrating attenuation of interference from outside the microchannel and tripolar recording of signals from within the microchannel. By using five-lines for 49 active microchannels the device overcomes limitations when connecting many electrodes in a 3-D miniaturized nerve interface. [ABSTRACT FROM AUTHOR]

This paper presents a subharmonic switching (SHS) digital power amplifier (PA) architecture that enhances power efficiency in the power back-off (PBO) region. The proposed technique can be combined with the class-G operation. By using either SHS or dual-power supply switching, it can provide several peak efficiency points, located at 0, −3.5, −9.5, and, −13 dB PBO. By judiciously choosing the optimal operation mode between SHS and dual supplies for each PA cell at different output power levels, we can further improve the efficiency between peaks. The SHS PA prototype is implemented with a switched-capacitor PA (SCPA) architecture in 65-nm CMOS to validate the effectiveness of the proposed technique, which achieves a 26.8-dBm peak output power with a 49.3% peak drain efficiency (DE) at 2.25 GHz and a 27% DE at −13-dB PBO. [ABSTRACT FROM AUTHOR]