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Timing analysis and timing closure are critical steps in digital circuit design. To ensure an error-free design, timing constraints are usually set-based upon the longest path delay from static timing analysis. However, a circuit could have dramatically different internal activity because of the variation of input workload. The path with the longest delay may not be active for certain input workloads, which would enable timing speculation for increased performance. This paper describes an approach to identify the greatest contributors of timing errors and mitigate those errors by replacing certain standard cells in the design. We evaluated our mitigation for several benchmark designs and demonstrated an error-free performance gain up to 37%. The entire design flow uses Synopsys electronic design automation tools and customized scripts, which can be adapted for other designs. [ABSTRACT FROM AUTHOR]

A four-path filter/mixer for surface acoustic wave (SAW)-less frequency division duplex (FDD) radio receivers is proposed, targeting high linearity and compression requirements. A bottom-plate mixing technique improves linearity by reducing the gate-source voltage modulation of the MOSFET switches. Differential bottom-plate mixing allows for switch sharing which halves the effective switch resistance to reduce drain-source voltage modulation. The first four-path switch-RC filter stage with bottom-plate mixing and a shared switch renders 2nd-order voltage-domain RF-bandpass filtering around the LO frequency. Extra out-of-band rejection is implemented combined with $V$ – $I$ conversion and zero-IF frequency down-conversion in the second cross-coupled switch-RC four-path stage, which offers a low-ohmic high-linearity current path for out-of-band interferers. A prototype chip fabricated in a 28-nm CMOS technology achieves an out-of-band IIP3 of +44 dBm, IIP2 of +90 dBm and blocker 1-dB gain-compression point of +13 dBm for a blocker frequency offset of 80 MHz. At this offset frequency, the measured desensitization is only 0.6 dB for a 0-dBm blocker, and 3.5 dB for a 10-dBm blocker at 0.7-GHz LO (i.e., 6- and 9-dB blocker noise figure). The chip consumes 38–96 mW for LO-frequencies of 0.1–2 GHz and occupies an active area of 0.49 mm2. [ABSTRACT FROM AUTHOR]

This paper proposes a high-efficiency single-phase T-type boundary conduction mode (BCM) microinverter. The conventional full-bridge BCM microinverter has achieved zero voltage switching (ZVS) and thereby improved the efficiency, but it suffers from high switching losses under light load conditions. The proposed T-type BCM microinverter reserves ZVS and uses a multilevel technique to further decrease the switching losses. The BCM operation with multilevel technique will have too low switching frequency when the grid voltage approaches half of the dc link voltage. To solve this problem, this paper adopts a third operation mode for the T-type switching leg to maintain the switching frequency above a minimum value. The corresponding mode transitions are also detailed to ensure a smooth operation. Because of the turn-offdelay of the freewheeling transistor, the actual lower current boundary deviates from the programmed one, which will distort output current. To address this issue, this paper also proposes a boundary compensation method. A prototype has been built for performance verification, which can test both full-bridge and T-type topology. Compared with the full-bridge BCM microinverter, the proposed T-type BCM microinverter has a higher efficiency over the whole load range. [ABSTRACT FROM AUTHOR]

Feedback field-effect transistor (FBFET), an alternative switching device, has received attention due to its ideal steep switching feature. By utilizing the positive feedback phenomenon, the total amount of electrons and holes contributing to drain current is sharply surged. Although the device has conspicuous subthreshold slope (SS) properties, advanced research for structure and performance of it is lacking. In this paper, single-gated and spacer-less silicon-on-insulator (SOI) FBFET with extremely steep switching (~1 mV/decade) characteristic is studied in various aspects; SS attribute, performance variation of scaled FBFET, the impact of structural variation, the gate margin for the device layout, and the hysteresis window. The prospect of SOI FBFET as a future candidate for CMOS logic application is investigated in detail. [ABSTRACT FROM AUTHOR]

This paper investigates utilizing a heterogeneous group of thermostatically controlled loads (TCLs) for long-term demand response applications. The steady-state services are achieved through manipulating the stored thermal-energy with minimal impact on devices’ switching rates and the operating duty-cycles. The Markov chain abstraction method has been developed in literature for aggregating the TCLs at fixed temperature set-point. In this paper, an extended Markov model (EMM) is proposed to account for the dynamics involved in modifying various set-point magnitudes in both directions. The EMM is formulated online based on linear mapping and fast restructuring to Markov chains developed offline at fixed set-points, where a training process is used to construct each Markov chain. Set-point adjustments force devices to operate in a synchronized pattern, causing the aggregated power to oscillate or traverse extreme conditions. Therefore, model predictive control with direct ON/OFF switching capability is proposed to apply the set-point change sequentially and control devices’ movement toward the new operating set-point. The performance of the proposed modeling and control techniques are compared against existing methods which rely on the direct ON/OFF control solely rather than adjusting the thermal-energy level. [ABSTRACT FROM AUTHOR]

This paper presents an ultra-low-voltage (ULV) $300\times 200$ pixel pulsewidth-modulation (PWM) CMOS imager with monitoring and capturing for Internet-of-Things (IoT) and artificial intelligent (AI) applications, fabricated in the CMOS 0.18- $\mu \text{m}$ standard process technology. In always-ON monitoring operation, the imager provides high dynamic range (HDR) and energy harvesting (EH) modes for event detection and energy collection, respectively. In low-power image capturing operation, the imager provides a linear-response (LR) mode for object identification and recording. In the LR mode, the proposed ULV PWM pixel with threshold variation cancellation (TVC) achieves a non-linearity of +0.36/−0.29% and a fixed-pattern noise (FPN) of 0.159%. With the proposed pixel-wise adaptive-multiple-sampling (AMS) scheme and the corresponding $n$ -time multiple sampling using dual-slope ramping (DSR) reference, the 0.4-V-operated PWM pixel achieves a total noise of 9.42e− at 4-time AMS operation. The achieved peak signal-to-noise ratio (PSNR) and dynamic range (DR) are 60.1 dB in the LR mode and 141 dB in the HDR mode, respectively, and the harvested power is 15.5 $\mu \text{W}$ at 60 klx in the EH mode. [ABSTRACT FROM AUTHOR]

A parallel hybrid modular multilevel converter (PHMMC) belongs to the class of modular multilevel converters, which have become potential candidates for high-voltage direct-current (HVDC) transmission systems. Due to the circuit topology of a PHMMC, the dc bus voltage contains low-order harmonics and cannot be fully regulated at a constant dc voltage. The dc bus voltage, if not properly controlled, leads to improper power transfer and increases the magnitude of dc current ripple on the dc transmission line. This paper proposes a zero-sequence voltage injection (ZSVI)-based model predictive control (MPC) strategy to control the dc current/power flow and simultaneously minimize the dc current ripple. The proposed strategy takes advantage of a cost function minimization technique to determine and inject the optimal zero-sequence voltage components into the dc- bus voltage of a PHMMC system. This paper derives a discrete-time dynamic model of the dc transmission-line current and, correspondingly, develops a predictive model. The predictive model is used to inject the appropriate amount of zero-sequence voltage components to the dc bus reference voltage waveform. Compared with the existing triplen harmonics injection method, the proposed ZSVI-MPC strategy improves the performance of a PHMMC system in terms of minimization of the dc current/voltage ripple. Performance of the proposed strategy for a 21-level PHMMC-based HVDC station system is evaluated based on time-domain simulation studies in the PSCAD/EMTDC software environment. The reported results demonstrate superior performance of the PHMMC-HVDC station operating based on the proposed ZSVI-MPC strategy, under various operating conditions, as opposed to the existing triplen harmonics injection method. [ABSTRACT FROM AUTHOR]

This paper investigates the applicability of averaged-value models (AVMs) for modular multilevel converters (MMCs) operating in a voltage-sourced converter-based-high-voltage dc (VSC-HVDC) grid. The AVM models are benchmarked by comparison with a detailed electromagnetic transient model of the grid, including a fully detailed MMC model. Analysis results show that the AVM is only effective as long as the capacitors are large enough to maintain nearly constant voltage across each MMC submodule. This paper also shows that previously developed MMC averaged models are not able to accurately simulate the transients under dc fault conditions. This paper introduces topology changes to a previously proposed averaged model that results in much improved simulation for such conditions. This paper also shows that the model can be used effectively to study HVDC grids with significant time savings. [ABSTRACT FROM AUTHOR]

This paper presents a new power electronic topology that aims to reduce switching losses in hard-switched inverters for brushless dc (BLDC) motor drives. This is achieved by extending the benefits of synchronous rectification used in low-voltage switch-mode dc–dc conversion to high-voltage motor drive applications and by minimizing the reverse conduction behavior of the intrinsic body diode of the synchronous rectifier MOSFET. The proposed topology for reducing body diode conduction includes the addition of a MOSFET in series with the rectifying switch and a SiC Schottky diode around the series switch combination. This paper focuses on theory, simulations, and experimental results and validates the benefits of proposed new topology for BLDC motor drive applications. An extension of this topology for sinusoidal back electromotive force permanent-magnet motors is also presented. [ABSTRACT FROM PUBLISHER]

This paper considers real-time energy-optimal trajectory generation for a servomotor system that performs a single-axis point-to-point positioning task for a fixed time interval. The servomotor system is subject to acceleration and speed constraints. The trajectory generation is formulated as a linear-constrained optimal control problem (LCOCP), and the Pontryagin's maximum principle is applied to derive necessary optimality conditions. Instead of solving multipoint boundary value problems directly, this paper proposes a novel real-time algorithm based on two realizations: solving the LCOCP is equivalent to determining an optimal time interval of the speed-constrained arc and solving a specific acceleration-constrained optimal control problem (ACOCP), and solving an ACOCP is equivalent to determining optimal switch times of acceleration-constrained arcs and solving a specific two-point boundary value problem (TBVP). The proposed algorithm constructs sequences of time intervals, ACOCPs, switch times, and TBVPs, such that all sequences converge to their counterparts of an optimal solution of the LCOCP. Numerical simulation verifies that the proposed algorithm is capable of generating energy-optimal trajectories in real time. Experiments validate that the use of energy-optimal trajectories as references in a servomotor system does not compromise tracking performance but leads to considerable less energy consumption. [ABSTRACT FROM PUBLISHER]

This paper proposes a vector control strategy for independent control of two permanent-magnet synchronous motors (PMSMs) using a single four-leg inverter (4LI). An expanded two-arm modulation to obtain a balanced three-phase output voltage is described. This paper also proposes a method to compensate for the fluctuations in the neutral point voltage of two split capacitors in the dc link. The experimental results show that independent speed and position control of two PMSMs can be achieved using a single 4LI with the proposed vector control method. [ABSTRACT FROM AUTHOR]

This paper demonstrates and discusses the roles of hole injection from the silicon substrate and inclusion of sub-oxide and metallic Si atoms in the repeatable resistance switching of sputter-deposited silicon oxide films. The roles of not only Si sub-oxide but also metallic Si atoms, are investigated in detail. In addition, we show how the structure of the interface between conductive filaments in the low-resistance state and the surrounding silicon oxide film influences the achievement of repeatable resistance switching. [ABSTRACT FROM AUTHOR]

This paper proposes a new most significant bit (MSB)-prediction switching scheme and presents an energy-efficient successive approximation register (SAR) analog-to-digital converter (ADC) using the proposed scheme. The prediction of the MSB is conducted before the sampling phase, and the MSB-1 conversion switches all the capacitors of the capacitive digital-to-analog converter (CDAC) from the references set by the prediction result after the sampling phase. Therefore, the reference voltage in the proposed scheme is reduced by half to satisfy the same input range. Compared with the regular Vcm-based CDAC, the proposed technique exhibits a 75.1% reduction in switching energy and a reduction ratio of (1/2)1/2in nonlinearity under the same capacitor area and matching condition. A 10-bit SAR ADC prototype is designed and simulated in a 180-nm CMOS process to validate the proposed technique. The ADC consumes $31.16~\mu \text{W}$ from a 1-V supply and the input range of [−2 V, 2 V]. The simulated signal-to-noise-and-distortion ratio is 61.01 dB at 2 MS/s, benefited from the redundant capacitors added to the CDAC. [ABSTRACT FROM AUTHOR]

In this paper, we propose a high-speed (kilohertz–megahertz), reconfigurable current starved ring oscillator (CSRO)-based true random number generator (TRNG) design. The proposed TRNG exploits the intradevice stochastic variations in resistive RAM switching parameters and random telegraph noise (RTN). We demonstrate the effect of RTN on the jitter of CSRO oscillations. We also propose a methodology to reconfigure the TRNG to generate new random numbers. The proposed 10-bit TRNG is validated by NIST test suite for randomness in the data stream. Energy/bit is 22.8 fJ for generation, and the speed of random data generation is 6 MHz. Security vulnerabilities and countermeasures of the proposed TRNG are also investigated. [ABSTRACT FROM AUTHOR]

On transmission lines where switching surges are not mitigated with closing resistors and/or surge arresters, high-speed reclosing on a line with trapped charge will produce high overvoltages that have been measured above 3 p.u. Careful simulations of these switching events using available electromagnetic transient (EMT) programs consistently produce significantly higher voltages than the measurements. This indicates a phenomenon present on the line that acts to reduce the switching surge magnitudes but is not typically modeled. This paper aims to identify the required simulation practices in reproducing the field measured overvoltages in EMT simulations and investigates the sensitivity of results to modeling approaches and electrical parameters. Field measurements from a switching surge test of a 230-kV line without surge mitigation have been used for model comparisons. Variations in frequency-dependent line modeling, ground resistivity, skin effect, shunt conductance, parallel lines, and source-side detail have been tested in an unsuccessful attempt to decrease the difference between the field measurements and the higher simulation overvoltages. It is demonstrated that even though the pattern of the transient voltage waveforms can be reproduced very well using frequency-dependent line models, the magnitude of the maximum overvoltage is significantly overestimated unless the effect of corona is considered. Two types of corona models are tested, and both demonstrate that corona is the primary factor that allows the simulations to correctly reproduce high peak overvoltage measurements. [ABSTRACT FROM AUTHOR]

In this paper, the NbOx, which was regarded as a promising material based on its insulator–metal transition (IMT) effects, was applied as the switching layer of the device. The threshold switching characteristics were comprehensively investigated with particular emphasis on temperature dependence. The conduction mechanism for high-resistance state (HRS) was fitted and verified to be Schottky emission. With the increase in temperature, the fitting results demonstrated that the Schottky barrier decreased, leading to a reduction in the resistance of HRS. Furthermore, according to Fourier’s law of heat conduction, the fluctuation range of temperature was smaller, causing a narrow distribution of the threshold voltage as the operating temperature increased. In addition, the increasing temperature caused high energy of electrons, which would induce an IMT more easily, leading to a lower threshold voltage. This paper provided the promise for improving the thermal stability of selected devices. [ABSTRACT FROM AUTHOR]

In this paper, a switchless dual-band, dual-mode power amplifier (PA) has been developed for multioctave operation. For the switchless dual-band operation, we proposed a new coupled-line-based diplexer structure. The proposed diplexer operates as a balun at high-band frequencies and the coupled line at low-band frequencies. To better understand the proposed diplexer structure, a detailed analysis is performed based on a coupled-line theory. The interstage and output-stage matching networks of the PA are designed by using the proposed diplexer. To maximize the power-added efficiency (PAE) of the designed PA, turn off the unused band PAs and decide the optimum off-state bias condition of transistors. The designed dual-band, dual-mode PA is fabricated with commercial 0.25- $\mu \text{m}$ GaN HEMT process. The fabricated PA shows over 15-dB small-signal gain at 5–11 GHz in the low-band mode and 9–18 GHz in the high-band mode. The measured average output power and PAE are 35 dBm, 23% in the low-band mode and 37 dBm, 26% in the high-band mode. [ABSTRACT FROM AUTHOR]

In this paper, a multiobjective-based congestion management (CM) methodology is proposed using the optimal transmission switching (OTS) strategies considering the minimization of the total operating cost and the maximization of probabilistic reliability as two conflicting objectives. To improve the efficiency of the transmission network, this paper considers the possibility of changing the topology of the transmission system using the transmission switching strategy. The OTS can increase the economic efficiency of power dispatch with the existing infrastructure. The objective of OTS is to find the most influential lines as candidate lines for the disconnection. System operators can change the network topology to increase the transfer capacity, to improve voltage profiles, and also to improve the reliability of the power system. In this paper, the loss of load probability reliability index is used to indicate the probability that an electrical power system is not able to serve the prescribed load within the concerned period of time. Here, the transmission lines that should be switched are determined by using the security-constrained ac optimal power flow. The proposed optimization problem is solved using the hybrid of evolutionary and stochastic programming approaches. The output of the proposed OTS is to find the transmission lines that have to be switched so that the congestion in the system can be relieved. A multiobjective optimization approach is used to generate the Pareto optimal solutions. The suitability and effectiveness of the proposed CM approach have been examined on IEEE 30- and 300-bus test systems. [ABSTRACT FROM AUTHOR]

Soft-switching techniques of transformerless photovoltaic grid-connected inverters (TLIs) can significantly reduce switching losses, as well as soften switching processes. Conventional dc–ac soft-switching configurations proposed by Dr. Deepakraj M. Divan are invalid in TLIs because of the leakage current problem. In order to develop soft-switching techniques in TLIs, this paper proposes a new soft-switching configuration and a procedure to guide the invention of soft-switching TLIs. First, this paper proposes two basic resonance tanks related to dc bus polarities, and then, uses these basic tanks to elevate four popular full-bridge-type TLIs according to the proposed guideline. As a result, four soft-switching TLIs are gained. Second, this paper picks obtained soft-switching highly efficient and reliable inverter concept (HERIC) as example to analyze its soft-switching operation principle and performance. As a consequence, all active switches of the gained soft-switching HERIC circuit are switched under both of zero-current turn-on and turn-off conditions; the reverse recovery problem of freewheeling diodes is alleviated owing to the zero-current turn-off of diodes; meanwhile, the common-mode voltage at the switching frequency scale is still constant. Finally, some experimental results from a 3-kW universal prototype at 50-kHz switching frequency are provided to verify the effectiveness of the main contributions of this paper. [ABSTRACT FROM AUTHOR]

An area-efficient pulsewidth modulation (PWM)-residual-aliasing reduction technique is proposed for Class-D audio amplifiers by utilizing a low-complexity feed-forward path to cancel the PWM high-frequency components inside the feedback loop. The proposed technique reduces the PWM-residual-aliasing distortion without increasing the required switching frequency or power-hungry controller circuits, thereby lowering both the quiescent current and total harmonic distortion plus noise (THD+N) in Class-D audio amplifiers. Measurement results show that the proposed technique improves the THD+N of second-order Class-D amplifiers by 16.2 dB with a 1-kHz input; in addition, the Class-D amplifier of this paper achieves a minimum THD+N of 0.0032% while operating at a 215-kHz switching frequency, resulting in a reduction in quiescent current of more than 33%. Compared with other state of the arts, this paper implemented in 0.5- $\mu \text{m}$ CMOS technology features a competitive THD+N while consuming the lowest quiescent current of 0.96 mA and occupying the smallest active area of 0.49 mm2. [ABSTRACT FROM AUTHOR]

This paper presents a multi-coupling wireless power transfer (WPT) system aimed at dealing with various charging requests simultaneously. The proposed WPT system is able to distribute the energy more reasonably based on the top priority principle applying a novel distribution algorithm. Besides, the proposed system has the ability to charge the load in both the constant current mode and constant voltage mode while detecting the state of charging without using the bidirectional wireless communication. Moreover, this paper also puts forward a current injection topology named capacitance buffer rather than the traditional capacitor array in order to alleviate the large demand of the capacitors with different values under different resonant frequencies. Both simulation and experimental results are provided to demonstrate the feasibility and the performance of the proposed system. [ABSTRACT FROM AUTHOR]

In this paper, interlaced magnetic recording (IMR) is generalized with a flexible inter-track interference cancellation (F-ITIC) scheme to enhance the overall areal density capability (ADC) by balancing and mitigating the mutual ITI between neighboring tracks. The IMR showed ADC gain by interlaced recording of aggressive bit density (BD) top and relaxed BD bottom tracks, where asynchronous ITI mitigation was applied to the bottom ones. On the other hand, IMR configuration can be generalized by the selective write width control, such that narrower relaxed BD top tracks are recorded over wider aggressive BD bottom tracks. In this generalized IMR (G-IMR), balanced ITI between interlaced tracks can provide ADC gain over legacy IMR (L-IMR) and customized F-ITIC for both tracks can further increase the gain. Note that the ITI processing scheme for G-IMR should be flexible in order to manage the ITI signals from high BD affecting low BD tracks, or vice versa. To evaluate the performance of G-IMR with the F-ITIC, numerical evaluations are conducted with the micro-pixelated magnetic channel model. The results show that G-IMR provides a favorable tradeoff between both tracks’ BDs and track density associated mutual ITIs, which offers a tangible ADC gain with the ITI cancellation over the L-IMR. [ABSTRACT FROM AUTHOR]

Ultrahigh-speed magnetization switching mechanism is strongly pursued, as it can improve the write performance of the magnetic random access memory (MRAM) and further extend the application area of spintronics. Currently, a well-studied switching mechanism is the spin transfer torque (STT), whose speed, however, is limited by an intrinsic incubation delay. Recently, spin–orbit torque (SOT) was proposed to solve the speed bottleneck of the STT. In this paper, we evaluate the potential of two types of SOT-MRAMs, whose data can be ultrafast written based on the recently discovered field-free SOT mechanisms, respectively. A cross-layer analysis is presented involving device modeling, circuit-level optimization, and architecture-level evaluation. First, the principle of the magnetization switching is analyzed with the macrospin simulation. Then, the optimization strategies at the circuit level are generalized through the SPICE-type simulation. Finally, we build up the memory architecture with the SOT-MRAMs, STT-MRAM, and static RAM. Their read/write performances are evaluated with NVSim software. It is demonstrated that one of the studied SOT-MRAMs shows the promising prospect in the non-volatile memory, especially suitable for high-capacity cache. [ABSTRACT FROM AUTHOR]

Impedance translation using passive N-path mixers has been used to achieve local oscillator (LO)-defined series bandstop and shunt bandpass filtering. In this paper, we generalize N-path filtering using a correlator-based approach and propose N-path passive mixers driven by orthogonal sequences. Such sequence-driven N-path filters can potentially reject or select signals based on their properties in the spectral, spatial, and code domains. Specifically, a Walsh-function (WF) sequence (WF-seq)-based N-path shunt filter is implemented, demonstrating the feasibility of shunt bandstop filtering using LO sequences other than nonoverlapping pulses. The WF-seq approach enables reconfigurable concurrent filtering at two different frequencies with shunt operation avoiding penalties due to the switch drive overlap. A 65-nm CMOS implementation achieves 20-dB rejection at one frequency and 14-dB rejection concurrently at two frequencies between 0.3 and 1.4 GHz. The reconfigurable bandstop filter is implemented using analog gyrators and consumes 35–62.5 mW and achieves 2.9-dB noise figure and −2.5–5-dBm IIP3. [ABSTRACT FROM AUTHOR]

This paper presents nonlinear optimization-based position and speed estimation scheme for IPMSM drives with arbitrary signal injection generated by inherent switching ripples associated with finite control set model predictive control (FCSMPC). The existing standard sensorless techniques are not suitable for FCSMPC which applies voltage vectors directly to an electrical machine without a modulator. The proposed method optimizes the nonlinear cost function derived from the standard IPMSM model with respect to position and speed at every sampling interval. This method can be applied to any type of signal injection and, hence, an ideal candidate for sensorless FCSMPC. In this method, the signal injection is needed only to generate persistent excitation to maintain the observability at low speeds. A strong persistent excitation is always present with FCSMPC except at standstill where the control applies null vector when the reference currents are zero. This situation is overcome in this paper by introducing a small negative $d$ -axis current at standstill. Thus, the proposed method can estimate the position and speed over a wide speed range starting from standstill to the rated speed without a changeover or additional signal injection. This paper also presents detailed convergence analysis and proposes a compensator for standstill operation that prevents converging to saddle and symmetrical solutions, and therefore, also eliminates the well-known ambiguity of $\pi$ rad in position estimation. The performance of the proposed sensorless scheme is experimentally verified for a wide range of operating conditions. [ABSTRACT FROM AUTHOR]

This paper presents low-power circuit techniques for comparators and controllers to reduce increasing power loss of an active diode with offset/delay calibration in a 13.56-MHz CMOS active rectifier. Unlike a conventional switched-offset comparator, the proposed voltage-mode switched-offset comparator reuses its bias current to generate continuously adjustable offset voltage, thereby reducing power loss. Offset calibration for accurate switching is adopted to improve power conversion efficiency (PCE) and voltage conversion ratio (VCR). The proposed switch controller for offset calibration uses dynamic logic circuits and reduces power overhead that NOR-based set-reset latches and edge detectors of conventional switch controllers cause. Under 200- ${\Omega }$ loading and 5-V output, the proposed comparator and controller reduce power consumption by up to 73% and 24% in simulations compared with the conventional comparator and controller, respectively. This paper is implemented with 5-V devices of a 0.35- ${\mu }\mathrm {m}$ CMOS process to support high voltage. A peak PCE of 89.0%, a peak VCR of 90.1%, and a maximum output power of 126.7 mW are measured for 200- ${\Omega }$ loading. [ABSTRACT FROM AUTHOR]

In-memory computing architecture is an emerging revolutionary computing paradigm that can break the von Neumann bottleneck. Computing methodology and circuit codesign using the CMOS compatible 1T1R resistive random access memory (RRAM) integration structure is presented in this paper. Functionally complete Boolean logic and arithmetic functions are experimentally demonstrated. With a single 40-nm CMOS process 1T1R unit, each of the 16 binary logics can be realized in two logic steps with an additional readout step for cascading, which shows functional reconfiguration and low computational complexity. Up to 107 cycles of NAND and XOR logic operations are performed to validate the correctness and reliability. Moreover, several fundamental adder circuits are designed and experimentally demonstrated in 1T1R devices as the proof of concept of the 1T1R computing architecture. The adders proposed in this paper include a ripple-carry adder and its optimized design and a carry-select adder, which all show promising advantages in nonvolatility, computation speed, and circuit area. This paper reports the most complex yet efficient RRAM-based 8-bit addition function experimentally so far and lays a solid foundation for constructing the future in-memory computing architecture. [ABSTRACT FROM AUTHOR]

The introduction of metal nanocrystals (NCs) has been confirmed to improve electrical uniformity of oxide-based resistive random access memory (RRAM) devices significantly; however, the current reports do not systematically elucidate the relationship between the size/distribution of NCs and the electrical uniformity of RRAM devices. In this paper, we focused on the impact of metal NCs size and areal density on the resistive switching (RS) performances of oxide RRAM by atomic layer deposition (ALD) based on the experimental results and theoretical calculation. The dependence of ALD cycles of 50–130 during Pt or CoPtx NCs growth on the RS parameters of Al2O3 or HfO2 memory units has been evaluated systematically. The RRAM embedded Pt or CoPtx NCs shows the trends: with increasing ALD cycles, the forming voltage, set/reset voltage, the resistance in off and on state, and ${R}_{ \mathrm{\scriptscriptstyle OFF}}/{R}_{ \mathrm{\scriptscriptstyle ON}}$ ratio entirely first decrease, then flatten, and increase later with a minimum value at about 100 cycles. Although all metal NCs with various sizes enhance the electric field strength compared to at the planar region, only metal NCs with proper NCs size and areal density (9 nm/6– $10\times 10^{\textsf {11}}$ /cm2 in this paper) can effectively produce stronger localized electric field at the tip of metal NCs, leading to optimal RS behavior. [ABSTRACT FROM AUTHOR]

When developing silicon carbide (SiC) devices, the reliability of the internal body diode is an important issue. Stacking faults (SFs) are expanded from basal plane defects by using a body diode. Although it is well known that ON-voltage degradation occurs due to SFs, their effects on dynamic reliability have not been studied well. Furthermore, including the effects of SFs, there are not many reports about the dynamic reliability of SiC-MOSFETs. In this paper, a double-pulse switching test using 3.3-kV SiC-MOSFETs was carried out to clarify the failure mechanism of the switching operation of SiC-MOSFETs and effects of SFs on the safe operation area (SOA). Before the switching test, current stress was applied to the body diode of the devices under test (DUTs) to expand the SFs. The circuit configuration was half-bridge type, and a double-pulse gate signal was applied to the lower arm DUT. The switching voltage was 1.8 kV, and the switching current increased at about 8-A steps to failure. As a result, reverse recovery SOA (RRSOA) reliability decreased depending on the amount of SFs in the SiC-MOSFET. Because RRSOA failure was caused by avalanche due to the hole concentration during reverse recovery and the SFs raised local current density, reverse bias SOA (RBSOA) hardly decreased even if SFs containing SiC-MOSFETs were used. This is because RBSOA failure was caused by degradation of the gate isolation layer due to overheating and the temperature coefficient of the SFs electric resistance indicated negative. [ABSTRACT FROM AUTHOR]

This paper presents a comparison of switching performances between the in-situ oxide, gallium nitride (GaN) interlayer FET (OG-FET) and the conventional GaN metal–oxide–semiconductor FET (MOSFET), and explores the influence of the channel electron mobility on the device switching performance. GaN OG-FET is a novel structure with a pristine GaN layer grown between the gate oxide and the p-GaN enhancing the channel mobility up to 185 cm2/ $\text {V}\cdot \text {s}$ , which is over $3{\times}$ larger than that of the typical reported value (50 cm2/ $\text {V}\cdot \text {s}$) in GaN MOSFET. Owing to the high channel electron mobility, the GaN OG-FET showed a switching loss 30% lower than that of the conventional GaN trench MOSFET. Our results indicate that GaN OG-FET has the potential to attain greater efficiency, particularly at higher frequencies, showing a possible patch toward megahertz range conversions. [ABSTRACT FROM AUTHOR]

This paper deals with the issue of adaptive observer-based stabilization for a more general class of uncertain switched stochastic nonlower triangular nonlinear systems with average dwell-time (ADT) switching. The completely unknown nonlinear functions possessing the entire states are handled using the neural networks universal approximation property and the variable separation technique. The main novelty of this paper is that it presents a universal formula for constructing an adaptive output-feedback controller of the considered system with only one adaptive parameter by designing a switched state observer. The theoretical analysis shows that the Lyapunov stability of the overall closed-loop system is ensured in the presence of ADT switching. Finally, the effectiveness and practicability of the obtained design scheme are illustrated by two simulation examples. [ABSTRACT FROM AUTHOR]

This paper investigates the performance of switch-mode power supplies used in desktop PCs (PC-SMPS’) across the entire range of operating powers. Experimental results show that at low to medium operating powers, the input ac current might lose its periodicity with supply voltage frequency, when PCS-MPS’ can be an unexpected source of interharmonics and dc component. In such cases, there is a significant increase of PC-SMPS’ current waveform distortion and a substantial decrease of efficiency and operational power factors, which requires application of appropriate measurement and calculation procedures during the analysis. To correctly assess these power-dependent changes in performance and power quality indicators, this paper introduces a novel testing and evaluation methodology, based on the known or assumed PC-SMPS operating cycle. [ABSTRACT FROM AUTHOR]

This paper discusses dynamic behavior of a dual-active-bridge (DAB) dc–dc converter. Conventional phase-shift control methods for the DAB converter may cause dc offsets in both inductor current and transformer magnetizing current in transient states. The dc offset in the inductor current would introduce an excessive peak current through the switching devices. The dc offset in the magnetizing current may induce magnetic-flux saturation. Conventional methods simultaneously turn on and off the diagonal switches in each H-bridge converter and produce a square-wave voltage with a 50% duty ratio. In contrast, the proposed method in this paper independently controls each switch to modify the duty ratio in transient states. This paper clearly derives the requirements of each switch to eliminate the dc offsets in both currents with a settling time shorter than half the switching period. Experimental results using a 5-kW 20-kHz system verify the validity of the proposed control method, which is effective not only in a single step change, but also in a continuous change in the phase-shift reference. [ABSTRACT FROM AUTHOR]

This paper presents two novel measurement methods to characterize silicon carbide (SiC) MOSFET devices. The resulting data are utilized to significantly improve the extraction of a custom device model that can now accurately reproduce device switching behavior. First, we consider the $I_{\text{d}}- V_{\text{ds}}$ output characteristics of power devices such as SiC transistors. These are typically measured using traditional curve tracers, but the characterization of the high-voltage and high-current (HVHC) region is very challenging because of device power compliance and self-heating. In this paper, we introduce a measurement technique that overcomes self-heating and derives the HVHC region from switching waveforms. The switching transient characteristics of devices are used to determine drain current $(I_{\text{d}})$ as a function of drain–source voltage $(V_{\text{ds}})$ in the HVHC range. Second, we consider another challenging characterization area: measurement of nonlinear capacitances when device is turned on. These capacitance characteristics of on-state devices are important for correcting disagreements between simulations and measurements in turn-off switching transient waveforms and cannot be measured using a conventional capacitance-voltage meter. We introduce S-parameter measurements as an effective method to obtain the capacitance characteristics of both off-state devices and on-state devices. These novel measurement techniques have been applied to the modeling of a SiC device. The extracted device model, a modified version of the popular Angelov−GaN high-electron-mobility transistor model, shows significant improvement in terms of the accuracy of switching waveforms of devices over a wide range of operating conditions. [ABSTRACT FROM AUTHOR]

The pump-back test is widely adopted in the industry for characterizing and qualifying high-power converters. One popular pump-back test configuration is to tie the dc links of two converters together and circulate the current through the inductor connected between the ac terminals. In this configuration, one of the converters operates in the voltage mode to generate the virtual grid and the other converter regulates the circulating current, where hysteresis control could be applied. However, the switching characteristics of hysteresis control are unique due to the pulsewidth modulation type voltage being the virtual grid. This paper contributes to analyzing the switching frequency characteristics of the hysteresis control in this pump-back test configuration. The switching frequency tracking phenomenon is revealed and reported in this paper for the first time. Theoretical analysis, simulation validation, and experimental demonstration are provided to support the major conclusions. [ABSTRACT FROM AUTHOR]

The switching properties of Te and TeTiW top electrodes (TEs) on TiW/SiN/TiN resistive switching memory devices are explored in this paper. The TeTiW TE device exhibits more favorable bipolar resistive switching behavior because of the decrease in binding energy after its use. This finding is confirmed through X-ray photoelectron spectroscopy analyses. The filament of the TeTiW TE device is metal like after forming, and the reset process corresponds with the thermal-dissolution mechanism. A physical model based on a Te filament is constructed to explain such phenomena. The TeTiW TE device provides the excellent endurance of more than 104 cycles, with an ON/OFF ratio of 500. The improvement can be attributed to the filament’s robustness during the forming and set processes, which prevent its diffusion even at high temperature. The device also features long retention for up to 104 s at 225 °C without stress, and 104 s at 85 °C with stress of −0.3 V. Therefore, it has high potential for high-density nonvolatile memory applications. [ABSTRACT FROM AUTHOR]

In this paper, we demonstrate the linear conductance-change characteristics of a conductive-bridging RAM (CBRAM) to be employed as an artificial synapse device in neuromorphic systems. The CBRAM with a bilayer electrolyte structure (${\mathrm {Cu/Cu}}_{{2}-{x}}\text{S}$ / $\mathrm {WO}_{{3}-{x}}$ /W) exhibits analog switching behavior during the depression process due to the well-controlled dissolution of the conductive filament. To analyze the origin of this motion, we investigate the effective voltage applied to $\mathrm {Cu}_{{2}-{x}}\text{S}$ and $\mathrm {WO}_{{3}-{x}}$. Our findings reveal that $\mathrm {Cu}_{{2}-{x}}\text{S}$ , acting as a voltage divider, helps in suppressing the large voltage drop in $\mathrm {WO}_{{3}-{x}}$ , where the formation/dissolution of filament occurs. Furthermore, due to the diode-like characteristics of $\mathrm {Cu}_{{2}-{x}}\text{S}$ and the division of voltage drop between $\mathrm {WO}_{{3}-{x}}$ and $\mathrm {Cu}_{{2}-{x}}\text{S}$ , an optimum programming energy is applied to $\mathrm {WO}_{{3}-{x}}$ during the depression process. This leads to linear conductance-change characteristics under identical pulses. However, abrupt conductance-change characteristics are observed during the potentiation process. Thus, we use only the device characteristics of the depression part for the neuromorphic system. An excellent classification accuracy is achieved due to the linear conductance-change characteristics and optimized pulse conditions. [ABSTRACT FROM AUTHOR]

As a power system operating point alters its position due to variations in power injections, its small-signal stability margin (SSSM) may decrease. Under this situation, a network topology change via line switching can increase the SSSM. In this paper, an online line switching method for maximizing the SSSM is presented, taking into account both the solution quality and the required computational speed. To balance the tradeoff between speed and solution quality, the line switching method presented in this paper is composed of three stages: 1) screening; 2) ranking; and 3) detailed evaluation. The effectiveness of the presented three-stage method is evaluated on IEEE standard power systems with promising results. [ABSTRACT FROM AUTHOR]

This paper presents the work carried out by the IEEE Working Grou[ on field-measured overvoltages and their analysis for validating power system component models to be used in switching transients studies. The work uses measurement data obtained from field tests performed by Bonneville Power Administration in June 1995 where switching overvoltages were measured on one of its 230 kV lines. This paper includes a description of the switching tests and the main results derived from field measurements. Details of the switching procedures that were followed to calibrate component models used to match field-recorded waveforms can be found in the Part II paper. [ABSTRACT FROM AUTHOR]

In this paper, the conventional I- and T-type three-level neutral-point-clamped (3L-NPC) inverter for low-voltage renewable energy systems is first investigated. Literature research shows that the T-type inverter improves I-type's insulated-gate bipolar transistor (IGBT) $+$ IGBT current paths. However, the IGBT $+$ diode paths are the same. The calculation in this paper further reveals that the IGBT $+$ diode current paths dominate the conduction losses and even the whole semiconductor losses. Based on the aforementioned recognitions, a novel T-type inverter is presented as an alternative to be applied in the low-voltage renewable energy systems. In the proposed 3L-NPC, four CoolMosfets replace the IGBT $+$ diode middle bidirectional switch. In the proposed topology, there is no diode involved in the current path supposing the unity power factor. In this way, the conduction loss is expected to be reduced compared with that from the conventional T-type 3L-NPC, particularly in the low and medium power ranges. [ABSTRACT FROM PUBLISHER]

In the rapidly growing field of electrified transportation technology, hybrid electric and electric vehicle (HEV/EV) manufacturers have been placing increasing demands on the designers to improve the efficiency and reduce the costs of vehicle components to sustain a niche in the EV market. To understand the significance and challenges in an efficient and economical drivetrain design, this paper presents a part of an ongoing project that aims at developing a comprehensive study on dc/ac drive motor technology in EV applications. In this paper, a new three-level three-phase matrix converter topology, along with two conventional frequently used three-level three-phase dc/ac converter topologies, namely, diode-clamped and H-bridge converters, are implemented. Furthermore, comprehensive analysis and comparative studies are conducted to examine the performance and efficiency of these converter topologies according to EV design criteria. In addition, experimental investigations are carried out on the aforementioned converter configurations to help EV designers choose the most suitable converter topology. [ABSTRACT FROM PUBLISHER]

Studies have been taken into the breakdown voltage jitter of corona-stabilized switch at high repetition rate up to several kHz. It is thought that the gas recovery affect the jitter of breakdown voltage directly at high repetition rate, because the gas switch will breakdown at a low voltage if the gas cannot fully recover. The breakdown voltage jitter is called voltage jitter in the following paper. However, based on the experimental results, the voltage jitter still exists at low repetition rate, even at single-shot mode. This is not explained by the previous studies. In this paper, voltage jitter below 100 Hz of a corona-stabilized switch is investigated experimentally. A corona-stabilized switch is introduced, using a cylindrical electrode as the cathode and a plane electrode as the anode. The gas used between the electrodes is SF6. A negative pulse with a maximum width of 30~\mu \texts is used to charge this switch. The tested factors include gas pressure, gap space, repetition rate, and switch geometry. Experimental results show that voltage jitter is mainly affected by the gas pressure and switch geometry. It is seen that voltage jitter decreases as gas pressure increases and a suitable cathode geometry presents a low voltage jitter. Critical volume is a region close to the highly stressed electrode, where the presence of an electron will lead to an electron avalanche which attains a critical size and hence leads to a stabilizing corona. Critical volume is introduced to explain the experimental results. It is found that less voltage jitter can be achieved with a smaller and more concentrated critical volume, as well as efficient corona stabilization. The results indicate that voltage jitter may be reduced by optimize the critical volume at low repetition rate. [ABSTRACT FROM PUBLISHER]

This paper investigates the potential improvement in signal reliability for outdoor wearable communications channels operating at 868 MHz using switched combining based macro-diversity. In this paper, a number of different macro-diversity configurations consisting of two and four base stations were considered to help mitigate the impact of body shadowing upon a wearable node, which was located on the central chest region of an adult male. During the field measurements, five different walking movements were performed, and then analyzed to investigate the efficacy of using macro-diversity. It was found that all of the considered switched combining schemes, including switch-and-stay combining, switch-and-examine combining (SEC) and SEC with post-examining selection (SECps) provided a worthwhile signal improvement when an appropriate switching threshold was adopted. The maximum diversity gain obtained in this paper was found to be 19.5 dB when using four-base station SECps. The diversity gain, the number of path examinations, and the number of path switches between base stations for the switched combiner output varied according to the determined switching threshold, highlighting the importance of the selection of an appropriate threshold level. Furthermore, the performance/complexity tradeoff is demonstrated. Finally, the fading behavior at the output of the switched diversity combiners was then characterized using the diversity specific equations developed under the assumption of independent and non-identically distributed Nakagami- $m$ fading channels. Over all of the measurement scenarios considered in this paper, the theoretical models provided an adequate fit to the fading observed at the output of the virtual switched combiner. [ABSTRACT FROM PUBLISHER]

This paper proposes a novel open-winding brushless doubly-fed reluctance generator (OW-BDFRG) with dual two-level converters in order to reduce the converter rating and switching frequency for large-scale wind turbine applications. The new converter topology is equivalent to a three-level converter directly connected to the control winding of typical BDFRG. The OW-BDFRG system with this topology structure requires lower converter rating and switching frequency, and has a more flexible control mode, better operation performance, and fault redundancy capability. For the OW-BDFRG, this paper also proposes a new control scheme combining direct power control (DPC) with sliding mode variable structure (SMVS) control to implement the power tracking. The voltage-vector switching table of DPC is redesigned according to the error signals of active and reactive powers of the power winding, as well as the sector location of control winding flux. The active and reactive powers of the OW-BDFRG can be directly decoupled and independently controlled by properly selecting the switching voltage vectors. The novelty of this paper lies in an OW-BDFRG topology driven by dual two-level converters to improve the system characteristics, and the use of SMVS control to improve the DPC accuracy and robustness to parameter variations. Finally, the effectiveness of the proposed system is verified through simulation and experimental studies. [ABSTRACT FROM AUTHOR]

Time-division duplex (TDD) systems rely on off-chip transmit/receive (T/R) switches to isolate the RX from the high-output power of the TX, while existing on-chip T/R switching solutions are narrow-band or high loss. This paper presents a wideband integrated T/R switching technique that eliminates the conventional, lossy series T/R switch from the signal path. The system reconfigures the PA as an LNA during the receive mode, and utilizes only DC mode control switches to enable TDD co-existence. To demonstrate this technique, a polar transmitter that can be re-purposed into a common-gate LNA is implemented in 65-nm CMOS. With an integrated front-end balun transformer, the transmitter achieves 20-dBm peak output power with 32.7% peak drain efficiency. In the receive mode, the PA is reconfigured into a wideband 3.4–5.4-GHz LNA achieving −6.7-dBm P1dB, and 5.1-dB noise figure. [ABSTRACT FROM AUTHOR]

This paper presents a 16-core voltage-stacked system with adaptive frequency clocking (AFClk) and a fully integrated voltage regulator that demonstrates efficient on-chip power delivery for multicore systems. Voltage stacking alleviates power delivery inefficiencies due to off-chip parasitics but adds complexity to combat internal voltage noise. To address the corresponding issue of internal voltage noise, the system utilizes an AFClk scheme with an efficient switched-capacitor dc–dc converter to mitigate noise on the stack layers and to improve system performance and efficiency. Experimental results demonstrate robust voltage noise mitigation as well as the potential of voltage stacking as a highly efficient power delivery scheme. This paper also illustrates that augmenting the hardware techniques with intelligent workload allocation that exploits the inherent properties of voltage stacking can preemptively reduce the interlayer activity mismatch and improve system efficiency. [ABSTRACT FROM PUBLISHER]

A self-biased CMOS analog mixer for ultra-wideband (UWB) applications is presented in this paper. The proposed mixer is complementary and self-biased, and has lower power consumption, superior isolation, and larger bandwidth. The proposed low-power, down conversion mixer is designed and fabricated in UMC 0.18\mu \textm CMOS technology. The measurement results show that it can operate at UWB frequencies that range from 1 to 6 GHz. The proposed mixer provides a maximum conversion gain of 13 dB, −4.5 dBm of third-order input intercept point, and a minimum double sideband noise figure of 12 dB. The maximum values of the measured local oscillator LO-to-RF, RF-to-IF, and LO-to-IF isolations are 50, 45, and 52 dB, respectively. [ABSTRACT FROM PUBLISHER]

This paper proposes an input voltage sensorless control algorithm for three-phase active boost rectifiers. Using this approach, the input ac-phase voltages can be accurately estimated from the fluctuations of other measured state variables and preceding switching state information from converter dynamics. Furthermore, the proposed control strategy reduces the input current harmonics of an ac–dc three-phase boost power factor correction (PFC) converter by injecting an additional common-mode duty ratio term to the feedback controllers’ outputs. This additional duty compensation term cancels the unwanted input harmonics, caused by the floating potential between ac source neutral and dc link negative, without requiring any access to the neutral point. A 6-kW (continuous power)/10-kW (peak power) three-phase boost PFC prototype using SiC-based semiconductor switching devices is designed and developed to validate the proposed control algorithm. The experimental results show that an input power factor of 0.999 with a conversion efficiency of 98.3%, total harmonic distortion as low as 4%, and a tightly regulated dc-link voltage with 1% ripple can be achieved. [ABSTRACT FROM PUBLISHER]

The IEC 61499 standard provides means to specify distributed control systems in terms of function blocks. For the deployment, each device may hold one or many logical resources, each consisting of a function block network with service interface blocks at the edges. The execution model is event driven (asynchronous), where triggering events may be associated with data (and seen as messages). In this paper, we propose a low-complexity implementation technique allowing to assess end-to-end response times of event chains spanning over a set of networked devices. Based on a translation of IEC 61499 to RTFM11

Real-time for the masses. [ABSTRACT FROM PUBLISHER]