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This research aimed to develop best-practice recommendations for identifying the "standard of care" (SoC) and integrate it when it is the comparator in diagnostic economic models (SoC comparator). A multi-methods approach comprising 2 pragmatic literature reviews and 9 expert interviews was used. Experts rated their agreement with draft recommendations based on the authors' analysis of the reviews. These were refined iteratively to produce final recommendations. Fourteen best-practice recommendations are provided. Care pathway mapping (using quantitative, qualitative, or mixed-methods approaches) should be used for identifying the SoC comparator. Guidelines analysis can be integrated with expert opinion to identify pathway variability and discrepancies from clinical practice. For integrating the SoC comparator into the model, recommendations around structure, input sourcing, data aggregation and reporting, input uncertainty, and model variability are presented. For example, modelers should consider that the reference standard is not synonymous with the SoC, and the SoC may not be the only comparator. The comparator limitations should be discussed with clinical experts, but elicitation of its diagnostic accuracy is not recommended. Probabilistic sensitivity analysis is recommended when evaluating the overall input uncertainty, and deterministic sensitivity analysis is useful when there is high model uncertainty or SoC variability. Consensus could not be reached for some topics (eg, the role of real-world data, model averaging, and alternative model structures), but the reported discussions provide points for consideration. To our knowledge, this is the first guidance to support modelers when identifying and operationalizing the SoC comparator in diagnostic cost-effectiveness models. • Modeling the cost-effectiveness requires a comparison of the new diagnostic and patient management strategy with a comparator, often a complex standard of care (SoC) pathway. The new diagnostic test can replace or, more commonly, be integrated with the diagnostic SoC pathway. This presents 2 main challenges in obtaining useful estimates of cost-effectiveness: (1) identifying the diagnostic SoC pathway to define the comparator and (2) integrating it into the model. • We identified possible methodological approaches through pragmatic literature reviews and expert interviews. Some examples are to identify the SoC comparator via mapping the care pathway through qualitative, quantitative, or mixed-methods approaches; to select data on the diagnostic accuracy of the SoC comparator from studies in which the reference standard is the one used for the new test and report detailed information of the data source; and to assess the impact of the SoC pathway variability through scenario analysis. • We provide 14 recommendations that can support modelers to minimize the risk of a misrepresentation of the incremental clinical utility of the new diagnostic test because of the uncertainty and variability of the SoC comparator. We identified practice recommendations, gaps in knowledge, and areas where further research would advance the field. [ABSTRACT FROM AUTHOR]

Digital health definitions are abundant, but often lack clarity and precision. We aimed to develop a minimum information framework to define patient-facing digital health interventions (DHIs) for outcomes research. Definitions of digital-health-related terms (DHTs) were systematically reviewed, followed by a content analysis using frameworks, including PICOTS (population, intervention, comparator, outcome, timing, and setting), Shannon-Weaver Model of Communication, Agency for Healthcare Research and Quality Measures, and the World Health Organization's Classification of Digital Health Interventions. Subsequently, we conducted an online Delphi study to establish a minimum information framework, which was pilot tested by 5 experts using hypothetical examples. After screening 2610 records and 545 full-text articles, we identified 101 unique definitions of 67 secondary DHTs in 76 articles, resulting in 95 different patterns of concepts among the definitions. World Health Organization system (84.5%), message (75.7%), intervention (58.3%), and technology (52.4%) were the most frequently covered concepts. For the Delphi survey, we invited 47 members of the ISPOR Digital Health Special Interest Group, 18 of whom became the Delphi panel. The first, second, and third survey rounds were completed by 18, 11, and 10 respondents, respectively. After consolidating results, the PICOTS-ComTeC acronym emerged, involving 9 domains (population, intervention, comparator, outcome, timing, setting, communication, technology, and context) and 32 optional subcategories. Patient-facing DHIs can be specified using PICOTS-ComTeC that facilitates identification of appropriate interventions and comparators for a given decision. PICOTS-ComTeC is a flexible and versatile tool, intended to assist authors in designing and reporting primary studies and evidence syntheses, yielding actionable results for clinicians and other decision makers. • Abundant, yet vaguely defined definitions in digital health represent a challenge for clinicians, decision makers, developers, and researchers. Despite having several guidelines/checklists for the standardization of evidence generation and assessment for digital health interventions (DHIs), the identification of comparable DHIs remains difficult because of their personalized nature, complex technologies, and linkages to larger systems. This may restrict the validity of evidence syntheses. • We introduce the PICOTS-ComTeC (population, intervention, comparator, outcome, timing, setting, communication, technology, and context) framework, a newly developed, flexible, and versatile tool to help the formulation of sufficiently specific and detailed definitions for patient-facing digital health interventions and related research questions. • To overcome the limitations of terminology in digital health, the PICOTS-ComTeC framework of patient-facing DHIs should be specified in sufficient detail, to allow the identification of comparable interventions and allow for the selection of appropriate comparators that deliver similar effects to patients; therefore, the fit of DHIs in clinical, financing or development decision contexts, and specific research questions can be assessed. [ABSTRACT FROM AUTHOR]

Malaria transmission-blocking vaccines target mosquito-stage parasites and will support elimination programmes. Gamete vaccine Pfs230D1-EPA/Alhydrogel induced superior activity to zygote vaccine Pfs25-EPA/Alhydrogel in malaria-naive US adults. Here, we compared these vaccines in malaria-experienced Malians. We did a pilot safety study then double-blind, block-randomised, comparator-controlled main-phase trial in malaria-intense Bancoumana, Mali. 18–50-year-old healthy non-pregnant, non-breastfeeding consenting adult residents were randomly assigned (1:1:1:1) to receive four doses at months 0, 1, 4·5, and 16·5 of either 47 μg Pfs25, 40 μg Pfs230D1 or comparator (Twinrix or Menactra)—all co-administered with normal saline for blinding—or 47 μg Pfs25 plus 40 μg Pfs230D1 co-administered. We documented safety and tolerability (primary endpoint in the as-treated populations) and immunogenicity (secondary endpoint in the as-treated populations: ELISA, standard-membrane-feeding assay, and mosquito direct skin feed assay). This trial is registered at ClinicalTrials.gov , NCT02334462. Between March 19, and June 2, 2015, we screened 471 individuals. Of 225 enrolled for the pilot and main cohorts, we randomly assigned 25 participants to pilot safety cohort groups of five (20%) to receive a two-dose series of Pfs25-EPA/Alhydrogel (16 μg), Pfs230D1-EPA/Alhydrogel (15 μg) or comparator, followed by Pfs25-EPA/Alhydrogel (16 μg) plus Pfs230D1-EPA/Alhydrogel (15 μg) or comparator plus saline. For the main cohort, we enrolled 200 participants between May 11 and June 2, 2015, to receive a four-dose series of 47 μg Pfs25-EPA/Alhydrogel plus saline (n=50 [25%]; Pfs25), 40 μg Pfs230D1-EPA/Alhydrogel plus saline (n=49 [25%]; Pfs230D1), 47 μg Pfs25-EPA/Alhydrogel plus 40 μg Pfs230D1-EPA/Alhydrogel (n=50 [25%]; Pfs25 plus Pfs230D1), or comparator (Twinrix or Menactra) plus saline (n=51 [25%]). Vaccinations were well tolerated in the pilot safety and main phases. Most vaccinees became seropositive after two Pfs230D1 or three Pfs25 doses; peak titres increased with each dose thereafter (Pfs230D1 geometric mean: 77·8 [95% CI 56·9–106·3], 146·4 [108·3–198·0], and 410·2 [301·6–558·0]; Pfs25 geometric mean 177·7 [130·3–242·4] and 315·7 [209·9–474·6]). Functional activity (mean peak transmission-reducing activity) appeared for Pfs230D1 (74·5% [66·6–82·5]) and Pfs25 plus Pfs230D1 (68·6% [57·3–79·8]), after the third dose and after the fourth dose (88·9% [81·7–96·2] for Pfs230D1 and 85·0% [78·4–91·5] Pfs25 plus Pfs230D1) but not for Pfs25 (58·2% [49·1–67·3] after the third dose and 58·2% [48·5–67·9] after the fourth dose). Pfs230D1 transmission-reducing activity (73·7% [64·1–83·3]) persisted 10 weeks after the fourth dose. Transmission-reducing activity of 80% was estimated at 1659 ELISA units for Pfs25, 218 for Pfs230D1, and 223 for Pfs230D1 plus Pfs25. After 3850 direct skin feed assays, 35 participants (12 Pfs25, eight Pfs230D1, five Pfs25 plus Pfs230D1, and ten comparator) had transmitted parasites at least once. The proportion of positive assays in vaccine groups (Pfs25 33 [3%] of 982 [–0·013 to 0·014], Pfs230D1 22 [2%] of 954 [–0·005 to 0·027], and combination 11 [1%] of 940 [–0·024 to 0·002]) did not differ from that of the comparator (22 [2%] of 974), nor did Pfs230D1 and combination groups differ (–0·024 to 0·001). Pfs230D1 but not Pfs25 vaccine induces durable serum functional activity in Malian adults. Direct skin feed assays detect parasite transmission to mosquitoes but increased event rates are needed to assess vaccine effectiveness. Intramural Research Program of the National Institute of Allergy and Infectious Diseases and US National Institutes of Health. [ABSTRACT FROM AUTHOR]

In this research, a new architecture of dynamic latch comparator is presented, which is able to provide high-speed, consumes low-power and low offset voltage. The proposed comparator has been verified in a design, a 12-Bit SAR ADC(Successive Approximation Register Charge-Redistribution Analog-To-Digital Converter). The comparator consists of two stage pre-amplifier and a StrongLatch. The pre-amplifier adopts an inverter-based input pair and a pair of capacitances in output stage to reduce noise. It is shown by simulation and analysis that the offset voltage is significantly reduced compared to a conventional dynamic latched comparator. The proposed circuit is designed and simulated in 28 nm CMOS technology. The results show that, for the proposed comparator, the speed is 2.37 ns and consumes only 426.6 μ W power, at 1.8 V supply voltage and 330 MHz clock frequency. This article presents two kinds of FoM(Figure of Merit) to prove that the comparator has excellent performance. • Analysis of offset source of differential pairs. • Optimize comparator design. • Validate the comparator design. [ABSTRACT FROM AUTHOR]

• Willingness to enroll in clinical trials was assessed for those on CFTR modulators. • Willingness to enroll was associated with proposed trial length and comparator. • Shorter trials and active comparators were favored over alternatives. • Future studies in people on CFTR modulators will be feasible for some trial designs. To assess the feasibility of enrolling people with CF (pwCF) taking the CFTR modulator elexacaftor/tezacaftor/ivacaftor (ETI) in clinical trials of a new modulator. PwCF receiving ETI at CHEC-SC study (NCT03350828) enrollment were surveyed for interest in 2-week to 6-month placebo- (PC) and active-comparator (AC) modulator studies. Those taking inhaled antimicrobials (inhABX) were surveyed for interest in PC inhABX studies. Of 1791 respondents, 75% [95% CI 73, 77] would enroll in a 2-week PC modulator study versus 51% [49, 54] for a 6-month study; 82% [81, 84] and 63% [61, 65] would enroll in 2-week and 6 month AC studies; 77% [74, 80] of 551 taking inhABX would enroll in a 2-week PC inhABX study versus 59% [55, 63] for a 6-month study. Previous clinical trial experience increased willingness. Study designs will affect feasibility of future clinical trials of new modulators and inhABX in people receiving ETI. [ABSTRACT FROM AUTHOR]

As a result of increased interest in space applications, radiation-aware circuit design has become a major concern to guarantee the safe operation of electronic systems operating under extreme space conditions. As the first step, several ad-hoc simulation approaches have been developed in analog and digital domains to estimate the functional behavior of circuits exposed to high radiation. However, most of these tools are application specific and stand-alone (not integrated into the simulation tools). Also, several commercial CAD solutions exist; however, access to these tools is limited due to security measures. To this end, we have developed a well-equipped, SPICE-integrated, and free-to-access simulation tool, RadiSPICE, capable of running statistical radiation simulations and performing extended temperature and sensitivity analyses. By using RadiSPICE, one can readily predict the functional behavior of circuits after long-term or short-term radiation effects. Moreover, the sensitivity analysis reveals vulnerabilities of the design against radiation and provides valuable design hints to the designer to make circuits radiation-hardened. To demonstrate the proposed tool, we have performed several experiments on two analog building blocks with different topologies (bandgap reference and comparator circuits) using RadiSPICE and discussed the robustness of the designs in detail. • This article presents RadiSPICE, a SPICE-integrated, free-access simulation tool. • The tool is intended for radiation-aware circuit design, for space applications. • Statistical simulations for long- and short-term radiation effects are covered. • The sensitivity analysis tool provides radiation-aware circuit design insight. • The circuit functionality after long- and short-term effects is demonstrated. • Two analog blocks are simulated and investigated for robustness in detail. [ABSTRACT FROM AUTHOR]

In this paper, a modified successive-approximation-register analog-to-digital converter (SAR ADC) with a novel low power dynamic comparator at 0.2 V supply voltage is presented. The power consumption of SAR ADC has been reduced by 70% with design of proposed low-power comparator and using power reduction techniques such as power gating and reducing the supply voltage. Also, by custom design for unit capacitor in the SAR ADC, the area has been reduced by 46% compared to the conventional structure. The proposed ADC with a sampling frequency of 1 kS/s and power consumption of only 1.21 nW for biomedical applications has been designed and simulated in a TSMC 65 nm CMOS technology and occupies an area of 0.013 m m 2. The proposed biomedical ADC is verified using analog electroencephalogram (EEG) and electrocardiogram (ECG) inputs which demonstrate it is proper to quantize these biosignals. The figure-of-merit (FOM) of the proposed converter is 3.2 fJ/conversion-step. • Designing a modified ADC with an ultra low supply voltage (0.2 V) for biosignals acquisition. • Designing a novel 0.2 V, ultra low power dynamic comparator. • The power consumption of SAR ADC has been reduced by 70% with design of proposed low-power comparator and using power reduction techniques such as power gating and reducing the supply voltage. • 46% reduction of occupied area using custom capacitor design. [ABSTRACT FROM AUTHOR]

This paper presents a 16-bit 1-Msps successive-approximation-register analog-to-digital converter (ADC) with a split-ADC digital calibration scheme based on dynamic element matching. A multi-segment capacitor array with redundant bits is utilised for ensuring that missing-level errors are calibrated in the digital domain, reducing the area and power consumption. The key circuit modules are optimised, such as the low-power dual-mode cascade comparator and dynamic element matching control logic. The prototype is fabricated by a 0.18-μm CMOS technology, and it exhibits 170.47 dB figure of merit Schreier (FoMs), 15.04 bits effective number of bits (ENOB) and 119.50 dB spurs free dynamic range (SFDR). The peak differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.422/0.536 LSB and −0.721/0.758 LSB, respectively. • A 16-bit 1 Msps SAR ADC is manufactured in 0.18 μm CMOS process with 170.47 dB FoMs. • A split-ADC digital calibration scheme based on dynamic element matching can improve the SFDR effectively. • A segmented capacitor array of 4 sub-capacitor arrays decreases the total capacitance of the high-resolution SAR ADC. • A dual-mode automatic zero comparator is utilised to reduce power consumption. [ABSTRACT FROM AUTHOR]

Achieving low propagation delay in comparators under low input overdrive voltage is challenging. To overcome this difficulty, this paper presents a novel rail-to-rail high-speed comparator. By clamping the output node of the current summation circuit relative to a fixed level V C , the overdrive recovery time under large signal is successfully reduced. Moreover,by adopting a cascaded approach with multiple stages of high bandwidth and low gain,not only is the comparator's gain enhanced,but it also acquires higher bandwidth. Ultimately, the comparator's output is transmitted at high speed through an LVDS interface. This design is implemented using 0. 18 μ m SiGe BiCMOS technology. Simulation results show that the comparator has a static power consumption of 26.4 mW, and for 5 mV input overdrive, the average propagation delay is about 1.09 ns. • The input common-mode range is expanded to rail-to-rail. • The propagation delay under small input overdrive is greatly reduced. • The static power consumption of the comparator is 26.4 mW. • The comparator's output is transmitted at high speed through an LVDS interface. • The comparator is implemented using 0.18 μ m SiGe BiCMOS technology. [ABSTRACT FROM AUTHOR]

In this paper we study some fuzzy order in fuzzy sets based on t-norm fuzzy arithmetic. The definition of the order comes from the extension principle for interval order: a > b iff a − b > 0 and from measurement sciences. In measurement sciences the order is given by a comparator whose operation is based on empirical determination of the difference of two input signals. Fuzzy comparison based on fuzzy sets subtraction is considered as an extension of substraction operation, namely a fuzzy set B is greater than a fuzzy set A if B − A is greater than zero in fuzzy arithmetic. In the paper we show that this fuzzy order is irreflexive, transitive, asymmetric and compact, subhomothetic, Archimedean and semi-Ferrers. Our idea refers to the work of M. K. Urbański (Modeling the measurement in algebraic fuzzy structures, Warsaw 2003, in polish) and to the fundamental problems in the measurement theory. [ABSTRACT FROM AUTHOR]

We present a highly robust 12-bit, 100 kS/s Successive Approximation Register (SAR) Analog-to-Digital Converter (ADC) that excels in mitigating the effects of mismatch, temperature variations and process corners. A modified hybrid switching method is developed in design of the Capacitive Digital-to-Analog Converter (C-DAC) that saves 17 % of the DAC power consumption. Furthermore, we utilize a switched local feedback loop in the pre-amplifier circuit of the comparator that significantly minimizes the offset. Using this technique, the 3-sigma offset is reduced from 11.33 mV to 0.37 mV. Moreover, a high performance latched-based Bit Slice Unit (BSU) is proposed to preserve the successive codes during each conversion. Designed in 65 nm CMOS technology, the ADC operates in −55 °C to +125 °C temperature range, consuming only 1.55 μW with a 0.7V supply voltage and occupying a 0.6 mm2 area. [ABSTRACT FROM AUTHOR]

A dynamic comparator is the core element in high-speed, high-resolution analog-to-digital converters (ADCs) used for communication applications. The majority of the dynamic comparators can only operate at high speeds when the input difference voltage is large enough. Due to the limited pre-amplifier gain, the comparators' performance deteriorates at lower input difference voltages, which is not suitable for high-speed, high-resolution ADCs. A double-tail dynamic comparator with a pair of auxiliary inverters is proposed to alleviate this problem. With the proposed comparator, the pre-amplifier's differential gain is increased, and the latch regeneration time is reduced by the auxiliary inverter pair resulting in faster comparison operations. The proposed comparator is designed, simulated, and compared with the latest topologies in 65 nm CMOS technology. The performance metrics such as delay, kickback noise, energy consumption per bit, rms noise, and power delay product are evaluated and compared with the state-of-the-art architectures. The proposed technique can be applied to any dynamic comparator that has differential signals at the output of the pre-amplifier stage. Simulations show that the auxiliary inverter pair improves the comparator's speed by more than 10%. [ABSTRACT FROM AUTHOR]

This paper presents a low voltage energy-efficient 10-bit SAR ADC. A double-merge and split (DMAS) switching scheme is proposed to reduce the CDAC switching energy by 92.2 % compared with conventional one without extra reference voltage (V CM ). Gain tunable voltage-controlled delay unit (GT-VCDU) is proposed for offset calibration of time-domain comparator (TD-CMP). The residual offset is reduced by proposed stage-by-stage calibration. 1 sigma of TD-CMP offset is reduced to 0.8 mV. The SAR ADC is fabricated in the 55 nm CMOS process occupied a core area of 0.038 m m 2. With a supply voltage of 0.5 V and a Nyquist rate input, the prototype consumes 164 nW at 100kS/s. The ENOB is 8.86-bit, resulting a FoM of 3.53 fJ/conversion-step. [ABSTRACT FROM AUTHOR]

In this paper, a low-power, small-area SAR-VCO ADC is proposed using a highly linear and single-path differential VCO-based quantizer. Compared to conventional digital solution or analog design, proposed digital synthesizable dynamic voltage comparator (DVC) employs a two-stage structure, which reduces the comparator delay and offset and saves chip area. Furthermore, improved differential voltage-to-current (V–I) converter enables the realization of a single-path differential VCO-based quantizer. Trimming circuits enhance the robustness of VCO, compensating for variations induced by process variations. Additionally, a novel frequency-to-digital converter (FDC) is used as the fine quantization to directly measure the frequency. Finally, a SAR-VCO ADC is realized in 65 nm CMOS process. The simulation results show that the signal-to-noise distortion ratio (SNDR) is 70.16 dB under sampling rate of 7.8 MHz at oversampling rate (OSR) of 8. The proposed ADC has a supply voltage of 1.2V and a power consumption of 405 μW. It occupies an area of 0.16 mm2, and achieves an area figure of merit (FoM A) of 25.12 fJ*mm2/conversion-step. [ABSTRACT FROM AUTHOR]

Heated tobacco products (HTPs) are non-combustible, inhaled tobacco products that generate an aerosol with fewer and lower levels of toxicants, with a potential to reduce risk relative to cigarette smoking. Here, we assessed in vitro toxicological effects of three menthol (glo neo neoCLICK, neo Smooth Menthol and Fresh Menthol) and one non-menthol (neo Smooth Tobacco) variants of glo HTP, along with market comparators for cigarettes and HTPs. Limited chemical characterization of the study products revealed significantly lower levels of acetaldehyde, acrolein, crotanaldehyde and formaldehyde in test samples from HTPs than those from cigarettes. The glo HTPs were non-mutagenic in the bacterial reverse mutagenesis assay. Although, the whole aerosol exposures of glo HTPs were classified as genotoxic in the in vitro micronucleus assay, and cytotoxic in the NRU (monolayer) and MTT (3 dimensional EpiAirway™ tissues) assays, the cigarette comparators were the most toxic study products in each of these assessments. Further, glo HTPs elicited oxidative stress responses only at the highest dose tested, whereas the cigarette comparators were potent inducers of oxidative stress at substantially lower doses in the EpiAirway tissues. The comparator (non-glo) HTP results were similar to the glo HTPs in these assays. Thus, the glo HTPs exhibit substantially lower toxicity compared to cigarettes. [ABSTRACT FROM AUTHOR]

Research on dendrites has been conducted for decades, providing valuable information for the development of dendritic computation. Creating an ideal neuron model is crucial for computer science and may also provide robust guidance for understanding our brain's underlying mechanisms and principles. This paper aims to review the related studies regarding a newly emerging, non-spiking and biologically inspired model, the dendritic neuron model (DNM). By mimicking the biological phenomena of neurons in vivo, the DNM incorporates a neural pruning scheme to eliminate superfluous synapses and dendrites, simplifying its architecture and forming unique neuron morphology for a specific task. Furthermore, the simplified structure can be transformed into logic circuits consisting of the comparators and logic AND, OR and NOT gates, without sacrificing model accuracy. The rapidity of binary operations in hardware implementation gives the DNM a distinct advantage to handle high-speed data streams. The advent of the big data era has led to an exponential explosion in the amount and variety of available information. The appealing properties of the DNM lead us to believe that it is worthy of more attention and that it might be a promising data mining technique. This article presents an in-depth analysis of the pruning and transformation mechanisms and a comprehensive review of the learning algorithms and real-world applications of the DNM. It also presents an empirical comparison of the optimization performance of different algorithms. Finally, we outline some critical issues and future works of the DNM. All the source code of DNM is available at http://www.dnm.net.cn/. [ABSTRACT FROM AUTHOR]

In the present work, a methodology has been proposed to design analog/mixed-signal circuits using digital-in-concept circuits in digital technology. This paper presents a digital standard cell-based, scalable, highly synthesizable analog voltage comparator designed in 180 nm CMOS technology at the supply voltage of 1.8 V. The digital design requires less design effort and is highly immune to process, voltage and temperature variations. The proposed comparator has been designed and simulated in the Cadence virtuoso analog design environment. It is observed from the simulation results that the total power dissipation and propagation delay is 143.2 μW and 1.07 ns, respectively. The offset voltage of the proposed comparator is 4.98 mV. Also, as a proof-of-concept, the feasibility of the proposed analog voltage comparator is carried out on Artix-7 field-programmable gate array (FPGA) using Xilinx Basys-3 FPGA kit and other off-the-shelf components. The proposed digital-in-concept comparator is suitable for low power and high-speed SoC application with reduced design effort and lesser time-to-market. • A methodology to design analog/mixed signal circuits using digital-in-concept technique in digital technology is proposed. • Digital standard cell-based, highly synthesizable analog voltage comparator has been presented. • The proposed analog comparator has been implemented on Xilinx Basys-3 FPGA using other off-the-shelf components. • The proposed comparator is scalable to lower technologies due to its standard cell-based design methodology. • The proposed design takes less design effort, highly immune to process, voltage and temperature variations. [ABSTRACT FROM AUTHOR]

This paper proposes an Active Rectifier for low-frequency vibration piezoelectric (PZE) energy harvesting of Autonomous Underwater Vehicle (AUV). By using the cross-coupled NMOS transistors and active driven PMOS transistor, the turned-on resistance across the transistors could be minimized such that the voltage conversion efficiency is improved. Besides, the problem of the reverse current is avoided. Moreover, the novel self-biased low power comparator operated in subthreshold region is employed to reduce the power consumption. Only 6 MOS transistors and 1 resistor are required in the proposed self-biased comparator. The proposed design is implemented with a 0. 18 μ m HV process. Based on the measurement results, the peak voltage conversion efficiency (VCE) and the peak power conversion efficiency (PCE) are 97.63% and 96.26%, respectively, at 50 K Ω loads and 20 Hz vibration frequency. The maximum output power is 14.1 mW with the load of 1 K Ω. [ABSTRACT FROM AUTHOR]

• Periodic-threshold amalgamated quasi-one-junction SQUID comparator enhances sensitivity via magnetic control. • Flux-biased Josephson-junction SQUID obtains low hysteresis constant by suppressing effective critical current. • A 30 GS/s sampling rate and 9 dB sensitivity enhancement have been verified in the simulation. • 2-bit operation and performance metrics have been confirmed through the chip fabricated by the SIMIT Nb03 process. This article proposes a periodic-threshold superconductive comparator named amalgamated quasi-one-junction SQUID comparator (AQOS) for sensitivity enhancement. The comparator employs a pair of compound Josephson-junction SQUID with magnetically-controlled effective critical current in quantization to relieve the constraints on the period current without disrupting the non-hysteresis operation state. As a result, the AQOS comparator can achieve three times more comparing operations than the quasi-one-junction SQUID (QOS) comparators, corresponding to a 9 dB sensitivity improvement. The AQOS comparator also adopts the complementary structure and feedback-free topology for linearity and robustness. It can reach a 30 GS/s sampling rate, 0.5 mA period current, −25 dBm sensitivity, more than ±10 % bias current margin, deviation of quantization current peak-to-peak magnitude that is about 10 % of the mean, and the 4.4 dB average DC duty bias margin in simulation from 1 GHz to 30 GHz with a process of 6 kA/cm2 Josephson critical current density. A 2-bit AQOS comparator has been fabricated with the SIMIT Nb03 process for the qualification test. It has passed functional tests at low frequency, and its performance metrics, including period current, sensitivity, and bias current margin, have also been proven. [ABSTRACT FROM AUTHOR]

In this paper, an area-and-energy-efficient 10-bit single-ended (SE) counter-type (CT) analog-to-digital converter (ADC) with dual 5-bit capacitive digital-to-analog converter (DAC) arrays and dual 5-bit counters is presented. The 10-bit capacitive-DAC (CDAC) array and counter of the conventional counter-type structure are divided into two 5-bit CDAC arrays and counters, respectively. Significant improvements are achieved in comparison to the conventional counter-type ADC as follows: the capacitance of the most-significant-bit (MSB) capacitor is reduced by 96.88 % from 512C to 16C; the total capacitors are reduced by 93.75 % from 1024C to 64C; the total clock cycles required in the conversion phase are reduced by 93.94 % from 1023 to 62; the average switching energy is reduced by 98.55 % from 2390CV2 to 35CV2. The proposed ADC occupies a smaller area, performs much faster, and its power consumption is greatly reduced. This structure has a simple design with small sampling capacitor (32C) and does not require a rail-to-rail comparator compared to SAR ADCs. It is suitable for biomedical and multi-channel applications. The proposed ADC is post-layout simulated in 65-nm CMOS technology which occupies 0.016 mm2 area. This ADC has 85.43 nW power consumption, 9.64 ENOB on 33.33 kS/s sampling rate, and 3.23 fJ/conversion-step FOM. [ABSTRACT FROM AUTHOR]

This paper presents a high-speed low-power cryogenic CMOS two-stage dynamic comparator for SAR ADC. The pre-amplifier uses the dynamic bias technique to save power. To increase the output voltage difference of the pre-amplifier, the StrongARM latch is inserted. The proposed latch keeps a cross-coupled inverter to ensure good positive feedback. The tail current source of the proposed latch is replaced by the input pair to suppress the through current. The auxiliary input pair enhances the gain and positive feedback to speed up the latch. The paper also presents a delay analysis of the dynamic bias technique, which gives a deep understanding and a good intuition for circuit design. The simulation results demonstrate the proposed comparator achieved a CLK-Q delay of 162.1 ps and 295.4 ps at V i d = 1 mV and V C M = 0.7 V with V D D = 1.2 V and f s = 1 GHz in 300 K and 4K. The energy per comparison is 34.04 fJ and 27.75 fJ. [ABSTRACT FROM AUTHOR]

Power supply noise in current nanometer technologies represents a growing risk, specially because of the uncertainties it produces in the critical paths delays which can result in erroneous computations. Also, these very short variations can affect the functionality of analog circuits like a comparator or an ADC. To tackle with these issues and to have a better power management, on-line power supply monitors have become one common solution. Traditional approaches use an external reference, are very sensitive to temperature and process variations or present high latency. In this work we propose a 3 sigma monitor with a novel detector circuitry that employs a feedback loop that works without an external reference and it is hardened against temperature and process variations. The sensor was designed in the 40 nm CMOS technology node, operating at 1.1 V and has been validated for a temperature range of 0 ∘ C to 85 ∘ C covering all process corners. Also, considering the 3 σ confidence, the sensor is able to detect over/undershoots voltage fluctuations up to 2 GHz in the range of -70 mV to +90 mV from the nominal voltage with a maximum latency of 1.1 ns and an energy consumption per measurement of 0.8 pJ. [Display omitted] • Power supply noise in current nanometer technologies represents a growing risk. • There is a need to tackle the supply voltage noise with a better power management. • On-line power supply monitors have become one common solution. • We propose a 3 σ monitor with a novel detector circuitry. • The monitor is hardened against temperature and process variations. • The sensor covers the commercial temperature range of 0° C to 85° C. • The proposed architecture presents small area and energy per measurement overheads. [ABSTRACT FROM AUTHOR]

This paper presents a novel mass comparator designed for the purpose of measuring small weights of 2 mg and lower, with readability of 10 ng. The mass comparator was developed using new types of coil and actuator. The added protective ring decreased the average sorption-induced mass variation for the coil by 84%. The accuracy of the novel comparator was verified in terms of stability, Type An uncertainty, and repeatability. Compared to the device of the best available accuracy, the standard uncertainties of the novel-design comparator were approximately 70% narrower. • New design of mass comparator with readability 10 ng was presented. • The effect of ambient conditions, such as mass variation, was minimized. • Stability of the measurement results was 65 ng. • Repeatability was 100 ng. • Proposed design of coil and actuator proved to be advantageous. [ABSTRACT FROM AUTHOR]

Background: Single-arm trial (SAT) data is increasingly reviewed for drug approvals by regulators and Health Technology Assessment (HTA) bodies. Supplementary data in the form of external comparators (ECs) can be used to provide clinical context to support these drug evaluations. In this study we characterized HTAs for SAT-based submissions, the use of supplementary EC data and outcomes from HTA review.Methods: HTA Accelerator database was used to describe SAT-based HTA submissions with decisions (2011-2019).Results: A total of 433 SAT-based HTA submissions were identified between 2011 and 2019 with a 13-fold increase during this period. Around 65%(283/433) were in oncology or hem-oncology. Around 52%(226/433) of submissions contained some type of EC data, including prior clinical trials (24%, 104) and real-world data (RWD) (20%, 87), but 40%(175) contained no EC data. The overall acceptance rate for SAT-based submissions was 48% and with RWD EC data acceptance was 59%. In the latest 5-year period (2015-2019), use of RWD ECs increased 22% as a proportion of submissions per year, whereas, prior trial ECs decreased (-14%) and use of no EC remained stable (-2%). Between 2015 to 2017 and 2018 to 2019, acceptance rate for RWD ECs increased by 20% (41% in 2015-2017 to 61% in 2018-2019) whereas prior trial EC use decreased by 10% and no EC submissions decreased 16%. Of 226 submissions using ECs, only 29%(66) used an adjusted indirect treatment comparison method.Conclusions: SAT-based submissions to HTA bodies are rapidly evolving in terms of composition and acceptance. Types of EC and methodological approach used are important determinants of positive outcomes. [ABSTRACT FROM AUTHOR]

To determine the polymerization shrinkage (%) and shrinkage stress (MPa) characteristics of ultra-rapid photo-polymerized bulk fill resin composites. Two ultra-rapid photo-polymerized bulk fill (URPBF) materials: PFill and PFlow were studied, along with their comparators ECeram and EFlow. PFill contains an addition fragmentation chain transfer (AFCT) agent. The URPBR materials were irradiated using two different 3 s high irradiance protocols (3000 and 3200 mW/cm2 based on Bluephase PowerCure and VALO LCUs, respectively) and one 10 s standard protocol (1200 mW/cm2 based on a Bluephase PowerCure LCU). Bonded disk and Bioman II instruments were used to measure Polymerization shrinkage % and shrinkage stress MPa, respectively, for 60 min at 23 ± 1 °C (n = 5). Maximum shrinkage- rate and maximum shrinkage stress- rate were also calculated for 15 s via numerical differentiation. The data were analyzed via multiple One-way ANOVA and Tukey post- hoc tests (α = 0.05). PFill groups, regardless of their irradiance protocol, showed significantly lower PS than the comparator, ECeram (p < 0.05). However, PFlow irradiated via different protocols, was comparable to EFlow and ECeram (p > 0.05). PFill consistently produced stress results which were significantly lower than ECeram (p < 0.05) and were comparable for both high irradiance protocols (p > 0.05). PFlow only exhibited significantly higher shrinkage stress when polymerized with the 3 sVALO protocol (p < 0.05). The maximum shrinkage strain- rate (%/s) was significantly lower in PFill-10s and PFill-3s groups (using PowerCure LCU) compared to ECeram. However, no differences were seen between PFlow and EFlow (p > 0.05). The maximum shrinkage stress- rate of PFill and PFlow was comparable between different irradiation protocols, as well as to their comparator ECeram (p > 0.05). High irradiation protocols over ultra-short periods led to slightly lower shrinkage strain but slightly higher stress, possibly due to reduced network mobility. The AFCT agent incorporated in PFill composite seemed to reduce shrinkage stress development, even with high irradiance protocols. [ABSTRACT FROM AUTHOR]

In this paper, a rail-to-rail time-domain comparator with low power supply voltage and low power consumption is introduced. The comparator can be employed in low-power converters and biomedical applications. In the proposed time-domain comparator, a rail-to-rail delay element has been employed to generate a significant voltage-to-time gain for the full range of input signals. This circuit is designed, laid out, and simulated in 0.18 μm TSMC technology and powered by 0.6 V and 1 V supply voltages. The simulation results show that the proposed comparator has a rail-to-rail dynamic range and the power consumption of the circuit is 0.6 μW and 19 μW at the clock frequency of 10 MHz and 100 MHz, respectively. The active area of 56 μm × 14 μm shows the compactness of the circuit comparing to the other similar works. The proposed comparator was used in an ADC to show its effectiveness to improve the performance of the ADC. An 8-bit 0.8 V 100 kS/s SAR-ADC is designed and simulated. It consumes 430 nW and the figure of merit is 19.3fJ/conversion-step. • Time-domain comparator is an alternative to conventional voltage-mode comparator. • V-to-T conversion is performed by controlling the capacitor discharging rate. • Offset, noise and power consumption are main problems in comparators. • Figure of merit (FoM) is used to characterize the performance of the comparator. [ABSTRACT FROM AUTHOR]

Being able to self-regulate can positively impact learners' academic achievement. An inherent catalyst of Self-Regulated Learning (SRL) is internal feedback, the new knowledge which is generated when comparing current knowledge against reference information. Learners may not always generate internal feedback, hampering further SRL. Supporting SRL can be done with a Learning Analytics Dashboard (LAD), in which reference frames allow for comparisons and facilitate internal feedback generation. This study explores internal feedback generation using a LAD and the effect of reference frame availability. A multiple method design examined the interplay of reference frames, comparison processes, internal feedback generation and preparatory activities engagement. Differences between three conditions were explored using Bain ANOVA's. Results showed that reference frames almost exclude other external comparators and are used in parallel with an internal comparator. A peer reference frame leads to most verbalizations of internal feedback, and potentially to most verbalizations of preparatory activities. • Learners' internal feedback generation in self-regulated learning can be supported with a Learning Analytics Dashboard. • Presenting a reference frame in a Learning Analytics Dashboard excludes the use of other external information as comparator. • Learners' use their perception of proficiency as an internal comparator in parallel to generate internal feedback. • A peer reference frame may support generation of internal feedback and preparatory activities the most. • Using multiple comparators when generating internal feedback may lead to inconclusive interpretations. [ABSTRACT FROM AUTHOR]

This paper presents a power-efficient dynamic-time current comparator for current mode signal processing. The proposed circuit utilizes a switched feedback-based inverter and a clock-shaping circuit. The switched feedback-based inverter can detect the polarity of the sensed current from the current subtraction circuit. While the clock-shaping circuit can manage the power consumption. Since the proposed current comparator exhibits a high sensitivity to ultra-low input current with a low input offset, it can be exploited in a current mode successive-approximation-register analog-to-digital converters for a wide range of wearable applications. Moreover, a design methodology for an efficient and robust current comparator is presented. The circuit is designed and simulated in TSMC 0.13 µm CMOS technology, and occupies a silicon area of 7834 µm2. The proposed current comparator consumes a power of 14 µW with a single power supply of 1.2 V. It provides a resolution of 2 nA, and a delay of 4.6 ns. Moreover, the post-layout simulation results indicate a good agreement compared to the prior art. [ABSTRACT FROM AUTHOR]

Formalin has been used as the preservative of fishes in the concentration range of 15–25 mgL−1. However, there have been a high frequency of violations in the optimum use of formalin levels. The consumption of fishes treated with excessive formalin levels leads to nasopharynx, leukaemia and sinonasal cancer and there is a huge demand for the development of formalin sensor. Conventional formalin sensors such as chromogenic and mass balance sensors fall short in real-time analysis due to the lack of specificity and sensitivity in the interference medium. In this context, it has been emphasized to develop a non-enzymatic electrochemical biosensor with microwave synthesized CdS nanoparticles as a nanointerface owing to its surface limited kinetics. NaCl of 1 mM was considered as an electrolyte solution in the present study. Dynamic sensing characteristics with varying formalin levels of 5–50 mgL−1 was studied in three different concentration ranges as 5–15 mgL−1 (concentration of formalin < NaCl; conversion of formalin to formic acid), 20–30 mgL−1 (concentration of formalin ∼ NaCl; equilibrium between the oxidative and reductive product), 35–50 mgL−1 (concentration of formalin > NaCl; complete oxidation of formic acid to CO 2). Hence, with the exhibition of such a dynamic sensitivity based on electrolyte, the developed biosensor acts as an electrochemical comparator showcasing a switch-like behaviour in detecting formalin levels. The threshold concentration of formalin required for the comparator effect was found to be 14.845 mgL−1. The developed biosensor, most essentially, exhibited a versatility in quantifying formalin levels in real-time fish samples. Image 1 • Electrochemical detection of formalin using CdS nanoparticles as nanointerface. • Dynamic sensitivity based on electrolyte concentration showcasing a switch-like behaviour. • A novel electrochemical comparator effect is reported. • Heterogeneous rate constant and surface coverage are consistent with comparator effect. • Threshold concentration of formalin to exhibit comparator effect is 14.845 mgL−1. [ABSTRACT FROM AUTHOR]

This work presents an ultra-low-power classifier that can be integrated within energy-constrained bio-sensors to enable rapid analysis for continuous health monitoring. The in-sensor classifier saves significant transmission energy by extracting critical information locally to eliminate the need of transmitting raw data to centralized servers for remote signal processing. The convolutional-neural-network (CNN)-based classifier is built by using reconfigurable delay-locked loops (DLLs) to carry out classification algorithms with time-domain multiply-accumulate (MAC) operations. Pseudo sigmoid activation functions are realized by regenerative comparators that transform weighted timing to probabilities. The presented classifier achieves low-power consumption of 240.34 nW while performing up to 20 k operations per second. The proposed time-domain classifier reduces the energy to 36% of the previous works. • In-sensor classifier that locally extracts critical features for rapid analysis. • Cascaded DLLs to perform precise multiplication and accumulation. • Regenerative comparator output as sigmoid activation function to estimate probability. • Time-domain operations for low supply voltages. • Integrated with edge sensors to enable long-term continuous bio-signal monitoring. [ABSTRACT FROM AUTHOR]

This paper presents a highly efficient ternary flash ADC, designed using the innovative gate-overlap tunnel FET (GOTFET) at the 45 nm technology node. The proposed GOTFETs have on-state currents I on more than double, while the off-state currents I off remaining at least an order of magnitude lower than the corresponding values of the standard 45 nm CMOS technology with the same width. Replacing MOSFETs with the proposed GOTFETs significantly reduces the static power consumption and improves performance. However, the higher I on increases the dynamic power as well. To minimize the dynamic power, we propose a novel complementary GOTFET (CGOT) based comparator design. In addition to the inherent advantages of the GOTFET technology, the proposed design further reduces the dynamic power, such that the final power delay product (PDP) is merely 6.3% of the PDP in conventional CMOS comparator design. In addition to the novelty related to the innovative GOTFET devices, there are at least two-fold circuit-level novelty reported in this work. Firstly, we propose a novel CGOT based comparator circuit design, which, in addition to the advantages of GOTFET, further reduces the dynamic power such that the PDP is less than 1/3rd of the original PDP of the conventional comparator designed with GOTFETs. Secondly, the proposed CGOT based ADC requires only 48 transistors to encode the comparator outputs into the 2-bit ternary output, which is 30% lower than the 70 transistors necessary for the 2-bit CMOS based ternary flash ADC designs reported earlier in the literature. We propose an efficient 2-bit ternary flash ADC with a resolution of 50 mV and input quantized to 9 levels. Subsequently, we benchmark the performance of the proposed CGOT ternary flash ADC with the same ADC circuit implemented using the standard 45 nm CMOS technology library, all corresponding devices having the same width. We demonstrate that in addition to the superior performance than the corresponding CMOS ADC, the proposed CGOT ADC design consumes significantly lower power. The overall PDP of the proposed CGOT ADC is merely 6.3% of the PDP in corresponding CMOS design. • Gate Overlap Tunnel FET : On Current more than double & Off current an order of magnitude lower than 45 nm CMOS. • New GOTFET based Comparator Design: PDP is merely 1/3rd of that of conventional comparator. • New GOTFET based Comparator Design: PDP is merely 1/3rd of that of conventional comparator. • Reduced Transistor Count : Requires only 48 transistors compared to 70 required for conventional designs. • Reduction in PDP : GOTFET based ADC shows 99.7% improvement in PDP. [ABSTRACT FROM AUTHOR]

This paper presents a new neurodynamic approach for solving the constrained pseudoconvex optimization problem based on more general assumptions. The proposed neural network is equipped with a hard comparator function and a piecewise linear function, which make the state solution not only stay in the feasible region, but also converge to an optimal solution of the constrained pseudoconvex optimization problem. Compared with other related existing conclusions, the neurodynamic approach here enjoys global convergence and lower dimension of the solution space. Moreover, the neurodynamic approach does not depend on some additional assumptions, such as the feasible region is bounded, the objective function is lower bounded over the feasible region or the objective function is coercive. Finally, both numerical illustrations and simulation results in support vector regression problem show the well performance and the viability of the proposed neurodynamic approach. [ABSTRACT FROM AUTHOR]

Digital comparators are important arithmetic components used in digital systems to determine if two numbers are equal, or if one number is greater or less than the other. In this work, the design of magnitude and 2's complement comparators is examined. New OR-based full tree and simplified tree magnitude comparator architectures are proposed. The existing and the proposed comparator architectures are implemented in standard cell technology and evaluated, after extensive experimental analysis, in high performance and relaxed conditions. The proposed comparators operate faster than the existing ones, while operating at the same speed yield significant improvement in area complexity and power dissipation. [ABSTRACT FROM AUTHOR]

In this paper, a low-power method for double-tail comparators is introduced. Using the proposed method, the power consumption of the pre-amplifier which is the dominant part is reduced considerably. Thanks to this method, the pre-amplifier is not able to draw more than required amount of power, therefore, the power is saved. Post layout and corner simulation results show the power consumption is reduced by about 40%. Moreover, several Monte-Carlo (M) simulations suggest the proposed method results in about 20% offset reduction at the cost of 5% area and 10% speed degradation. • In dynamic comparators, the pre-amplifier amplifies the input differential signal to some extent then the latch finalizes the comparison. After some moment from the latch activation, the pre-amplifier is wasting power and sometimes reduces the gain worsening the power consumption and offset voltage. The aim of the proposed comparator is to overcome this issue. In low-offset comparators, the sizing of the input transistors of the pre-amplifier is chosen large for matching purposes so that the pre-amplifier consumes the dominant part of the total power consumption making it a good candidate to work on for low-power applications. In this paper, a low power method for dynamic comparators is presented using which the power consumption of the pre-amplifier is controlled in a proper way. Therefore, not only the power is saved but also the input referred offset voltage is improved. • In the paper, analytical derivations are presented to quantify the amount of power saving. Simulations showed the derivations are consistent with the circuit. The proposed method is able to reduce the power consumption by about 30%-40% and the offset voltage by about 20%. Post layout simulation of the RC-CC extracted circuit confirms the benefits of the proposed comparator. • The proposed method is applicable to different types of the double tail comparators. This method is simple yet effective in power reduction. [ABSTRACT FROM AUTHOR]

This work presents a design flow for asynchronous, self-timed dual-rail circuits which introduces a timing assumption in the return-to-spacer phase. The design flow enables power proportionality and is demonstrated through the design of a 32-bit ripple-carry adder and a 32-bit comparator for internet of things applications. The designs are synthesized to a 65 nm cell library with state-of-the-art transistor sizing for subthreshold. Simulation results show improved performance and energy per computation across operating conditions compared with single-rail equivalents. The design flow allows extension of the power proportional philosophy to a wider range of circuits. • A novel sizing strategy for CMOS cells in subthreshold is presented. • A design flow for dual-rail circuits is presented for IoT applications. • The design flow produces circuits with improved energy and delay over single-rail. • Adder and comparator circuits benefit from early propagation. • Early propagation improves average-case performance. [ABSTRACT FROM AUTHOR]

• The pharmacodynamics of plazomicin were studied in a pre-clinical model of infection. • Plazomicin AUC/MIC ratios for 24-h static and bactericidal effects were determined for E. coli and K. pneumoniae. • Plazomicin AUC/MIC targets align with amikacin. The new aminoglycoside plazomicin shows in vitro potency against multidrug-resistant Enterobacteriales. The exposure–response relationship of plazomicin and the comparator aminoglycoside amikacin was determined for Escherichia coli , while for Klebsiella pneumoniae only plazomicin was tested. An in vitro pharmacokinetic model was used. Five E. coli strains (two meropenem-resistant) and five K. pneumoniae strains (two meropenem-resistant) with plazomicin MICs of 0.5–4 mg/L were used. Antibacterial effect was assessed by changes in bacterial load and bacterial population profile. The correlation between change in initial inoculum after 24 h of drug exposure and the AUC/MIC ratio was good (plazomicin R 2 ≥ 0.8302; amikacin R 2 ≥ 0.9520). Escherichia coli plazomicin AUC/MIC ratios for 24-h static, –1, –2 and –3 log drop were 36.1 ± 18.4, 39.3 ± 20.9, 41.2 ± 21.9 and 44.8 ± 24.3, respectively, and for amikacin were 49.5 ± 12.7, 55.7 ± 14.8, 64.1 ± 19.2 and 73.3 ± 25.3. Klebsiella pneumoniae plazomicin AUC/MIC ratios for 24-h static, –1, –2 and –3 log drop were 34.0 ± 15.2, 46.8 ± 27.8, 67.4 ± 46.5 and 144.3 ±129.8. Plazomicin AUC/MIC ratios >66 and amikacin AUC/MIC ratios >57.7 were associated with suppression of E. coli growth on 4 × or 8 × MIC recovery plates. The equivalent plazomicin AUC/MIC to suppress resistance emergence with K. pneumoniae was >132. The plazomicin AUC/MIC for 24-h static effect and –1 log reduction in E. coli and K. pneumoniae bacterial load was in the range 30–60. Plazomicin AUC/MIC targets aligned with those of amikacin for E. coli. [ABSTRACT FROM AUTHOR]

Alzheimer's disease (AD) biomarkers, such as cerebrospinal fluid (CSF) amyloid-β (1–42; Aβ42), can provide high diagnostic accuracy. Several immunoassays are available for Aβ42 quantitation, but standardisation across assays remains an issue. We compared the Elecsys® β-Amyloid (1–42) CSF assay with three assays and two liquid chromatography tandem mass spectrometry (LC-MS/MS) methods. Three method comparison studies evaluated the correlation between the Elecsys® β-Amyloid (1–42) CSF assay versus: INNOTEST® β-AMYLOID(1–42) (860 samples) and the Roche Diagnostics-developed LC-MS/MS method (250 samples); INNO-BIA AlzBio3 and the University of Pennsylvania (UPenn)-developed LC-MS/MS method (250 samples); and ADx-EUROIMMUN Beta-Amyloid (1–42) enzyme-linked immunosorbent assay (ELISA) (49 samples). High correlation was demonstrated between Elecsys® β-Amyloid (1–42) CSF and comparator assays: INNOTEST® β-AMYLOID(1–42) (Spearman's ρ, 0.954); INNO-BIA AlzBio3 (Spearman's ρ, 0.864); ADx-EUROIMMUN Beta-Amyloid (1–42) ELISA (Pearson's r, 0.925). Elecsys® assay and LC-MS/MS measurements were highly correlated: Pearson's r, 0.949 (Roche Diagnostics-developed method) and 0.943 (UPenn-developed method). Findings from this multicentre evaluation further support use of the Elecsys® β-Amyloid (1–42) CSF assay to aid AD diagnosis. CSF-based certified reference materials should improve agreement across assays and mass spectrometry-based methods, which is essential to establish a global uniform CSF Aβ42 cut-off to detect amyloid pathology. • Elecsys® β-Amyloid (1–42) CSF assay shows good correlation with comparator assays. • Elecsys® assay measurements correlate well with two JCTLM-approved LC-MS/MS methods • CSF-based certified reference materials should improve agreement across methods. • Elecsys® β-Amyloid (1–42) CSF assay is a robust and sensitive diagnostic aid for AD. [ABSTRACT FROM AUTHOR]

A novel approach for photonic quantization using dual-output Mach–Zehnder modulators (DOMZMs) and balanced photodetectors (BPDs) is proposed and experimentally demonstrated. Based on the phase-shifting technique, all DOMZMs used in the scheme have identical half-wave voltages but are biased at different voltages. Due to the use of BPDs and DOMZMs with complementary outputs, the threshold voltages of comparators can be kept at zero, which eliminates the influence of power fluctuation of the input sampling pulses and improves the effective number of bits (ENOB) of the analog-to-digital conversion (ADC) system. After the comparators, a digital Gray code that represents the analog signal to be digitized is obtained. Proof-of-concept experiments with 8 and 16 quantization levels are implemented to verify the feasibility of the proposed approach. Bit resolution, ENOB degradation induced by bias voltage errors and potential for photonic integration are also discussed. [ABSTRACT FROM AUTHOR]

This paper proposes a new method that compares the magnitude between multiple digital input signals and introduces its logic circuit at RTL (register transfer level). For simultaneously comparing multiple inputs, the proposed algorithm uses a simple digital logic function to provide information of the largest (or smallest) value and position for these inputs. The disadvantage of using this method is that it incurs an increase hardware resource usage. To overcome this, we propose a reuse method for the overlapped logic operation. The proposed method focuses on improving the operational clock frequency, in other words, decreasing combinational delay time. After implementing the comparison method with Verilog-HDL (hardware description language), we conduct an experiment with the 28 nm CMOS library provided by TSMC Inc. In the case of 4, 8, 16, and 32 input signals, the proposed method can increase the operating clock frequency by as much as about 1.65, 2.42, 3.28 and 3.45 times, respectively, with about 1.04, 0.97, 1.84 and 4.26 times the hardware resources. • A new method to compare the magnitude between multiple unsigned digital input signals. • Simultaneously comparing multiple inputs with a simple logic function. • Experiment with the 28 nm CMOS library. • In the case of 4, 8, 16 and 32 input signals, high speed clock frequency as much as 1.65, 2.42, 3.28 and 3.45 times. [ABSTRACT FROM AUTHOR]

This paper presents a performance evaluation of an ultra low-voltage non-clocked voltage comparator, designed and fabricated in a standard twin-well 130 nm CMOS technology. The comparator can handle the input voltage within rail-to-rail range and is capable of working in temperature range from −20 to 85 °C and with power supply voltage as low as 0.4 V. The comparator is intended to be employed in an on-chip energy harvester system with minimized quiescent current consumption. So-called g m / I D low-voltage design methodology in combination with the bulk-driven design approach have been selected in the circuit topology. The measurement results obtained from fabricated prototype chips, including static and dynamic parameters, are presented and discussed as well. An excellent correlation between simulations and the measured bench data has been observed with the supply voltage value of 0.6 V, while slightly less tight correlation has been reported for V DD = 0.4 V. Anyhow, simulations and measurements both confirm that the presented silicon-proven comparator topology is capable of reliable operation with power consumption within nW range. [ABSTRACT FROM AUTHOR]

This article investigates the use of the distance function to protect shunt reactors. For this purpose, mho phase comparator is assessed. To carry out a comparative evaluation, the distance function performance was further compared with the differential function performance. Moreover, the Alternative Transit Program (ATP) was applied to model an electrical system, in which the reactor is subjected to different faults, including phase-to-phase, phase-to-ground, turn-to-ground and turn-to-turn faults. The performance of the evaluated distance function was also investigated against the number of turns involved and the leakage factor. From the results obtained, it is suggested the joint use of the distance function with the differential protection, because if the differential function does not operate, distance function would guarantee the operation for internal faults, including turn-to-ground and turn-to-turn faults, increasing reliability of protection scheme for shunt reactors. Also, the present study may serve as a guide for further studies, for example, that evaluate the use of distance function to protect iron-core reactors. • Proposes an evaluation of distance protection function for shunt reactor. • Distance protection function and differential function are compared. • Phase-to-ground, phase-to-phase, turn-to-ground and turn-to-turn faults are simulated. • The joint use of evaluated functions provides more secure faults identification. [ABSTRACT FROM AUTHOR]

This paper proposes a mid-stage latch circuit to be employed in a high-speed comparator. The advantages of the proposed circuit are low kickback noise and offset. Moreover, low-power and high-speed characteristics are obtained by avoiding direct connection between the pre-amplifier and latch stages using another stage between them. The power-delay product (PDP) of the comparator is reduced due to the reduction in charging and discharging delays at the latching nodes. The proposed comparator consumes only 244.19 µW using a 1 V supply voltage. Furthermore, the bandwidth, delay, offset, and kickback noise of the proposed comparator are 4 GHz, 26.91 ps, 3 mV, and 38 mV, respectively. Results indicate the proper performance of the proposed comparator in low-power applications. [ABSTRACT FROM AUTHOR]

This paper presents a high-speed common-mode insensitive two-stage regenerative comparator designed for low supply voltage applications. The proposed comparator features a doubled transistor latch that enables rail-to-rail operation, which is pioneered to the best of the author's knowledge. The voltage swing of output nodes of the pre-amplifiers is limited to reduce the power consumption. This limitation boosts the regeneration speed of the doubled transistor latch. The proposed comparator realized by a standard 65 nm CMOS technology. The post-layout simulation results corroborate that the proposed comparator with 50 MHz sample rate and 0.6 V supply voltage dissipates 3.4 µW power, and occupies 168 µm2 area. Also, the offset voltage variation within the full common-mode range can be below 2 mV. In a worst-case scenario compared to the conventional single-stage comparator, the proposed comparator improves delay and energy efficiency by more than 80%. Considering its overall performance, this energy-efficient comparator is suitable for all low supply voltage applications, including Internet of Things (IoT), successive approximation registers analog-to-digital converters (SAR ADCs), and biomedical implants. [ABSTRACT FROM AUTHOR]

This paper presents a power and area efficient pseudo single ended switching ADC for portable biomedical signal monitoring applications. The switching method features an 8-bit binary-weighted DAC array with a novel layout method called limited bottom-plate routing (LBPR) maintaining both feasibility and symmetry, a dynamic biased comparator and dynamic control logic. As a result, the proposed ADC saves 96.7% power consumption and 87.5% area occupation compared with conventional SAR ADC. Also, a novel DAC array layout method is promoted maintaining both feasibility and symmetry. A prototyped chip including a proposed ADC is fabricated in a 0.13 μm CMOS process. On condition of 0.6 V supply voltage and 10 kS/s sampling rate, the measured signal-to-noise-distortion (SNDR) and spurious free dynamic range (SFDR) are 57.8 dB and 64.3 dB, respectively. Besides, the ADC consumes only 40 nW power and 0.053 mm2 area achieving a figure-of-merit (FoM) of 6.26 fJ/conversion-step. Low power and low area occupation make it a good candidate for biomedical signal monitoring applications. [ABSTRACT FROM AUTHOR]

High-rate, pixelated detectors in present and future particle tracking applications call for advanced front-end circuits enabling the efficient readout of the signals delivered by the sensor. A compact, synchronous comparator enabling the integration of a zero dead time front-end is presented in this work. The proposed architecture is based on a clocked cascade of two common source stages followed by a couple of inverters. The circuit is virtually insensitive to process variations and mismatch and it is suitable for the development of flash-ADCs to be integrated in the elementary cell of a matrix of readout channels to be connected to the pixel sensor. The paper discusses the theory of operation of the proposed architecture and presents the main results coming from the simulation of the comparator in a commercial 28 nm CMOS technology. [ABSTRACT FROM AUTHOR]

• The percentages of Pseudomonas aeruginosa (P. aeruginosa) isolates resistant to imipenem, meropenem and doripenem were 26.9%, 20.5% and 17.5%, respectively. • Carbapenemase genes were detected in 14.3% of meropenem-resistant P. aeruginosa strains. • Imipenem-resistant meropenem-susceptible P. aeruginosa isolates had fewer carbapenemase genes (0.3% vs. 4.1%; P < 0.05) and a lower risk of being classified as multidrug-resistant than the imipenem-susceptible meropenem-resistant isolates (16.1% vs. 73.6%; P < 0.05). • Ceftazidime–avibactam and ceftolozane–tazobactam had higher susceptibility rates than meropenem–vaborbactam for meropenem-resistant P. aeruginosa (61.8% and 55.5% vs. 30.2%; P < 0.05). This study aimed to investigate the in vitro susceptibility and β-lactamase-encoding genes of Pseudomonas aeruginosa (P. aeruginosa) isolates with discrepant resistance to various carbapenems. Data on P. aeruginosa isolates were obtained from the Antimicrobial Testing Leadership and Surveillance program from 2012–2021. Minimum inhibitory concentrations of P. aeruginosa isolates were determined using the broth microdilution method. β-lactamase-encoding genes were identified using multiplex polymerase chain reaction assays. Among the P. aeruginosa isolates that were tested, the percentages of isolates resistant to imipenem, meropenem and doripenem were 26.9% (14 447 of 53 617), 20.5% (14 098 of 68 897) and 17.5% (3660 of 20 946), respectively. Imipenem-resistant P. aeruginosa isolates were more susceptible to all tested antimicrobial agents (except colistin) than the meropenem-resistant or doripenem-resistant P. aeruginosa isolates. Carbapenemase genes were detected in 14.3% (2020 of 14 098) of meropenem-resistant P. aeruginosa isolates. Imipenem-resistant meropenem-susceptible P. aeruginosa isolates had higher susceptibility profiles, fewer carbapenemase genes (0.3% [five of 1858] vs. 4.1% [10 of 242]; P < 0.05) and a lower risk of being classified as multidrug-resistant than the imipenem-susceptible meropenem-resistant isolates (16.1% [299 of 1858] vs. 73.6% [178 of 242]; P < 0.05). Among all β-lactam combination agents, ceftazidime–avibactam and ceftolozane–tazobactam had higher susceptibility rates than meropenem–vaborbactam for meropenem-resistant P. aeruginosa (61.8% and 55.5% vs. 30.2%; P < 0.05). Discrepancy in the resistance of different P. aeruginosa isolates to various carbapenems suggests their different underlying resistance mechanisms. These findings can be useful for effective resistance trend monitoring and accurate antimicrobial treatment in the future. [ABSTRACT FROM AUTHOR]