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We study the effects of the variation of ferroelectric material properties (thickness, polarization, and coercivity) on the performance of negative capacitance FETs (NCFETs). Based on this, we propose the concept of conservative design of NCFETs, where any unintentional yet reasonable and simultaneous variation ( $\sim \pm 3$ %) in ferroelectric parameters does not result in the emergence of hysteresis and causes only a reasonable variation in the ON-current (≤5%) and, within these constraints, the enhancement of ON-current due to the addition of the ferroelectric gate oxide, which is is maximized. [ABSTRACT FROM AUTHOR]

Negative capacitance FETs (NCFETs) have attracted significant interest due to their steep-switching capability at a low voltage and the associated benefits for implementing energy-efficient Boolean logic. While most existing works aim to avoid the ID – VG hysteresis in NCFETs, this paper exploits this hysteresis feature for logic-memory synergy and presents a custom-designed nonvolatile NCFET D flip-flop (DFF) that maintains its state during power outages. This paper also presents an NCFET fabricated for this purpose, showing <10 mV/decade steep hysteresisedges and high, up to seven orders inmagnitude, R\text {DS} ratio between the two polarization states. With a device-circuit codesign that takes advantage of the embedded nonvolatility and the high R\text {DS} ratio, the proposed DFF consumes negligible static current in backup and restore operations, and remains robust even with significant global and local ferroelectric material variations across a wide 0.3–0.8 V supply voltage range. Therefore, the proposed DFF achieves energy-efficient and low-latency backup and restore operations. Furthermore, it has an ultralow energy-delay overhead, below 2.1% in normal operations, and operates using the same voltage supply as the Boolean logic elements with which it connects. This promises energy-efficient nonvolatile computing in energy-harvesting and power-gating applications. [ABSTRACT FROM PUBLISHER]

We demonstrate non-volatile, n-type, back-gated, MoS2 transistors, placed directly on an epitaxial grown, single crystalline, PbZr0.2Ti0.8O3 (PZT) ferroelectric. The transistors show decent ON current (19μA/lm), high on-off ratio (107), and a subthreshold swing of (SS~92 mV/dec) with a 100 nm thick PZT layer as the back gate oxide. Importantly, the ferroelectric polarization can directly control the channel charge, showing a clear anti-clockwise hysteresis. We have selfconsistently confirmed the switching of the ferroelectric and corresponding change in channel current from a direct time-dependent measurement. Our results demonstrate that it is possible to obtain transistor operation directly on polar surfaces, and therefore, it should be possible to integrate 2D electronics with single crystalline functional oxides. [ABSTRACT FROM AUTHOR]

Ferroelectric field-effect transistors (FEFETs) are an important candidate for emerging nonvolatile memory applications but suffer from a lack of physical understanding of the device operation. Previous FEFET models utilized the Preisach model of ferroelectrics and do not accurately capture the physics of the FEFET that the majority of the polarization charge is screened by trapped charge at the interfaces. We propose an empirical model for FEFETs, which also considers screening of ferroelectric polarization. The screening charge is modeled as a dissipative (leakage) current across the baseline MOS gate-stack. The proposed model is calibrated using the experimental data of p-type ZrO2 FEFETs and unravels the weak electrostatic coupling between the ferroelectric polarization and semiconductor channel charge. In addition, the model captures the memory window discrepancy between the charge–voltage characteristics and current–voltage characteristics observed in the experimental data, provides new insight into the ferroelectric device, and is well-suited for use as a compact model implementation of FEFETs. [ABSTRACT FROM AUTHOR]

While the theoretical maximum of the memory window $\Delta {V}_{t}$ in a ferroelectric field-effect transistor (FEFET) is $2{E}_{C}{t}_{F}$ , ${E}_{C}$ and ${t}_{F}$ being coercive field and FE thickness, respectively, experimentally $\Delta {V}_{t}$ is observed to be much less than that, even in the case of complete polarization switching in the ferroelectric layer. This occurs because trapped charges in the gate oxide stack partially or completely screen the ferroelectric polarization, only a fraction of which gets “electrostatically” reflected in the semiconductor channel. In this article, we provide a generalized experimental framework to quantify the efficiency of practical FEFETs in converting the switched ferroelectric polarization into the memory window. To that end, we propose three efficiency metrics: 1) switched ferroelectric polarization $\Delta {P}_{F}$ to memory window conversion ratio, $\eta _{MW}=\Delta {V}_{t}/\Delta {P}_{F}$ ; 2) switched ferroelectric polarization to the semiconductor charge ($\Delta {Q}_{S}$) conversion efficiency or the charge conversion efficiency $\eta _{c}=\Delta {Q}_{s}/\Delta {P}_{F}$ ; and 3) the ratio of memory window to the width of polarization versus gate voltage hysteresis characteristics ($\Delta {V}_{P}$) or the voltage conversation efficiency $\eta _{V}=\Delta {V}_{t}/\Delta {V}_{P}$. We measure and compare these efficiency metrics in n-type and p-type FEFETs, fabricated in different facilities by different groups. In all the cases, we find that the maximum values of memory window efficiency $(\eta _{MW})_{max}$ , charge conversion efficiency $(\eta _{c}$) $_{max}$ , and voltage conversion efficiency ($\eta _{V}$) $_{max}$ are in the range: 2.5–5.5 Vm2/C, 4%–10%, and 5%–20%, respectively. [ABSTRACT FROM AUTHOR]

Enhancement‐mode ultrawide‐bandgap Al0.65Ga0.35N/Al0.4Ga0.6N metal–insulator–semiconductor heterojunction field‐effect transistors are demonstrated using fluorine‐plasma treatment for threshold voltage control and Al2O3 as gate dielectric. The device exhibits a threshold voltage of 5 V, a maximum drain current density of 105 mA mm−1, and a transconductance of 19 mS mm−1. In addition, the capability to achieve low off‐state current density at 3–4 × 10−9 mA mm−1, an exceptionally low gate leakage current density of 1.4 × 10−8 mA mm−1 even at a high forward gate bias of VGS = 12 V, and a current on/off ratio >1010 is shown. Small signal measurement shows that the device has a unity current gain cutoff frequency fT of 3.8 GHz and power gain cutoff frequency fmax of 4.5 GHz. [ABSTRACT FROM AUTHOR]

Three-dimensional NAND architecture (3-D NAND) based on ferroelectric field-effect transistors (FeFETs) is explored for in-memory computing. In ferroelectric Hafnia-based polycrystalline thin film, which is deposited on the gate of the FeFETs, the monoclinic (M), and orthorhombic (O) phases coexist. These two phases of positional distribution introduce a read-out current variation in the 3-D NAND of FeFETs. Herein, we employ TCAD simulations to quantify such variation and optimize bias conditions for improving the accuracy of in-memory computing. Furthermore, the array-level impact of the phase variation on vector-matrix multiplication has been investigated using a 3-D netlist with SPICE simulations, indicating sufficient read-out accuracy possible for analog-to-digital conversion. [ABSTRACT FROM AUTHOR]

We present the temperature-dependent electrical characteristics of high-current depletion (D-mode) and barrier-recessed enhancement-mode (E-mode) ultrawide bandgap (UWBG) AlxGa1−xN channel insulated gate heterojunction field-effect transistors fabricated on the same wafer. The key motivation is the higher Baliga figure of merit for devices with the UWBG AlGaN channel and their strong potential for use in high-power, high-temperature harsh environmental applications. Over a temperature range of 125 °C, the VTH shifted in the opposite direction for D- and E-mode devices with a rate of +13.5 mV/K and −23 mV/K, respectively, giving an overall shift of +1.7 V and −2.9 V. This was attributed to changes in the fixed and trapped charge densities in the dielectric and at the dielectric–AlGaN barrier interface. A single deep sub-bandgap trap level was sufficient to explain the threshold shifts in both devices. The effective channel mobility in the E-mode devices was argued to be limited by charge scattering, arising from the same charges introduced during barrier recessing that shifted VTH. [ABSTRACT FROM AUTHOR]

Doped HfO2-based ferroelectric field-effect transistor (FeFET) is being actively explored as an emerging nonvolatile memory device with the potential for in-memory computing. In this work, we identify a new challenge of ferroelectric partial switching, namely “history effect” in minor loop dynamics. We experimentally demonstrate the minor loop dynamics in both ferroelectric capacitor (FeCap) and 28-nm FeFET in Part I. In this article, a physics-based phase-field multidomain switching model is used to understand the origin. Even though the device may have the same polarization state that is externally observable, its internal domain configuration varies depending on its history. We model such history effect into the FeFET-based neural network simulation and analyze its negative impact on the training accuracy and then propose a possible mitigation strategy. [ABSTRACT FROM AUTHOR]

Doped HfO2-based ferroelectric field-effect transistor (FeFET) is being actively explored as an emerging nonvolatile memory device with the potential for in-memory computing. In this work, we identify a new challenge of ferroelectric partial switching, namely “history effect” in minor loop dynamics. We develop a testing protocol to experimentally measure different transition paths in both ferroelectric capacitors (FeCap) and 28-nm high-k metal-gate (HKMG) FeFET in Part I. The measurement results suggest that the intermediate states programming condition depends on the prior states that the device has gone through, and the condition may vary even when the transition occurs between the same starting and ending states. In Part II, a physics-based phase-field multidomain switching model is used to understand the origin of the history effect. [ABSTRACT FROM AUTHOR]

Ferroelectric-doped HfO2-based ferroelectric field-effect transistors (FeFETs) are being actively explored as emerging nonvolatile memory (NVM) devices with the potential for in-memory computing. In this two-part article, we explore the feasibility of the FeFET-based 3-D NAND architecture for both in situ training and inference. To address the challenge of erase-by-block in a NAND-like structure, we propose and experimentally demonstrate the drain-erase scheme to enable the individual cell’s program/erase/inhibition, which is necessary for individual weight updates in in situ training. We described the device characterization of different drain-erase conditions and results in Part I. The array-level design for this drain-erase scheme for both AND-type and NAND-type array is addressed in this Part II. A 3-D vertical channel FeFET array architecture is proposed to accelerate the vector-matrix multiplication (VMM). 3-D timing sequence of the weight update rule is designed and verified through the 3-D-array-level SPICE simulation. Finally, the VMM operation is simulated in a 3-D NAND-like FeFET array. [ABSTRACT FROM AUTHOR]

Ferroelectric-doped HfO2-based ferroelectric field-effect transistors (FeFETs) are being actively explored as emerging nonvolatile memory devices with the potential for in-memory computing. In this two-part article, we explore the feasibility of FeFET-based 3-D NAND architecture for both in situ training and inference. To address the challenge of erase-by-block in NAND-like structure, we propose and experimentally demonstrate the drain–erase scheme to enable the individual cell’s program/erase/inhibition, which is necessary for individual weight update in in situ training. We describe the device characterization of different drain–erase conditions and results in this article. The experimental conditions are characterized on 22-nm fully depleted silicon-on-insulator (FDSOI) and 28-nm high-k metal gate (HKMG) FeFET devices from GLOBALFOUNDRIES. With appropriate biasing, up to 104 ON/OFF ratio could be achieved by drain–erase. The 3-D NAND array architecture design and verification for in-memory computing will be described in Part II of this article. [ABSTRACT FROM AUTHOR]

A ferroelectric field-effect transistor (FeFET) with scaled dimensions (170 nm and 24 nm of gate width and length, respectively) and a 10 nm thick Si doped HfO 2 ferroelectric in the gate oxide stack are characterized at cryogenic temperatures down to 6.9 K. We observe that a decrease in temperature leads to an increase in the memory window at the expense of an increased program/erase voltage. This is consistent with the increase in the ferroelectric coercive field due to the suppression of thermally activated domain wall creep motion at cryogenic temperatures. However, the observed insensitivity of the location of the memory window with respect to temperature cannot be explained by the current understanding of the device physics of FeFETs. Such temperature dependent studies of scaled FeFETs can lead to useful insights into their underlying device physics, while providing an assessment of the potential of this emerging technology for cryogenic memory applications. [ABSTRACT FROM AUTHOR]

Negative capacitance field-effect transistors (NCFETs) with optimal ferroelectric parameters provide phenomenal power reduction as discussed in Part I. In this part, we explore the impact of operating voltage on power consumption at the device, gate, and full-chip levels. We first observe that high operating voltages applied to NCFET devices lead to an abrupt increase in both the drain current and the gate capacitance. Furthermore, negative capacitance is lost when the voltage is set too high. On the other hand, the gate capacitance increase still exists, although with smaller magnitude, even at low operating voltages. This helps reduce device delay and eventually full-chip delay. Furthermore, delay improvement at the full-chip level can be traded off to gain power reduction at the full-chip level. Finally, our experiments suggest that a sufficiently low supply voltage (= 0.4 V out of [0.2 and 0.8 V] range in our study) is needed to maximize power and performance gain at full-chip level. [ABSTRACT FROM AUTHOR]

In this two-part article, we propose a framework for selecting ferroelectric oxide material for the design of a negative capacitance field-effect transistor (NCFET). The investigation is based on an exhaustive search of two important ferroelectric material parameters: remnant polarization and coercive field in the context of their negative capacitance properties. The effects of these parameters are first studied at the NCFET device level and systematically extended up to the full-chip level. Based on this search, we arrive at the notion of optimality of ferroelectric parameters for a given “isoperformance full-chip benchmark”: The power dissipation in a specific circuit/system is maximally reduced by using optimized NCFETs while meeting the target performance. In Part I, we develop the framework for identifying optimal ferroelectric parameters at a given VDD. This sets the stage for Part II, where we investigate the optimal ferroelectric parameters as VDD is scaled. [ABSTRACT FROM AUTHOR]

Ultrawide bandgap (UWBG) AlGaN-channel metal-oxide-semiconductor heterostructure field-effect transistors (MOSHFETs) with a ZrO2 gate dielectric achieve peak current in excess of 0.4 A/mm and current ON/OFF ratios >106 with subthreshold swings as low as 110 mV/decade. These devices have strong potential for use in power and radio frequency electronics or as true solar-blind photodetectors. In this work, we present the photoresponse analysis in UWBG AlGaN MOSHFETs. Persistent photoconductivity with the decay time above 10 minutes can be quenched by illuminating with strong UV light at 365 nm and 254 nm, suggesting deep traps to be responsible for this behavior. Upon correlating the optical response under various illumination conditions with cathodoluminescence of these devices, we identified two key trap levels at ∼2.48 ± 0.14 eV and 3.76 ± 0.06 eV, controlling the slow response time. By depth-profiling using cathodoluminescence, these traps are identified to be at the AlN/AlGaN interface at the back of the device, due to partial relaxation from the lattice mismatch between AlN and Al0.4Ga0.6N. [ABSTRACT FROM AUTHOR]

In this letter, we design and demonstrate an improved metalorganic chemical vapor deposition (MOCVD) grown reverse Al-composition graded contact layer, whereby the Al-composition of AlxGa1−xN in the contact layer is graded from the higher Al-composition as in the channel to lower Al-composition, to achieve a low resistance contact to MOCVD grown ultrawide bandgap Al0.70Ga0.30N channel metal-semiconductor field-effect transistors. Increasing the thickness of the reverse graded layer was found to improve contact layer resistance significantly, leading to a contact resistivity of 3.3 × 10−5 Ω cm2. Devices with a gate length, LG, of 0.6 μm and a source-drain spacing, LSD, of 1.5 μm displayed a maximum current density, IDS,MAX, of 635 mA/mm with an applied gate voltage, VGS, of +2 V. Breakdown measurements on transistors with a gate to drain spacing, LGD, of 770 nm had breakdown voltage greater than 220 V, corresponding to a minimum breakdown field of 2.86 MV/cm—almost 3× higher than that exhibited by lateral GaN channel devices with similar dimensions. This work provides a framework for the design of low resistance contacts to MOCVD grown high Al-content AlxGa1−xN channel transistors. [ABSTRACT FROM AUTHOR]

To further reduce the power dissipation in nanoscale transistors, the fundamental limit posed by the Boltzmann distribution of electrons has to be overcome. Stabilization of negative capacitance in a ferroelectric gate insulator can be used to achieve this by boosting the transistor gate voltage. Up to now, negative capacitance is only directly observed in polymer and perovskite ferroelectrics, which are incompatible with semiconductor manufacturing. Recently discovered HfO2-based ferroelectrics, on the other hand, are ideally suited for this application because of their high scalability and semiconductor process compatibility. Here, for the first time, a direct measurement of negative capacitance in polycrystalline HfO2-based thin films is reported. Decreasing voltage with increasing charge transients are observed in 18 and 27 nm thin Gd:HfO2 capacitors in series with an external resistor. Furthermore, a multigrain Landau-Khalatnikov model is developed to successfully simulate this transient behavior in polycrystalline ferroelectrics with nucleation limited switching dynamics. Structural requirements for negative capacitance in such materials are discussed. These results demonstrate that negative capacitance effects are not limited to epitaxial ferroelectrics, thus significantly extending the range of potential applications. [ABSTRACT FROM AUTHOR]

Abstract: We present a method to determine the average device channel temperature of AlGaN/GaN metal–oxide–semiconductor heterostructure field effect transistors (MOSHFETs) in the time domain under continuous wave (CW) and periodic-pulsed RF (radiation frequency) operational conditions. The temporal profiles of microwave output power densities of GaN MOSHFETs were measured at 2GHz under such conditions and used for determination of the average channel temperature. The measurement technique in this work is also being utilized to determine the thermal time constant of the devices. Analytical temporal solutions of temperature profile in MOSHFETs are provided to support the method. The analytical solutions can also apply to generic field effect transistors (FETs) with an arbitrary form of time-dependent heat input at the top surface of the wafer. It is found that the average channel temperature of GaN MOSHFETs on a 300μm sapphire substrate with the output power of 10W/mm can be over 400°C in the CW mode while the average channel temperature of GaN MOSHFETs on a SiC substrate with the same thickness only reaches 50°C under the same condition. The highest average channel temperature in a pulsed RF mode will vary with respect to the duty cycle of the pulse and type of the substrate. [Copyright &y& Elsevier]

• New approach to make ohmic contacts to high Al-content AlGaN channel HFETs. • First demonstration of All-MOCVD grown AlGaN channel HFETs with a graded contact layer. • Demonstration of lowest contact resistance on AlGaN channel HFETs with Al composition above 50%. We report a gate recessed Al 0.7 Ga 0.3 N/Al 0.5 Ga 0.5 N heterostructure field effect transistor (HFET) with a graded contact cap layer grown by metal organic chemical vapor deposition (MOCVD) on AlN/Sapphire substrate. A low specific contact resistivity ρ c of 2.1 × 10−5 Ω·cm2 is demonstrated with current injection from the top of the Al 0.7 Ga 0.3 N barrier to the Al 0.5 Ga 0.5 N channel. The device with a gate length of 160 nm exhibits a drain current density at gate shorted to source (I D,SS) of 420 mA/mm, a cutoff frequency f T of 20 GHz, and a maximum oscillation frequency (f max) of 40 GHz. The same device has a three terminal off-state gate-to-drain breakdown voltage of 170 V, corresponding to an average breakdown field (F BR) of 2.8 MV/cm between the gate and drain, due to drain induced barrier lowering effect. Devices with a gate length of 1 µm demonstrate a gate to drain breakdown voltage of 195 V or an average breakdown field of 3.9 MV/cm. This work provides a way to make ohmic contacts to Al-rich AlGaN channel heterojunction transistors for high power and high frequency applications. [ABSTRACT FROM AUTHOR]