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In this work, we present a systematic study of the effect of the stoichiometry of BaTiO3 (BTO) films grown on the Ge(001) substrate by molecular-beam-epitaxy using different characterization methods relying on beam diffraction, including reflection high-energy electron diffraction (RHEED), X-ray diffraction (XRD), and selected-area electron diffraction in transmission electron microscopy. Surprisingly, over a wide range of [Ba]/[Ti] ratios, as measured by the Rutherford backscattering spectrometry, all the BTO layers exhibit the same epitaxial relationship h100iBTO(001)// 〈110〉Ge(001) with the substrate, describing a 45° lattice rotation of the BTO lattice with respect to the Ge lattice. However, varying the [Ba]/[Ti] ratio does change the diffraction behavior. From RHEED patterns, we can derive that excessive [Ba] and [Ti] generate twinning planes and a rougher surface in the non-stoichiometric BTO layers. XRD allows us to follow the evolution of the lattice constants as a function of the [Ba]/[Ti] ratio, providing an option for tuning the tetragonality of the BTO layer. In addition, we found that the intensity ratio of the 3 lowest-order Bragg peaks I(001)/ I(002), I(101)/I(002), and I(111)/I(002) derived from ω-2θ scans characteristically depend on the BTO stoichiometry. To explain the relation between observed diffraction patterns and the stoichiometry of the BTO films, we propose a model based on diffraction theory explaining how excess [Ba] or [Ti] in the layer influences the diffraction response. [ABSTRACT FROM AUTHOR]

The tunneling current through an atomic force microscopy (AFM) tip is used to evaluate the effective electrical contact area, which exists between tip and sample in contact-AFM electrical measurements. A simple procedure for the evaluation of the effective electrical contact area is described using conductive atomic force microscopy (C-AFM) in combination with a thin dielectric. We characterize the electrical contact area for coated metal and doped-diamond tips operated at low force (<200 nN) in contact mode. In both cases, we observe that only a small fraction (<10 nm2) of the physical contact (~100 nm2) is effectively contributing to the transport phenomena. Assuming this reduced area is confined to the central area of the physical contact, these results explain the sub-10 nm electrical resolution observed in C-AFM measurements. [ABSTRACT FROM AUTHOR]

Band-to-band tunneling parameters of strained indirect bandgap materials are not well-known, hampering the reliability of performance predictions of tunneling devices based on these materials. The nonlocal band-to-band tunneling model for compressively strained SiGe is calibrated based on a comparison of strained SiGe p-i-n tunneling diode measurements and doping-profile-based diode simulations. Dopant and Ge profiles of the diodes are determined by secondary ion mass spectrometry and capacitance-voltage measurements. Theoretical parameters of the band-to-band tunneling model are calculated based on strain-dependent properties such as bandgap, phonon energy, deformation-potential-based electron-phonon coupling, and hole effective masses of strained SiGe. The latter is determined with a 6-band k.p model. The calibration indicates an underestimation of the theoretical electron-phonon coupling with nearly an order of magnitude. Prospects of compressively strained SiGe tunneling transistors are made by simulations with the calibrated model. [ABSTRACT FROM AUTHOR]

Following an extensive investigation of various monolayer transition metal dichalcogenides (MX2), research interest has expanded to include multilayer systems. In bilayer MX2, the stacking order strongly impacts the local band structure as it dictates the local confinement and symmetry. Determination of stacking order in multilayer MX2 domains usually relies on prior knowledge of in-plane orientations of constituent layers. This is only feasible in case of growth resulting in well-defined triangular domains and not useful in-case of closed layers with hexagonal or irregularly shaped islands. Stacking order can be discerned in the reciprocal space by measuring changes in diffraction peak intensities. Advances in detector technology allow fast acquisition of high-quality four-dimensional datasets which can later be processed to extract useful information such as thickness, orientation, twist and strain. Here, we use 4D scanning transmission electron microscopy combined with multislice diffraction simulations to unravel stacking order in epitaxially grown bilayer MoS2. Machine learning based data segmentation is employed to obtain useful statistics on grain orientation of monolayer and stacking in bilayer MoS2. [ABSTRACT FROM AUTHOR]

In this atomic-scale study on wet etching, the importance of surface chemistry, in particular the nature of the surface oxides, is demonstrated for technologically relevant group IV semiconductors, Ge and SiGe. Elemental quantification of Ge in hydrochloric acid solution containing hydrogen peroxide showed a striking impact of the Si bulk concentration on the kinetics of etching. Post operando surface analysis provided insight into the oxide product formed after etching: a non-homogeneous porous layer with a depletion of Ge components at the outer surface due to pull out effects. Oxide formation was verified by microscopic imaging. We provide basic reaction schemes that help to elucidate the results. [ABSTRACT FROM AUTHOR]

We report on the performance of the quantum confined Stark effect (QCSE) in ultra-thin (~350 nm) Ge/SiGe quantum well stacks grown on Si. We demonstrate an absorption contrast $\Delta \alpha /\alpha $ of 2.1 at 1 Vpp swing in QCSE stacks grown on ultra-thin (100 nm) strain relaxed GeSi buffer layers on 300 mm Si wafers. Such ultra-thin QCSE stacks will enable future integration of highly efficient QCSE electro-absorption modulators with low optical coupling loss to passive Si waveguides in a sub-micron silicon photonics platform. [ABSTRACT FROM AUTHOR]

Polycrystalline silicon (pc-Si) thin-films with a grain size in the range of 0.1–100 μm grown on top of inexpensive substrates are economical materials for semiconductor devices such as transistors and solar cells and attract much attention nowadays. For pc-Si, grain size enlargement is thought to be an important parameter to improve material quality and therefore device performance. Aluminum-induced crystallization (AIC) of amorphous Si in combination with epitaxial growth allows achieving large-grained pc-Si layers on nonsilicon substrates. In this work, we made pc-Si layers with variable grain sizes by changing the crystallization temperature of the AIC process in order to see if larger grains indeed result in better solar cells. Solar cells based on these layers show a performance independent of the grain size. Defect etching and electron beam induced current (EBIC) measurements showed the presence of a high density of electrically active intragrain defects. We therefore consider them as the reason for the grain size independent device performance. Besides dislocations and stacking faults, also Σ3 boundaries were electrically active as shown by combining electron backscattered diffraction with EBIC measurements. The electrical activity of the defects is probably triggered by impurity decoration. Plasma hydrogenation changed the electrical behavior of the defects, as seen by photoluminescence, but the defects were not completely passivated as shown by EBIC measurements. In order to reveal the origin of the defects, cross section transmission electron microscopy measurements were done showing that the intragrain defects are already present in the AIC seed layer and get copied into the epitaxial layer during epitaxial growth. The same types of intragrain defects were found in layers made on different substrates (alumina ceramic, glass ceramic, and oxidized silicon wafer) from which we conclude that intragrain defects are not related to the relatively rough alumina ceramic substrates often used in combination with high temperature epitaxy. Further improvement of the material quality, and hence device performance, is therefore not simply achieved by increasing the grain size, but the intragrain quality of the material also needs to be taken into account. For pc-Si layers based on AIC and epitaxial growth, the seed layer has a crucial impact on the intragrain defect formation. [ABSTRACT FROM AUTHOR]

Atomic layer deposition (ALD) is used in applications where inorganic material layers with uniform thickness down to the nanometer range are required. For such thicknesses, the growth mode, defining how the material is arranged on the surface during the growth, is of critical importance. In this work, the growth mode of the zirconium tetrachloride/water and the trimethyl aluminum/water ALD process on hydrogen-terminated silicon was investigated by combining information on the total amount of material deposited with information on the surface fraction of the material. The total amount of material deposited was measured by Rutherford backscattering, x-ray fluorescence, and inductively coupled plasma–optical emission spectroscopy, and the surface fractions by low-energy ion scattering. Growth mode modeling was made assuming two-dimensional growth or random deposition (RD), with a “shower model” of RD recently developed for ALD. Experimental surface fractions of the ALD-grown zirconium oxide and aluminum oxide films were lower than the surface fractions calculated assuming RD, suggesting the occurrence of island growth. Island growth was confirmed with transmission electron microscopy (TEM) measurements, from which the island size and number of islands per unit surface area could also be estimated. The conclusion of island growth for the aluminum oxide deposition on hydrogen-terminated silicon contradicts earlier observations. In this work, physical aluminum oxide islands were observed in TEM after 15 ALD reaction cycles. Earlier, thicker aluminum oxide layers have been analyzed, where islands have not been observed because they have already coalesced to form a continuous film. The unreactivity of hydrogen-terminated silicon surface towards the ALD reactants, except for reactive defect areas, is proposed as the origin of island growth. Consequently, island growth can be regarded as “undesired surface-selective ALD.” [ABSTRACT FROM AUTHOR]

The polycrystalline silicon (pc-Si) layers with variable grain sizes were constructed by changing the crystallization temperature of the AIC process and determine if larger grains resulted in better solar cells. The crucial impact of seed layer on the intragrain defect formation for the pc-Si layers based on AIC and epitaxial growth suggested that in addition to increased grain size, the intragrain quality of the material should also be considered in order to improve material quality and achieve high device performance.

We report the electrical properties of 60° dislocations originating from the +1.2% lattice mismatch between an unintentionally doped, 315 nm thick Ge0.922Sn0.078 layer (58% relaxed) and the underlying Ge substrate, using deep level transient spectroscopy. The 60° dislocations are found to be split into Shockley partials, binding a stacking fault. The dislocations exhibit a band-like distribution of electronic states in the bandgap, with the highest occupied defect state at ∼EV + 0.15 eV, indicating no interaction with point defects in the dislocation's strain field. A small capture cross-section of 1.5 × 10−19 cm2 with a capture barrier of 60 meV is observed, indicating a donor-like nature of the defect-states. Thus, these dislocation-states are not the source of unintentional p-type doping in the Ge0.922Sn0.078 layer. Importantly, we show that the resolved 60° dislocation-states act as a source of leakage current by thermally generating minority electrons via the Shockley-Read-Hall mechanism. [ABSTRACT FROM AUTHOR]

Co has elicited a strong interest to replace Cu for future interconnect applications in microelectronic circuits due to its potentially lower resistivity and better reliability at scaled dimensions. Here, we demonstrate Co wires with electrical cross-sectional areas as small as 34 nm2 using a simple subtractive patterning technique. Semiclassical resistivity modeling of the wire resistivity indicates that grain boundary scattering is the dominant contribution for cross-sectional areas of the order of 100 nm2, while the contribution of surface scattering increases drastically below 50 nm2. Furthermore, wafer-level reliability tests of the Co wires show the high fusing current densities and a strong resistance to thermoelectric stress demonstrating the potential for robust reliability. The resistivity and the reliability of the Co wires are comparable with those of Ru wires. [ABSTRACT FROM AUTHOR]

The structure, crystallinity and properties of as-deposited two-dimensional (2D) transition metal dichalcogenides are determined by nucleation mechanisms in the deposition process. 2D materials grown by atomic layer deposition (ALD) in the absence of a template are polycrystalline or amorphous. Little is known about their nucleation mechanisms. Therefore, the nucleation behavior of WS2 during plasma enhanced ALD from WF6, H2 plasma and H2S at 300 °C is investigated on amorphous ALD Al2O3 starting surface and on monocrystalline, bulk sapphire. Preferential interaction of the precursors with the Al2O3 starting surface promotes fast closure of the WS2 layer. The WS2 layers are fully continuous at WS2 content corresponding to only 1.2 WS2 monolayers. On amorphous Al2O3, (0002) textured and polycrystalline WS2 layers form with grain size of 5 to 20 nm due to high nucleation density (∼1014 nuclei/cm2). The WS2 growth mode changes from 2D (layer-by-layer) growth on the initial Al2O3 surface to three-dimensional (Volmer-Weber) growth after WS2 layer closure. Further growth proceeds from both WS2 basal planes in register with the underlying WS2 grain and from or over grain boundaries of the underlying WS2 layer with different in-plane orientation. In contrast, on monocrystalline sapphire, WS2 crystal grains can locally align along a preferred in-plane orientation. Epitaxial seeding occurs locally albeit a large portion of crystals remain randomly oriented, presumably due to the low deposition temperature. The WS2 sheet resistance is 168 MΩμm, suggesting that charge transport in the WS2 layers is limited by grain boundaries. [ABSTRACT FROM AUTHOR]

Raman spectroscopy is uniquely sensitive to crucial material properties like stress and composition, but is inherently diffraction-limited, impeding its application potential in nanostructured devices. Under correct polarization conditions, the Raman response from a periodic array of fins is dramatically enhanced inside the semiconductor material, re-enabling fast and non-destructive optical characterization of deep-subwavelength semiconductor patterns. In this paper, it is shown that the effect is not limited to the material system where it was first observed, and results of nanofocused Raman spectroscopy in a variety of semiconductor materials are presented. The authors illustrate and discuss how the universality of the enhancement creates a unique potential for non-invasive and rapid stress and composition measurements at the nanoscale. [ABSTRACT FROM AUTHOR]

In this work, we report on wet-chemical defect revealing in InP fin structures relevant for device manufacturing. Both HCl and HBr solutions were explored using bulk InP as a reference. A distinct difference in pit morphology was observed between the two acids, attributed to an anisotropy in step edge reactivity. The morphology of the etch pits in bulk InP suggests that the dislocations are oriented mainly perpendicular to the surface. By studying the influence of the acid concentration on the InP fin recess in nanoscale trenches, it was found that aqueous HCl solution was most suitable for revealing defects. Planar defects in InP fin structures grown by the aspect ratio trapping technique could be visualized as characteristic shallow grooves approximately one nanometer deep. It is challenging to reveal defects in wide-field InP fins. In these structures, dislocations also reach the surface next to stack faults or twinning planes. Due to the inclined nature, dislocation-related pits are only a few atomic layers deep. Extending the pits is limited by the high reactivity of the fin sides and the strong surface roughening during etching. The process window for revealing wet-chemical defects in InP fins is limited. [ABSTRACT FROM AUTHOR]

Vertical InAs nanowires (NWs) grown on a Si substrate are promising building-blocks for next generation vertical gate-all-around transistor fabrication. We investigate the initial stage of InAs NW selective area epitaxy (SAE) on a patterned Si (111) substrate with a focus on the interfacial structures. The direct epitaxy of InAs NWs on a clean Si (111) surface is found to be challenging. The yield of vertical InAs NWs is low, as the SAE is accompanied by high proportions of empty holes, inclined NWs, and irregular blocks. In contrast, it is improved when the NW contains gallium, and the yield of vertical InxGa1-xAs NWs increased with higher Ga content. Meanwhile, unintentional Ga surface contamination on a patterned Si substrate induces high yield vertical InAs NW SAE, which is attributed to a GaAs-like seeding layer formed at the InAs/Si interface. The role of Ga played in the III-V NW nucleation on Si is further discussed. It stabilizes the B-polarity on a non-polar Si (111) surface and enhances the nucleation. Therefore, gallium incorporation on a Si surface is identified as an important enabler for vertical InAs NW growth. A new method for high yield (>99%) vertical InAs NW SAE on Si using an InGaAs nucleation layer is proposed based on this study. [ABSTRACT FROM AUTHOR]

The effective bandgap is a crucial design parameter of heterojunction tunneling field-effect transistors. In this letter, we demonstrate a method to measure the effective bandgap directly from the band-to-band tunneling current of a heterojunction Esaki diode, of which we only require knowledge of the electrostatic potential profile. The method is based on a characteristic exponentially increasing current with forward bias, caused by sharp energy filtering at cryogenic temperature. We apply this method experimentally to a n+In0.53Ga0.47As/pGaAs0.5Sb0.5 Esaki diode and define requirements to apply it to other heterojunctions. [ABSTRACT FROM AUTHOR]

TCAD finite-element process simulations have been performed on Ge-channel n and pMOSFETs with embedded source/drain stressors or a strained Ge channel on a relaxed SiGe strain relaxed buffer (SRB), respectively, and compared with nanobeam diffraction strain measurements. While there is overall a good agreement between the simulated and experimental strain profiles, some deviations may occur, due to the presence of extended defects in the strain relaxed Ge buffer layers. This highlights the importance of selection of a strain-free reference in the relaxed Ge or SiGe SRB. [ABSTRACT FROM AUTHOR]