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This work advances the application of neural ordinary differential equations (ODEs) to circuit modeling. Prior works primarily utilized the recurrent neural network (RNN), which is a specific type of neural ODE. In this work, the capability of neural ODEs to represent different types of circuits is studied. Stability conditions are presented, both for neural ODEs in a standalone configuration and for neural ODEs with feedback connections, and practical techniques to impose the stability constraints during training are demonstrated. Based on the theoretical and experimental results, this work provides guidance as to when and how an accurate and stable neural ODE circuit model can be generated. [ABSTRACT FROM AUTHOR]

MOSFET breakdown voltage is strongly affected by the measurement conditions and the device layout. Substrate resistance has only a moderate influence on the breakdown voltage, and its dependence on device layout may be captured using a simple, semi-empirical model.

The studies have confirmed that, for ESD stress conditions; the time-to-breakdown of gate oxides as thin as 2nm can be predicted using the 1/E model. The 1/E model best fits the time-to-breakdown data. The report has stated that ESD protection networks must provide adequate voltage clamping for ultrathin gate oxide and must limit the voltage overshoot.

To enable accurate system-level electrostatic discharge (ESD) simulation, this article applies statistical learning to obtain I/O port models of the victim integrated circuits (ICs). A quasi-static I–V model derived using kernel regression can capture the circuit board dependency of the behavior observed at the I/O pin, regardless if there is snapback. The non-parametric kernel model can be reduced to a system-specific parametric model, which has smaller requirements for computing time and memory. In some cases, transient system-level ESD simulation may require the IC model to replicate the dynamic behavior of the nonlinear circuit. A recurrent neural network is demonstrated to be a suitable model in such cases. This article provides a detailed RNN training flow for IC pin modeling, and presents a Verilog-A implementation of the RNN for use with Simulation Program with Integrated Circuit Emphasis (SPICE)-type simulators. [ABSTRACT FROM AUTHOR]

Reliability is an important consideration during semiconductor technology development, which ensures that the performances of devices, circuits, and systems are maintained over a specified period of time, leading to successful products. Device reliability is at the core of overall product reliability, which continues to remain an important area of research and has attracted the attention of IEEE Transactions on Electron Devices (T-ED) authors and readers throughout the years. Device reliability can be classified into two broad areas: gradual drift of device performance over time or sudden failure, and both are of importance for logic, memory, RF, and power devices. Different aspects of device reliability are usually reported, such as the development of electrical or physical characterization methods, investigation and modeling of a particular phenomenon, impact of material and processes on reliability, and development of reliability tolerant technologies. [ABSTRACT FROM AUTHOR]

On-chip supply noise induced by power-on ESD is studied with the aid of on-chip monitor circuits and circuit simulation. The monitor circuits’ outputs provide information about the magnitudes of the ESD-induced supply noise. The supply noise monitor circuits were implemented on a 130-nm CMOS test chip. Voltage monitor circuits record the maximum and minimum supply voltage excursions. Flip-flop monitor circuits respond to a rapid voltage change at the supply. Circuit simulation is used to validate hypotheses about how the noise spreads throughout the power delivery network. [ABSTRACT FROM AUTHOR]

Hundreds of static discharges were directed to a circuit board containing a custom test chip, and the resulting soft-failures were recorded. The large time-derivative of the ESD current is the primary cause of soft-failures in this system. Magnetic coupling between traces and bondwires produces glitches at IO pins; the magnitude of these glitches is increased by the bounce of the on-chip supply net relative to the on-board supply. Additionally, logic upsets due to substrate current collection are observed when the equipment-under-test is tethered, i.e., when it has a low impedance path to Earth-ground. [ABSTRACT FROM PUBLISHER]

Adaptive active bias conditioning (AABC) is proposed for high-speed inputs/outputs (I/O) to mitigate the tradeoff between bandwidth and electrostatic discharge (ESD) reliability. During a component-level ESD event, the I/O transistors’ gate voltages are adaptively set to the values that maximize ESD robustness based on the ESD polarity. The AABC technique has no deleterious effect on signal integrity or power consumption, because its circuitry is located off the high-speed signal path and activated only during ESD. The efficacy of the protection scheme is validated on a 130-nm complementary metal-oxide semiconductor test chip. Thirty percent improved ESD resiliency is found from the charged device model and very-fast transmission line pulsing tests with only 10% area overhead, relative to a transceiver with the same I/O protection and no AABC. In order to diagnose ESD-induced failures, a new failure analysis method, which utilizes power-on I – V curves, is introduced. Using this method, the failed device can be inferred without the use of any destructive, physical failure analysis techniques. [ABSTRACT FROM PUBLISHER]

An inherent CDM–electrostatic discharge (ESD) hazard exists in T-coil circuits due to magnetic coupling from the pad to the receiver input. An “inductance halving” technique is proposed to reduce magnetic coupling during ESD, thereby canceling voltage overshoot. Receiver circuits with continuous-time linear equalizers are placed on a 65-nm CMOS test chip to evaluate the performance of the proposed T-coil in comparison with the conventional T-coil with secondary ESD protection. From the eye diagram test using 25-Gb/s pseudorandom bit sequence data, the receiver with an inductance-halving T-coil shows 1.8× higher and 29% wider eye opening, as compared with the receiver with a T-coil protected by a secondary ESD device. In a very fast transmission line pulsing test, both schemes achieve around an 8-A failure current, which demonstrates that the proposed T-coil can effectively protect receiver circuits against CDM-like ESD stresses. [ABSTRACT FROM PUBLISHER]

This paper presents a methodology to construct an equivalent circuit model of a packaged integrated circuit mounted on a field-induced charged device model electrostatic discharge tester. Circuit simulation is used to obtain the full-component current and voltage distributions. This paper focuses on predicting overvoltage stress at power domain crossing circuits. [ABSTRACT FROM PUBLISHER]

The physical effects that must be included in an accurate model of a silicon-controlled rectifier are discussed and compared with those for bipolar transistors. There are key differences in the modeling of the intrinsic silicon resistances and current gain for the two devices. Proper modeling of the underlying physics results in a compact model that is applicable over a wide range of current levels and is scalable. [ABSTRACT FROM AUTHOR]

The interdie signal interfaces in a three-dimensional (3-D) integrated circuit are vulnerable to overvoltage stress induced by charged device model (CDM) ESD, although they do not necessarily lie on any of the main ESD current paths. Circuit simulation shows that the magnitude of the stress is highly sensitive to the design of the ground distribution network on both the die and package levels. The placement of TSVs also impacts the stress generated at the interdie interfaces. If excessive, the voltage stress can be mitigated by placing a small ESD clamp at the interdie signal interface. A power supply domain may span multiple dies in a 3-D stack; this work investigates whether it is possible to remove the clamps from some of the dies in the stack to save silicon area without severely impacting the CDM reliability of the interdie interface circuits. [ABSTRACT FROM PUBLISHER]

An active rail clamp circuit provides protection against component-level ESD; this work explores the challenges associated with designing a rail clamp to additionally provide protection when the IC is powered on. The fast transient response required to protect against ESD makes it difficult to design a stable circuit and introduces tradeoffs between supply integrity and the clamping characteristic. This work presents an analysis of how these performance metrics are affected by device sizes. Interactions between a rail clamp circuit, which may be an active or passive clamp, and the parasitic elements of the package and board are examined; it is shown that these interactions may briefly power down the supply. [ABSTRACT FROM PUBLISHER]

This paper presents a computationally efficient methodology to predict the peak current stress experienced by a microelectronic component during a field-induced charge device model (FICDM) electrostatic discharge test. The methodology is applied to a variety of IC components in different types of packages; the peak current values obtained from simulations agree well with those obtained from FICDM measurements. [ABSTRACT FROM PUBLISHER]

It is demonstrated that if the compact model of a snapback-type device is calibrated using only pulsed I–V data, it may not correctly reproduce the device response to arbitrary electrostatic discharge (ESD) waveforms. Transient I–V measurements are demonstrated to improve the completeness of the device characterization and model verification. Given an accurately calibrated ESD compact model, circuit simulations may be used to identify device-tester interactions that have been reported to cause unexpected damage during ESD testing. The interaction between a snapback device and an ESD tester can be understood in the context of a relaxation oscillator. [ABSTRACT FROM PUBLISHER]

The on-chip stresses induced by various charged device model (CDM) test methods are compared at both the package and wafer levels. Test methods studied include field-induced CDM (FICDM), wafer-level CDM (WCDM2), capacitively coupled transmission-line pulsing (CC-TLP), and very fast TLP (VF-TLP). The generated stresses are compared on the basis of voltage monitor readings and integrated circuit (IC) functional failures. In general, core circuit failures induced by FICDM are replicated on the wafer level. Package-related parasitics can alter the externally measured FICDM current pulse relative to that delivered internal to the IC, causing miscorrelation with wafer-level testers. [ABSTRACT FROM PUBLISHER]