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Amorphous SiC (a-SiC) films are the most promising dielectric diffusion barriers to replace silicon nitride in Cu-interconnect technology. However, reclaim of wafers with a-SiC films is a challenge issue for mass production. In this paper, a novel wafer reclaim method is proposed. It is observed that a-SiC can be oxidized to Si[O.sub.2] in both dry [O.sub.2] and steam ambients at temperatures as low as 550 [degrees]C. The oxidation mechanism can be described by the Deal-Grove model that is traditionally used to describe oxidation of Si. Experiments prove that the oxidation process is clean and uniform. It is also observed that carbon doped oxide (CDO) films can be oxidized easily, too. Therefore, oxidation followed by HF etching could be a universal process to reclaim wafers deposited with a-SiC or CDO films. Since the oxidation rate of Si substrates at medium temperatures is much lower than that of a-SiC and CDO films, the oxidation process is virtually self-limiting. Compared with a traditional reclaim method based on wafer polishing, this universal oxidation-etching method exhibits great benefits in terms of low cost, high throughput, and the ability to perform nearly unlimited numbers of reclaim cycles. Index Terms--Amorphous silicon carbide, low dielectric constant, wafer reclaim.

Sacrificial layer (SACL) coating had been proposed to protect the sealing layer of underlying copper lines during trench etching as via-first scheme is employed for dual-damascene patterning. Because the coated SACL thickness depends on via size and via density, the process window is hard to identify. In this paper, the criteria for a successful SACL process are derived. A four-step procedure for SACL process developing is also proposed. It is suggested that shallow trench depth and medium etch rate selectivity between inter-metal-dielectric and SACL material are preferred. The SACL thickness in via can be adjusted by adjusting the overetching percentage at the SACL breakthrough step so that the criteria are satisfied. The validity of the proposed criteria is proved by the very high yield of via chains with via size ranging from 0.27 to 0.16[micro]m. It is concluded that the SACL process can be robust and can be employed to reduce the thickness of the capping layer effectively even beyond the 0.13-[micro]m technology node. Index Terms--Copper, dual-damascene, interconnections.

The oxidation rate of SiC can be greatly enhanced by pre-amorphization ion-implantation (PAI), and the PAI process has been employed to form the LOCal Oxidation of SiC (LOCOSiC) structure for device isolation in SiC integrated circuits (ICs). This work presents the study on the defect layer below the thermally grown SiO2 and the impact of the defect layer on devices. The deep-level transient spectroscopy (DLTS) analysis reveals that the defect layer consists lots of C vacancies and Si vacancies. The leakage current of the edge-intensive N+/P-junction exhibits stronger temperature dependence than that of the P+/N-junction. This result confirms that C vacancy is an effective lifetime killer in n-type SiC, but not in p-type SiC. Although these defects increase the leakage current of the edge-intensive SiC N+/P-junction by 42 times at 150 °C compared with the junction with conventional chemical vapor deposited (CVD) field oxide (FOX), the leakage current is still much lower than the required OFF-state current of ICs. The defect layer has high resistance, and it is hard to let the SiC surface into inversion state so that the threshold voltage of the field MOSFET is higher than ±24 V. [ABSTRACT FROM AUTHOR]

This work demonstrates a trench isolated lateral double-implanted MOSFET (LDMOS) on Si-face in 4H-silicon carbide (SiC). A device $\vphantom {_{\int _{}}}$ where ${L}_{\textit {ch}} = 0.8\,\,\mu \text{m}$ and ${L}_{d} = 12\,\,\mu \text{m}$ shows an ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ of 22.9 $\text{m}\Omega $ cm2 at a ${V}_{\text {GS}}$ of 20 V and a breakdown voltage (BV) of 1100 V, corresponding to a high BV2/ ${R}_{ \mathrm{\scriptscriptstyle ON},\text {sp}}$ of 55.5 MW/cm2. Devices that have different ${L}_{\text {ch}}$ , ${L}_{\text {JFET}}$ , ${L}_{d}$ , and P-top dose values are measured in order to investigate the effects of geometry on the static performance. Operations at 150 °C are measured to evaluate the temperature performance. Gate charge waveforms are also measured in order to include the switching performance in the evaluation. The ${R}_{ \mathrm{\scriptscriptstyle ON}} \times {Q}_{G}$ and ${R}_{ \mathrm{\scriptscriptstyle ON}} \times {Q}_{\text {GD}}$ values are calculated as 17.7 and $9.0~\Omega $ nC, respectively, which are promising for power-integrated circuit applications. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate CMOS integration that is fully compatible with a commercial double-implanted MOS (DMOS) process in 4H-SiC without requiring additional masks and cost. The characteristics of the NMOS, the PMOS, the CMOS inverter, and the ring oscillators are measured up to 175 °C. Propagation delay is reduced from 117 ns at room temperature to 17.8 ns at 175 °C, thanks to the increased current capability of both the NMOS and the PMOS. The body effect from the high substrate voltage on the PMOS is also investigated. The characteristics of the PMOS and the CMOS inverter are measured for a substrate voltage up to 800 V. The propagation delay for the ring oscillator is also measured when the substrate voltage is 300 V. [ABSTRACT FROM AUTHOR]

In this article, the degradation mechanism of the Ge N+-P junctions with a thin GeSn surface layer is investigated, aiming for source/drain (S/D) application in emerging field-effect transistors. GeSn is a promising channel material with high carrier mobility, which can offer a better performance of the field-effect transistors. By performing thermal annealing at different temperatures, the reverse-biased leakage current increases apparently when annealing temperature exceeds 550 °C. X-ray diffraction (XRD) analysis indicates most Sn atoms escape from lattice sites while secondary-ion mass spectroscopy (SIMS) analysis indicates enhanced Sn diffusion in Ge bulk after ion implantation. Therefore, a degradation model considering Sn-defects interaction is proposed to explain the degradation of junction leakage current and possible solution is proposed. [ABSTRACT FROM AUTHOR]

Hafnium oxide is one of the most promising high dielectric constant materials to replace silicon dioxide as the gate dielectric. To take the advantages of high dielectric constant of HfO[SUB2] thoroughly, the relatively low dielectric constant interfacial layer must be controlled carefully. In this work, the formation of an interfacial SiO[SUB2] layer at the HfO[SUB2]/Si interface was studied comprehensively. It is observed that during reactive sputtering deposition of the HfO[SUB2] layer, a very thick interfacial SiO[SUB2] layer, thicker than 3 nm, would be grown. O-radical signals, instead of O[SUB2]-radicl signals, are detected in the sputtering chamber. An O-radical enhanced oxidation model is proposed to explain such an unusual thick SiO[SUB2] layer. The adoption of a two-step deposition method, the thickness of interfacial SiO[SUB2] layer can be reduced only if the bottom Hf layer is thicker than 5 nm. However, the reduction of effective oxide thickness would be limited. Reoxidation of Hf film sounds a better choice. A 1.0-1.5-nm-thick interfacial SiO[SUB2] layer is still observed. This implies that the traced oxygen in the sputtering chamber plays a critical role on the formation of the interfacial layer. It is thus concluded that reactive sputtering is not a suitable method to prepare a HfO[SUB2] layer with a negligible interfacial SiO[SUB2] layer. Reoxidation of Hf film is a better choice, but the oxygen content in the sputtering chamber must be well controlled. [ABSTRACT FROM AUTHOR]

Nano-porous carbon doped oxide (CDO) is one of the potential low dielectric constant (low-k) materials that can achieve a dielectric constant as low as 2.2 and is expected to be suitable for the next generation multilevel interconnection. However, the electrical stability of CDO in contact with metal has not been addressed. In this work, metal ions’ drift into nano-porous CDO is investigated. It is observed that both the Al and Cu ions can be driven into porous CDO film easily by applying electric field or thermal treatment. This results in a severe flat band voltage shift of the metal/CDO/Si capacitor structure. It is hypothesized that the lacking formation of self-limited aluminum oxide between Al and CDO film make Al ions drift into CDO. The adhesion of Al and Cu to CDO is also very poor. A physical model, combining weak dielectric polarization and metal ions drift, was proposed to explain the observed electrical instability. The inconsistent results regarding the Al/porous low-k/Si structure reported in the previous literatures can also be explained with this proposed model. Fortunately, TaN, as a common diffusion barrier material for Cu interconnect structure, is proved to have good adhesion to CDO. Negligible metal ions would drift in CDO during electrical stress. It is concluded that with a suitable diffusion barrier, such as TaN, CDO is still a very promising material for next generation Cu-interconnect technology. © 2003 American Institute of Physics. [ABSTRACT FROM AUTHOR]

It has been reported that Ar plasma treatment on the n-type 4H-SiC surface before metal deposition can reduce the contact resistance. In that work, the n+ layer was formed by ion implantation at room temperature (RT). In this paper, it is found that Ar plasma treatment on the high-temperature (HT) implanted n+ layer degrades but not improves the contact resistance. A composition of RT/low-energy and HT/high-energy ion implantation can achieve low sheet resistance of the n+ layer and low contact resistance simultaneously. A twofold mechanism is proposed that the amorphous interfacial layer produced by Ar plasma treatment reduces the Schottky barrier height and the defects generated by RT ion implantation enhance current conduction by trap-assisted tunneling. [ABSTRACT FROM AUTHOR]

The effects of Ar inductively coupled plasma (ICP) treatment followed by a 600 °C–1000 °C rapid thermal annealing (RTA) on the n-type 4H-silicon carbide (SiC) Schottky-barrier diodes and n+-implanted ohmic contacts were investigated. The ICP treatment created a 3-nm-thick, sp2–C-rich, and amorphous layer at the SiC surface. The RTA repaired the bombardment-induced damages before metal deposition to avoid current degradation. This ICP + RTA-treated surface strongly pinned the Schottky-barrier height (SBH) at a minimum of 0.88 eV. In theory, the low SBH is beneficial to decrease the specific contact resistance ($\rho _{C}$). $\rho _{C}$ of the ICP + RTA-treated Ti ohmic contacts decreased to lower than $10^{-{5}} \,\,\Omega \cdot \text {cm}^{{2}}$ after 400 °C postmetal deposition annealing (PMDA). However, the additional O atoms, fixed in the amorphous layer by RTA, affected the $\rho _{C}$ reduction. Fortunately, due to the chemical affinity for O of Ti, the in-diffused Ti could contend for the O atoms against the Si–O bonds during the PMDA. Therefore, the oxidized barricade was decomposed gradually, leading to the lowest $\rho _{C}$ , $1.3\times 10^{-{6}} \,\,\Omega \cdot \text {cm}^{{2}}$ , after 600 °C PMDA. The lowest $\rho _{C}$ is $25\times $ and $8\times $ lower than that of the Ni silicide and the nontreated Ti contacts, respectively, at the same doping concentration. [ABSTRACT FROM AUTHOR]

Presents a study that investigated the characteristics of PtSi-silicided p[sup+] n shallow junctions fabricated by implanting BF[sub2][sup+] ions and low-temperature furnace annealing. Benefits of self-aligned silicide process; Procedures in preparing the samples; Summary of the sample identification number and the key process conditions.

Presents a study that investigated low-termperature reaction of thin-film platinum with silicon. Sheet resistance measurement of silicide formation sequence; Use nitrogen furnace; X-ray diffraction analysis.

Studies the capability of using platinum and platinum-silicon in the ion implantation through metal or metal silicide technique. Procedure of the experiment; Measured electrical characteristics of the sample; Results of the leakage current analysis; Conclusion.

Presents a technique based on the ion implantation of fluoride ion or species containing fluoride atoms into the silicon substrate underneath the platinum silicide (PtSi) layer. Function of PtSi; Material analysis of the PtSi under various annealing conditions; Silicide film characteristics.

The effects of Ar inductively coupled plasma (ICP) treatment on the Ohmic contact on n+-implanted SiC were investigated in this letter. The effects of ICP treatment were negligible on the Ni-silicide contact, because the treated surface layer was consumed during silicide formation. However, for the Ti contact, as the annealing temperature increased, the ion-bombardment-induced damage layer transformed to a uniform amorphous C-rich layer, and the specific contact resistance of the ICP-treated Ti contact decreased to 8.3\times 10^-7~\Omega -cm2 after 600 °C annealing. This is the lowest value achieved at such a low process temperature. Thus, appropriate ICP treatment and annealing can be used to form low-resistivity Ohmic contacts with a lower thermal budget that are comparable with Ni-based silicide Ohmic contacts. [ABSTRACT FROM AUTHOR]

Effects of hot phosphorus (P) implantation on the NiGe-contacted Ge n+/p junction are studied in this work. At an adequately high ion-implantation temperature (150°C), the P depth profiles of the hot-implanted samples are similar to that of the room-temperature implanted ones. Hot P implantation is demonstrated effectively in reducing ion implantation induced defect formation and suppressing nickel atoms diffusion. Therefore, hot P implantation is efficient in lowering junction leakage and excellent junction characteristics exhibiting \sim 1\times 10^6~J \mathrm{\scriptscriptstyle ON}/J \mathrm{\scriptscriptstyle OFF} ratio is achieved. [ABSTRACT FROM PUBLISHER]

In this letter, the electrical properties of local oxidation of silicon (LOCOS) field oxide formed on 4H-SiC are reported. Moreover, unlike the conventional Si LOCOS process, a simpler method based on Ar preamorphization implantation is proposed. In addition to direct characterization of the field oxide, device properties achieved using LOCOS isolation are compared with those achieved using the conventional chemical vapor deposition oxide isolation to clarify the impact of isolation technology. The results of this letter would be insightful for silicon-carbide-based very-large-scale integration technology. [ABSTRACT FROM PUBLISHER]

Presents a study that formed a shallow silicided n[sup+]p junction by implanting arsenic ions into platinum or platinum silicide films followed by low-temperature furnace annealing in the nitrogen ambient. Benefits from implanting a dopant through metal/silicide; Reason that the ion implantation through metal sample exhibits smaller leakage than ion implantation through metal silicide sample; Annealing temperature dependence of the forward ideality factor.

Presents information on a study which examined proposed mechanisms on the role of fluorine in the thermal stability of silicide/silicon structures. Background of the study; Methodology of the study; Results and discussion.

Tunnel field-effect transistor (FET) is a promising candidate in ultralow-power applications due to its distinct operation mechanism, namely band-to-band tunneling (BTBT). The integration of different low-bandgap materials is explored extensively to improve the ON-state BTBT current of the tunnel FETs. The epitaxial tunnel layer (ETL) tunnel FET integrated with the hetero-material system is a promising structure due to its process compatibility with CMOS technologies. In the scenario of n-channel operation, the concept of the suppression of the low electric field BTBT is proposed. The SiGe/Si hetero-material system is applied to the n-channel ETL tunnel FET to suppress the low electric field BTBT by the ETL band engineering. The optimized ETL tunnel FET exhibits a high ON-state BTBT current due to the low bandgap material in the ETL. The average SS behavior is also further improved by suppressing the low electric field BTBT. In this study, the design concept and the device parameters of the n-channel ETL tunnel FET are discussed in detail. The performances of the complementary ETL tunnel FETs using the SiGe/Si hetero-material system are also provided to enrich the value of the ETL tunnel FET in the circuit applications. [ABSTRACT FROM PUBLISHER]

The 3-D NAND flash memory architectures will be a future trend, because they provide high memory capacity without aggressively scaling down. A vertical-gate (VG) structure composed of polysilicon (poly-Si) channels is a promising 3-D structure that could facilitate realizing an extremely tight-pitch NAND flash memory cell with high memory capacity. However, the variability of the VG memory cell induced by grain boundaries in the poly-Si channels is a major concern for aggressively scaled-down memory cells. In this paper, a discrete-trap approach is applied to emulate the real trap effects in a 3-D memory cell, and the 3-D structure geometry effects and the variation in the threshold voltage ( VT) induced by the discrete grain-boundary traps are studied. Various \Delta VT behaviors related to the structure geometry and trap position are examined. The effect of varying the body thickness on the \Delta VT is stronger than that of varying the channel width. This paper presents various cases for using the discrete-trap approach to study the variability of VT in 3-D VG memory cells. [ABSTRACT FROM AUTHOR]

The impact of adjacent word-line's pass gate voltage interference on charge-trapping (CT) NAND Flash is extensively studied in this paper. From our previous work with a 38-nm half-pitch BE-SONOS NAND Flash device, we found that the threshold voltage significantly decreases with increasing pass gate voltage during reading. This observation is in contrary to the common belief that the CT NAND devices are immune to interference. In this paper, we further evaluate the pass gate voltage interference on 3-D CT NAND Flash, which is the most promising path for the future NAND Flash industry. Owing to the superior gate control ability in the double-gate architecture, the commonly observed pass gate voltage interference due to pitch scaling is suppressed. Stronger gate control ability also restrains the impact of field penetration in devices with narrow channel width. In 3-D CT NAND Flash, the thinner channel can also provide better gate control ability, which, in turn, results in smaller pass gate voltage interference. [ABSTRACT FROM PUBLISHER]

The 3-D stacking of multiple layers of NAND using thin-film transistor (TFT) devices is widely accepted as the next step in continuing NAND Flash scaling. Low mobility and reliability problems are two well-known concerns regarding TFT devices. However, another important implication of using TFT devices is that the Vt variation induced by randomly distributed grain boundaries degrades the array performance. In this paper, an extensive TCAD simulation was conducted to systematically investigate how grain boundary generated traps affect NAND Flash devices. Minimizing the density of grain boundary traps is crucial for array performance. In addition, optimal gate control ability reduces the impact of grain boundaries. Thus, using double gate architecture in vertical gate 3-D NAND is favorable. Furthermore, when pitch is scaled in the future, device exhibiting smaller channel thickness should be used to increase the gate control. [ABSTRACT FROM PUBLISHER]

Highlights: [•] Comparing the performance of CNT-interconnects with four combinations. [•] Improving the electrical properties and reliabilities by double layer structures. [•] Demonstrating the size and structure percolative conductance of CNT-interconnects. [•] Proposing further work for the CNT-interconnect optimization. [ABSTRACT FROM AUTHOR]

The tunnel field-effect transistor (FET) is a promising candidate for use in ultralow-power applications because of its distinct operation principle, namely, band to band tunneling (BTBT). However, the ON-state current of the tunnel device is extremely low because of the poor tunneling efficiency of the BTBT. In this paper, a novel epitaxial tunnel layer (ETL) structure combining vertical tunneling orientation was proposed. The ETL structure performs more favorably than does the traditional lateral tunnel FET structure in an all-silicon device. By using low bandgap materials in the ETL, the ON-state BTBT current increases and an extremely low intrinsic OFF-state current is maintained because of the small low bandgap junction area. The onset voltage of the bipolar BTBT can also be postponed using ETL band engineering. The optimized parameters of the Six\rm Ge1\-{\rm x} ETL tunnel FET structure increase the ON-state current 10^7\--10^8 times compared with that of the traditional lateral silicon tunnel FET. The minimal subthreshold swing (SS) and ON/OFF current ratio also improve, the SS decreases from 47 mV/decade to 29 mV/decade, and the ON/OFF current ratio increase from 10^5 to 10^10. In this paper, the effects of the ETL parameters on device performance are discussed in detail. [ABSTRACT FROM PUBLISHER]

Abstract: In this paper, a simple and low temperature fabrication process, slow spin rate coating and dry etching, is proposed to construct the CNT-interconnects for future VLSI interconnect applications. Two sets of CNT-interconnects named width and length varying interconnects were fabricated to investigate the characterization of size dependent conductivity of CNT-interconnects. Not only the amount of the CNT solution spin-coated for forming the CNT networks but also the area of CNT-interconnect regime would affect the conductance, variation, and conductive probability of CNT-interconnects. The yield of working CNT-interconnects does not show direct relation with the conductive probability or the amount of the CNT solution for CNT network formation. Based on the percolation theory, we characterize the average conductance of size-varying CNT-interconnects by three regions: percolation region, power region and linear region. In addition, as the density within a specified CNT-interconnect regime accumulates, the conductive behavior would be eventually characterized as a conventional resistor. [Copyright &y& Elsevier]

Abstract: Carbon nanotube field effect transistors (CNTFETs) have been considered as one of the potential candidates for nanoelectronics beyond Si CMOS. However, it is not easy to have high performance CNTFETs with high yield currently. In this work, we proposed a local bottom-gate (LBG) CNTFETs combined with a novel device concept and optimized process technologies. High performance of CNTFET with low subthreshold swing of 139mV/dec, high transconductance of 1.27μS, and high I on/I off ratio of 106 can be easily obtained with Ti source/drain contact after a post annealing process. Record high yield of 74% has been demonstrated. On the basis of the proposed process, lots of high performance CNTFETs can be obtained easily for advanced study on the electrical characteristics of CNTFETs in the future. [Copyright &y& Elsevier]

Abstract: Multi-gate non-volatile memory (NVM) cell is a promising approach in the next generation. In this work, the performance of NVMs using nanocrystals (NCs) and nanowires (NWs) as charge trapping materials were evaluated by three-dimensional simulation. It is found that the NWs located at different positions have different charge injection speeds. And the NW density will strongly affect the charge injection efficiency. The NW at channel center can result in large memory window and acceptable channel controllability. Although the total charges injected into NWs is lower than that injected into NCs under the same programming condition, using NWs as charge trapping material exhibits larger memory window and better channel controllability. It is suggested that the NW is a better choice than NC to be charge storage material from the perspective of memory performance. [Copyright &y& Elsevier]

The gate-to-source capacitance ( C\mathrm {GS}) in the p-channel tunnel FET (pTFET) with a Ge epitaxial tunnel layer (ETL) structure is investigated. The characteristic of C\mathrm {GS} is revealed and studied with various frequencies and temperatures. Due to the highly efficient band-to-band tunneling (BTBT) in the Ge ETL pTFET, the minority carriers for the source can be generated by the BTBT process and can respond with the gate voltage. Therefore, the contribution of C\mathrm {GS} to the total gate capacitance in the ON-state would increase, which results in a decrease of the gate-to-drain capacitance. This property is beneficial to the suppression of the Miller capacitance effect on the TFET-based circuit. [ABSTRACT FROM AUTHOR]

A CMOS process compatible p-channel tunnel field-effect transistor (TFET) with an epitaxial tunnel layer (ETL) structure is demonstrated experimentally. The fabricated ETL p-TFET exhibits high tunneling current ( I\mathrm{\scriptscriptstyle ON}\sim 0.17~\mu \text{A}/\mu \text{m} at \vert VG\vert =0.5 V after V\mathrm {TH} adjustment), ultra-low OFF-state current, and good average subthreshold swing (S.S. $\sim 100$ mV/ decade up to 10 nA/ \mu \text{m} ). Overall performance exceeds that of the current state-of-the-art Ge-based planar p-TFETs. [ABSTRACT FROM AUTHOR]

Lower saturation current flowing through the same cell twice is a major drawback of vertical stack array transistor architecture. A loading effect further reduces the saturation current and causes higher threshold voltage. A simple word line cut process not only doubles the bit density to reduce the bit cost, but also reduces the loading effect. This letter used an assisted gate can to further enhance the saturation current with acceptable cell characteristics. Furthermore, the major parameters that influence the performance of the vertical stack array transistor architecture were studied extensively. An ultra-high density three-dimensional NAND flash architecture can be used in the future NAND flash industry. [ABSTRACT FROM PUBLISHER]

In this letter, we present a high performance Ge n-channel metal-oxide-semiconductor field-effect transistor (MOSFET) with a NiGe Schottky junction source/drain fabricated using phosphorus dopant segregation. Phosphorus atoms were implanted into NiGe and then driven toward the NiGe/p-Ge interface to depin the Fermi level and form a Schottky junction. A high effective barrier height (\PhiBp) of 0.57 eV, resulting in a high junction current ratio of >10^4 at the applied voltage \vertVa\vert=\pm1~V. The nMOSFET exhibited a high ION/IOFF ratio of \sim8\times 10^3~(ID), \sim10^5~(IS), and a subthreshold swing of 138 mV/decade. The nMOSFET developed in this letter exhibited greater transconductance and a drain leakage current that is more than two orders of magnitude lower compared with nMOSFETs with the conventional n^+/p junction. [ABSTRACT FROM AUTHOR]