101 results on '"Tsui, Bing-Yue"'
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2. Defect Inspection Techniques in SiC
3. Time-dependent dielectric breakdown of gate oxide on 4H-SiC with different oxidation processes
4. Schottky barrier diodes isolated by local oxidation of SiC (LOCOSiC) using pre-amorphization implantation technology
5. Well-behaved 4H-SiC PMOSFET with LOCal oxidation of SiC (LOCOSiC) isolation structure and compromised gate oxide for Sub-10V SiC CMOS application
6. Reduction of Contact Resistivity by Nano-Textured Contact
7. Strong Fermi-level pinning induced by argon inductively coupled plasma treatment and post-metal deposition annealing on 4H-SiC
8. A study on NiGe-contacted Ge n+/p Ge shallow junction prepared by dopant segregation technique
9. Effect of surface preparation on the radiation hardness of high-dielectric constant gate dielectric
10. Design, Process, and Characterization of Complementary Metal-Oxide-Semiconductor Circuits and Six-Transistor Static Random-Access Memory in 4H-SiC.
11. A novel wafer reclaim method for amorphous SiC and carbon doped oxide films
12. Process sensitivity and robustness analysis of via-first dual-damascene process
13. A Study on the Isolation Ability of LOC al O xidation of SiC (LOCOSiC) for 4H-SiC CMOS Process.
14. 1100 V, 22.9 mΩcm 2 4H-SiC RESURF Lateral Double-Implanted MOSFET With Trench Isolation.
15. Demonstration of CMOS Integration With High-Voltage Double-Implanted MOS in 4H-SiC.
16. Impact of interface nature on deep sub-micron Al-plug resistance
17. Plasma charging damage during contact hole etch in high-density plasma etcher
18. Degradation Mechanism of Ge N+-P Shallow Junction With Thin GeSn Surface Layer.
19. Formation of interfacial layer during reactive sputtering of hafnium oxide.
20. Metal drift induced electrical instability of porous low dielectric constant film.
21. Effect of Ion-Implantation Temperature on Contact Resistance of Metal/n-Type 4H-SiC With Ar Plasma Treatment.
22. Effects of Rapid Thermal Annealing on Ar Inductively Coupled Plasma-Treated n-Type 4H-SiC Schottky and Ohmic Contacts.
23. Formation of PtSi-contacted p+n shallow junctions by BF+2 implantation and low-temperature furnace annealing.
24. Low-temperature reaction of thin-film platinum (≤300 Å) with (100) silicon.
25. Formation and characterization of a PtSi contacted n+p shallow junction.
26. High-temperature stability of platinum silicide associated with fluorine implantation.
27. Reduction of Specific Contact Resistance on n-Type Implanted 4H-SiC Through Argon Inductively Coupled Plasma Treatment and Post-Metal Deposition Annealing.
28. Reduced Junction Leakage by Hot Phosphorus Ion Implantation of NiGe-Contacted Germanium n+/p Shallow Junction.
29. A reliable Schottky barrier height extraction procedure.
30. Characterization of LOCOS Field Oxide on 4H-SiC Formed by Ar Preamorphization Ion Implantation.
31. Formation of 0.1-μm n+p junction by As+ implantation through Pt or PtSi film.
32. Role of fluorine atoms on the thermal stability of the silicide/silicon structure.
33. A comparison study on the Al-based interfacial layers for Ge MIS devices.
34. Band Engineering to Improve Average Subthreshold Swing by Suppressing Low Electric Field Band-to-Band Tunneling With Epitaxial Tunnel Layer Tunnel FET Structure.
35. Evaluation of ultra-low specific contact resistance extraction by cross-bridge Kelvin resistor structure and transmission line method structure.
36. A Novel Approach Using Discrete Grain-Boundary Traps to Study the Variability of 3-D Vertical-Gate NAND Flash Memory Cells.
37. Impact of \Vpass Interference on Charge-Trapping NAND Flash Memory Devices.
38. Modeling the Impact of Random Grain Boundary Traps on the Electrical Behavior of Vertical Gate 3-D <sc>NAND</sc> Flash Memory Devices.
39. High performance of CNT-interconnects by the multi-layer structure.
40. Six\rm Ge1\-{\rm x} Epitaxial Tunnel Layer Structure for P-Channel Tunnel FET Improvement.
41. Characteristics of size dependent conductivity of the CNT-interconnects formed by low temperature process.
42. Integral contact process in submicron technology.
43. A process for high yield and high performance carbon nanotube field effect transistors
44. Multi-gate non-volatile memories with nanowires as charge storage material
45. Investigation Into Gate-to-Source Capacitance Induced by Highly Efficient Band-to-Band Tunneling in p-Channel Ge Epitaxial Tunnel Layer Tunnel FET.
46. Experimental Demonstration of p-Channel Germanium Epitaxial Tunnel Layer (ETL) Tunnel FET With High Tunneling Current and High ON/OFF Ratio.
47. Ultra-High Bit Density 3D NAND Flash-Featuring-Assisted Gate Operation.
48. Simulation study of carbon nanotube field emission display with under-gate and planar-gate structures.
49. A new procedure to extract ultra-low specific contact resistivity.
50. Enhancing the Performance of Germanium Channel nMOSFET Using Phosphorus Dopant Segregation.
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