Search

Interconnect RC delay, predominantly affected by the effective dielectric constant (k-value) and by the copper resistivity ([rho] cu), is an important performance metric for back-end-of-line (BEOL) process assessment. As process technology scales, interpretation of fundamental process-induced RC delay variations becomes a challenge as the relative importance of statistical process-induced fluctuations (variation of critical dimensions during plasma etching of low-k materials, line profiles, thickness nonuniformity, etc.) grows rapidly and begins to show. A more accurate interpretation of experimental data and prediction of future performance trends requires a more realistic assessment that accounts for such statistical fluctuations. In this paper, an inventory of the most common possible sources of statistical process-induced RC delay variations is made, parameterized, and subsequently used to generate a realistic 2-D interconnect model from which, R and C, and thereby RC delay, are computed. For both wire resistivity and RC, response surface models (RSM) are subsequently generated based on the results of a full factorial design-of-experiment analysis with these input parameters. Finally, based on the RSMs, an improved methodology of interconnect performance evaluation is proposed. Index Terms--Capacitance, copper, delay circuit, modeling, RC circuits, resistivity, variability.

The backgating effect on trench-isolated enhancement-mode p-GaN devices fabricated on 200-mm GaN-on-SOI was investigated. We show that to minimize the backgating effect in the monolithically integrated half-bridge, the sources of both the low side and high side need to be connected to their respective fully isolated Si(111) device layers to keep the substrates and the sources at equipotential. [ABSTRACT FROM AUTHOR]

This paper presents an extensive investigation of the impact of the resistivity of the silicon substrate on the vertical leakage and charge trapping in 200 V GaN-on-Si enhancement-mode high-electron mobility transistors. Three wafers having different substrate resistivities were submitted to combined DC characterization, step-stress experiments, and electroluminescence (EL) analysis. The results described within this paper demonstrate that: 1) the use of a highly resistive silicon substrate can increase the vertical breakdown voltage of the transistors, due to the fact that the voltage drop on the GaN buffer is mitigated by the partial depletion of the substrate (this latter causes a plateau region in the drain to substrate I–V characteristic) and 2) highly resistive substrate results in stronger trapping effects, due to the capacitance of the depleted substrate and the resulting backgating effects. The results described within this paper indicate that the choice of the resistivity of the substrate is the result of a tradeoff between high breakdown voltage (that could be in principle achieved through a highly resistive substrate) and the minimization of trapping processes (which can be hardly obtained with a resistive substrate). [ABSTRACT FROM AUTHOR]

To get a better insight into the vertical leakage mechanism of GaN-on-Si, the carrier transport from n+, n, p+, and p-Si(111) substrates through the AlN nucleation layer was investigated. A plateau in the current-voltage curve was found only for the AlN/p-Si heterojunction due to depletion of the p-Si substrate. Detailed study illustrated that it was the leaky AlN that cannot effectively block the increasing amount of electrons in the inversion layer at the interface and triggered the depletion. Temperature-dependent characterization suggested that the forward vertical leakage mechanism of AlN/Si could be explained sequentially by Ohm’s law, space-charge-limited conduction, variable-range hopping, and trap-assisted tunneling. A model involving shallow donor traps, interface traps, and deep level traps was proposed to explain the leakage characteristics. This paper shows that the carrier concentration of the Si substrates strongly impacts the vertical leakage characteristics, and also that the carrier transport from the Si substrate through the AlN nucleation layer is heavily influenced by traps. [ABSTRACT FROM AUTHOR]

This paper demonstrates and investigates the time-dependent vertical breakdown of GaN-on-Si power transistors. The study is based on electrical characterization, dc stress tests and electroluminescence measurements. We demonstrate the following original results: 1) when submitted to two-terminal (drain-to-substrate) stress, the AlGaN/GaN transistors show a time-dependent degradation process, which leads to the catastrophic failure of the devices; 2) time-to-failure follows a Weibull distribution and is exponentially dependent on stress voltage; 3) the degradation mechanism is strongly field dependent and weakly thermally activated, with an activation energy of 0.25 eV; and 4) emission microscopy suggests that vertical current flows under the whole drain area, possibly through extended defects. The catastrophic failure occurs at random positions under the drain contact. The time-dependent failure is ascribed to a percolation process activated by the high-electric field that leads to the generation of localized shunt paths between drain and substrate. [ABSTRACT FROM PUBLISHER]

In this paper, fully recessed-gate GaN MISFETs with two different gate dielectrics, i.e., plasma-enhanced atomic layer deposition (PEALD) SiN and ALD Al2O3 gate dielectric, are used to study the origin of positive bias temperature instability (PBTI). By employing a set of dedicated stress-recovery tests, we study PBTI during the stress and relaxation. Hence, a defect band model with different distributions of defect levels inside the gate dielectric is proposed, which can excellently reproduce the experimental data and provide insightful information about the origin of PBTI in GaN MISFETs. The results indicate that the serious PBTI in the device with PEALD SiN is mainly due to a wide distribution of defect levels ( \sigma \sim 0.67 eV), centered below the conduction band of GaN ( E_{C} -0.05 eV), and can be easily accessed by the channel carriers already at a low-gate voltage. On the other hand, ALD Al2O3 gate dielectric shows a narrower distribution of defects ( \sigma \sim 0.42$ eV), which are far from the conduction band of GaN ( E_{C} +1.15 eV). This observations explain the improved PBTI reliability observed in devices with ALD Al2O3. [ABSTRACT FROM AUTHOR]

In this work, we have systematically investigated the technique of low-temperature AlN interlayer in MOCVD growth of double heterojunction high-electron-mobility transistors buffer stacks on 200 mm Si (111) substrates. We have demonstrated that a continuous compressive stress can be maintained by insertion of interlayers which compensated a large tensile stress during cooling for a thick buffer. This eventually led to a low wafer bow and a good surface quality that enabled wafers with full device stack meeting the specifications for processing in our 200 mm CMOS pilot line. We also demonstrated at both forward and reverse bias conditions a significantly improved vertical buffer breakdown voltage (which is defined at a leakage current of 1 µA/mm² in the present work) of >500 V at 25 °C and >300 V at 150 °C, respectively. [ABSTRACT FROM AUTHOR]

This letter reports an in-depth study of the negative threshold voltage instability in GaN-on-Si metal-insulator–semiconductor high electron mobility transistors with partially recessed AlGaN. Based on a set of stress/recovery experiments carried out at several temperatures, we demonstrate that: 1) operation at high temperatures and negative gate bias (−10 V) may induce a significant negative threshold voltage shift, that is well correlated to a decrease in on-resistance; 2) this process has time constants in the range between 10–100 s, and is accelerated by temperature, with activation energy equal to 0.37 eV; and 3) the shift in threshold voltage is recoverable, with logarithmic kinetics. The negative shift in threshold voltage is ascribed to the depletion of trap states located at the SiN/AlGaN interface and/or in the gate insulator. [ABSTRACT FROM PUBLISHER]

In this paper, a further leakage reduction of AlGaN/GaN Schottky barrier diodes with gated edge termination (GET-SBDs) has been achieved by optimizing the physical vapor deposited TiN as the anode metal without severe degradation of on-state characteristics. The optimized GET-SBD multifinger power diodes with 10 mm anode width deliver \sim 4 A at 2 V and show a median leakage of 1.3 \mu \text{A} at 25 °C and 3.8 \mu \text{A} at 150 °C measured at a reverse voltage of −200 V. The temperature-dependent leakage of Si, SiC, and our GaN power diodes has been compared. The breakdown voltage (BV) of GET-SBDs was evaluated by the variation of anode-to-cathode spacing ( L\mathrm{ AC} ) and the length of field plate. We observed a saturated BV of \sim 600 V for the GET-SBDs with L\mathrm{ AC} larger than 5 \mu \textm . The GET-SBD breakdown mechanism is shown to be determined by the parasitic vertical leakage current through the 2.8 \mu \textm -thick buffer layers measured with a grounding substrate. Furthermore, we show that the forward voltage of GET-SBDs can be improved by shrinking the lateral dimension of the edge termination due to reduced series resistance. The leakage current shows no dependence on the layout dimension LG (from 2 to 0.75 \mu \textm ) and remains at a value of $\sim 10$ nA/mm. The optimized Au-free GET-SBD with low leakage current and improved forward voltage competes with high-performance lateral AlGaN/GaN SBDs reported in the literature. [ABSTRACT FROM PUBLISHER]

In this paper, three electrical techniques (frequency dependent conductance analysis, AC transconductance (AC-gm), and positive gate bias stress) were used to evaluate three different gate dielectrics (Plasma-Enhanced Atomic Layer Deposition Si3N4, Rapid Thermal Chemical Vapor Deposition Si3N4, and Atomic Layer Deposition (ALD) Al2O3) for AlGaN/GaN Metal-Insulator- Semiconductor High-Electron-Mobility Transistors. From these measurements, the interface state density (Dit), the amount of border traps, and the threshold voltage (VTH) shift during a positive gate bias stress can be obtained. The results show that the VTH shift during a positive gate bias stress is highly correlated to not only interface states but also border traps in the dielectric. A physical model is proposed describing that electrons can be trapped by both interface states and border traps. Therefore, in order to minimize the VTH shift during a positive gate bias stress, the gate dielectric needs to have a lower interface state density and less border traps. However, the results also show that the commonly used frequency dependent conductance analysis technique to extract Dit needs to be cautiously used since the resulting value might be influenced by the border traps and, vice versa, i.e., the gm dispersion commonly attributed to border traps might be influenced by interface states. [ABSTRACT FROM AUTHOR]

In this work we report on the three dominant trapping mechanisms affecting the dynamic performance of a double-heterostructure GaN-based MIS-HEMT grown on silicon substrate. In the OFF-state, with high drain voltage and pinched-off 2DEG, the dominant mechanism is the charge-trapping in the gate-drain access region caused by the transversal drain-to-substrate potential. This effect causes the dynamic increase of the ON-resistance, and is positively temperature-dependent, thus of great concern for high-temperature operation. In the SEMI-ON-state, due to the presence of high VDS and relatively high IDS, an additional trapping mechanism emerges, involving the injection of hot electrons from the 2DEG into trap states located in the GaN-buffer or in the AlGaN barrier. This mechanism, critical in hard-switching operations, affects both the ON-resistance and the VTH. Finally, when the gate is positively biased (gate overdrive state) trapping of electrons happens in the gate dielectric layer(s), leading to strong metastable VTH instabilities. [ABSTRACT FROM AUTHOR]

This letter demonstrates that GaN-based MIS-HEMTs submitted to stress with high-temperature, high drain bias, and constant source current (HTSC stress) may show degradation modes that are not detectable during standard high temperature reverse bias (HTRB) stress. Based on a number of stress/recovery experiments, we demonstrate the following novel results: 1) the combined presence of high drain bias and constant drain–source current (HTSC stress) can lead to a significant increase in ON-resistance ( R\mathrm{\scriptscriptstyle ON} ) that is not detected under conventional HTRB stress; 2) R\mathrm{\scriptscriptstyle ON} increases without changes in the threshold voltage, indicating that charge trapping takes place in the access regions, and not under the gate; 3) the R\mathrm{\scriptscriptstyle ON} increase has a monotonic dependence on the source current flowing during stress; and 4) for the same stress current level, the R\mathrm{\scriptscriptstyle ON} increase has a negative dependence on temperature. The strong correlation between R\mathrm{\scriptscriptstyle ON} increase and source current and the negative temperature coefficient strongly support the hypothesis that trapping originates from the injection of hot electrons toward the gate–drain access region. [ABSTRACT FROM PUBLISHER]

This paper reports on an extensive analysis of the trapping processes and of the reliability of experimental AlGaN/GaN MIS-HEMTs, grown on silicon substrate. The study is based on combined pulsed characterization, transient investigation, breakdown, and reverse-bias stress tests, and provides the following, relevant, information: 1) the exposure to high gate-drain reverse-bias may result in a recoverable increase in the on-resistance (RON), and in a slight shift in threshold voltage; 2) devices with a longer gate-drain distance show a stronger increase in RON, compared to smaller devices; 3)current transient measurements indicate the existence of one trap level, with activation energy of 1.03 ± 0.09 eV; and 4) we demonstrate that through the improvement of the fabrication process, it is possible to design devices with negligible trapping. Furthermore, the degradation of the samples was studied by means of step-stress experiments in off-state. Results indicate that exposure to moderate-high reverse bias (<; 250 V for LGD = 2 μm) does not induce any measurable degradation, thus confirming the high reliability of the analyzed samples. A permanent degradation is detected only for very high reverse voltages (typically, VDS = 260-265 V, on a device with LGD = 2 μm stressed with VGS = - 8 V) and consists of a rapid increase in gate leakage current, followed by a catastrophic failure. EL measurements and microscopy investigation revealed that degradation occurs close to the gate, in proximity of the sharp edges of the drain contacts, i.e., in a region where the electric field is maximum. [ABSTRACT FROM AUTHOR]

Au-free GaN-based metal–insulator–semiconductor high electron-mobility transistors grown on 150-mm Si substrates are reported. The device characteristics for three different processes are compared: an ohmic-first and a gate-first process with Al2O3-only as gate dielectric and a novel approach with a bilayer gate dielectric stack consisting of Si3N4 and Al2O3. The Si3N4 layer was deposited in situ in the metal-organic chemical vapor deposition reactor in the same growth sequence as the rest of the epilayer stack and the Al2O3 layer was deposited ex situ by atomic layer deposition. Only the process with the bilayer gate dielectric results in robust devices with a breakdown voltage >600~V. The ohmic contact resistance for Au-free Ti/Al/W metallization scheme is <1~\Omega\cdotmm. The devices show high maximum output current density (>0.4~A/mm); and low gate and drain leakage (<10^-10~A/mm). The maximum pulsed mode drain–source current of power bars with 20 mm gate width is 8 A. The specific on-state resistance is 2.9 m \Omega\cdotcm^2. [ABSTRACT FROM AUTHOR]

Depletion mode insulated gate AlGaN/GaN power switching HEMTs were evaluated for stability under heavy-ion irradation. Experiments were performed for different types of heavy-ion species, values of gate bias, drain bias, and device geometry. For the insulated gate AlGaN/GaN devices, an as-of-yet unobserved single-event occurred, which we have termed single-event switching (SES). These SES events occurred next to previously observed single-event gate rupture (SEGR) events. It was found that the SES events were gate leakage dependent and stopped occurring above a certain threshold value of gate leakage. Statistical analysis showed that the cross section for single SES events exhibited a lognormal distribution with a median value close to the gate area, and the capture cross section exhibited a slight voltage dependence. The gate leakage after irradiation, on the other hand, was exponentially distributed and was strongly voltage and geometry dependent, indicating an electric field dependency. [ABSTRACT FROM AUTHOR]

The ESD robustness of GaN-on-Si Schottky diodes is investigated using on-wafer HBM and TLP. Both forward and reverse diode operation modes are analyzed as a function of device geometry, which strongly impact the corresponding failure mechanism. In forward mode, the anode-to-cathode length reduction and the total device width increase are beneficial for ESD robustness; however, in reverse mode, the ESD robustness does not depend on the total device width and saturates at around 400 V for medium and long anode-to-cathode lengths. The corresponding failure mechanisms are respectively attributed to the current distribution and Si substrate breakdown under forward and reverse mode ESD stresses. [ABSTRACT FROM PUBLISHER]

A combined deep-level transient spectroscopy (DLTS) and electron spin resonance (ESR) study is performed to identify the electrically active defects at the AlN/Si (111) interface. It is shown that the density of deep-level states not only depends on the thermal budget of the epitaxial deposition but also on the strain built up during growth and upon cooling to room temperature (RT). At the same time, diffusion of Si into the 200 nm thick AlN layer produces a thin crystalline Si3N4 interfacial layer, identified by transmission electron microscopy (TEM). This gives rise to so-called dangling bond Pb centres at the Si3N4/Si (111) interface. In addition, a strong evolution of the electrically active defect clusters in the silicon substrate close to the interface has been observed both in DLTS and ESR. [ABSTRACT FROM AUTHOR]

We investigated the limitations of the field plate (FP) effect on breakdown voltage VBD that is due to the silicon substrate in AlGaN/GaN/AlGaN double heterostructures field-effect transistors. In our previous work, we showed that in devices with large gate–drain distance (LGD > \8\ \mu\m), the breakdown voltage does not linearly increase with LGD because of a double leakage path between the silicon substrate and the metal contacts, which makes the device break at the silicon interface. In this paper, we showed that the effect of the FP for such large LGD is not significant because the breakdown is still dominated by the silicon substrate. The increase in VBD due to the FP is significant only for devices with small gate–drain distances (LGD < \8\ \mu\m). Indeed we show that for such small LGD the increase in the breakdown voltage is more than double, whereas for larger LGD, this is only about 10%. Simulations of AlGaN/GaN/AlGaN devices for small LGD are carried out with different FP lengths and passivation thickness in order to study the electric field distribution. [ABSTRACT FROM AUTHOR]

In this letter, we studied the forward bias gate breakdown mechanism on enhancement-mode p-GaN gate AlGaN/GaN high-electron mobility transistors. To the best of our knowledge, it is the first time that the temperature dependence of the forward gate breakdown has been characterized. We report for the first time on the observation of a positive temperature dependence, i.e., a higher temperature leads to a higher gate breakdown voltage. Such unexpected behavior is explained by avalanche breakdown mechanism: at a high positive gate bias, electron/hole pairs are generated in the depletion region at the Schottky metal/p-GaN junction. Furthermore, at a high gate bias but before the catastrophic gate breakdown, a light emission was detected by a emission microscopy measurement. This effect indicates an avalanche luminescence, which is mainly due to the recombination of the generated electron/hole pairs. [ABSTRACT FROM PUBLISHER]

This letter reports an extensive analysis of the charge capture transients induced by OFF-state bias in double heterostructure AlGaN/GaN MIS- high electron mobility transistor grown on silicon substrate. The exposure to OFF-state bias induces a significant increase in the ON-resistance (R \(_{\mathrm {{on}}}\) ) of the devices. Thanks to time-resolved on-the-fly analysis of the trapping kinetics, we demonstrate the following relevant results: 1) R \(_{\mathrm {{on}}}\) -increase is temperature- and field-dependent, hence can significantly limit the dynamic performance of the devices at relatively high-voltage and high temperature (100 °C–140 °C) operative conditions; 2) the comparison between OFF-state and back-gating stress indicates that the major contribution to the R \(_{\mathrm {{on}}}\) -increase is due to the trapping of electrons in the buffer, and not at the surface; 3) the observed exponential kinetics suggests the involvement of point-defects, featuring thermally activated capture cross section; and 4) trapping-rate is correlated with buffer vertical leakage-current and is almost independent to gate-drain length. [ABSTRACT FROM AUTHOR]

The nonlinear cold HEMT model generation procedure is described. It starts with the determination of the corresponding small-signal model by adapting the cold FET extraction approach for HEMTs. Then, the small-signal model is transformed to obtain a straightforward implementable, consistent small-signal cold HEMT model, suitable for resistive mixer design. [ABSTRACT FROM AUTHOR]

We report on a novel Au-free CMOS process-compatible process for AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors. The process starts from a 150-mm GaN-on-Si substrate with an embedded \Si3\N4\/ \Al2\O3 bilayer gate dielectric, encapsulated by a high-temperature low-pressure chemical vapor deposited nitride layer. Power devices with a 20-mm gate width reach a maximum output current of 8 A, a breakdown voltage of 750 V, and a specific on-resistance Ron, sp of 2.9 \m\Omega\cdot\cm^2. The off-state drain leakage at 600 V is 7 \mu\A. We show robust gate dielectrics with a large gate bias swing. [ABSTRACT FROM PUBLISHER]

III-Nitride materials are very promising to be used in next-generation high-frequency power switching applications. In this letter, we demonstrate the performance of normally off AlGaN/GaN/AlGaN double-heterostructure FETs (DHFETs) using a boost-converter circuit. The figures of merit of our large (57.6-mm gate width) GaN transistor are presented: RON \ast QG of 2.5 \Omega\cdot\nC is obtained at VDS = \140\ V. The switching performance of the GaN DHFET is studied in a dedicated high-frequency boost converter: both the switching times and power losses are characterized. We show converter efficiency values up to 96.1% at 500 kHz and 93.9% at 850 kHz at output power of 100 W. [ABSTRACT FROM AUTHOR]

In this letter, we present a local substrate removal technology (under the source-to-drain region), reminiscent of through-silicon vias and report on the highest ever achieved breakdown voltage (VBD) of AlGaN/GaN/AlGaN double-heterostructure FETs on a Si (111) substrate with only 2-\mu\m-thick AlGaN buffer. Before local Si removal, VBD saturates at \sim700 V at a gate–drain distance (LGD) \geq \8\ \mu\m. However, after etching away the substrate locally, we measure a record VBD of 2200 V for the devices with LGD = \20\ \mu\m . Moreover, from Hall measurements, we conclude that the local substrate removal integration approach has no impact on the 2-D electron gas channel properties. [ABSTRACT FROM AUTHOR]

The breakdown mechanism in GaN-based heterostructures (HFETs) grown on silicon substrate is investigated in detail by TCAD simulations and silicon substrate removal technique. High-voltage electrical measurements show that the breakdown voltage saturates for larger gate-drain distances. This failure mechanism is dominated by the avalanche breakdown in the Si substrate. High-voltage TCAD simulations of AlGaN/GaN/Si substrate structures show higher impact ionization factor and electron density at the Si interface indicating a leakage current path where avalanche breakdown occurs. Experimentally, by etching off the Si substrate the breakdown voltage no longer saturates and linearly increases for all gate-drain gaps. We propose the silicon removal technique as a viable way to enhance the breakdown voltage of AlGaN/GaN devices grown on Si substrate. [ABSTRACT FROM AUTHOR]

In this letter, we present a novel approach to enhance the breakdown voltage (VBD) for AlGaN/GaN/AlGaN double-heterostructure FETs (DHFETs), grown by metal-organic chemical vapor deposition on Si (111) substrates through a silicon-substrate-removal and a layer-transfer process. Before removing the Si substrate, both buffer isolation test structures and DHFET devices showed a saturation of VBD due to the electrical breakdown through the Si substrate. We observed a VBD saturation of 500 V for isolation gaps larger than 6 µm. After Si removal, we measured a VBD enhancement of the AlGaN buffer to 1100 V for buffer isolation structures with an isolation gap of 12 µm. The DHFET devices with a gate-drain (LGD) distance of 15 µm have a VBD > 1100 V compared with ~300 V for devices with Si substrate. Moreover, from Hall measurements, we conclude that the substrate-removal and layer-transfer processes have no impact on the 2-D electron gas channel properties. [ABSTRACT FROM AUTHOR]

We report on the fabrication and characterization of Au-free Ti/Al/TiN-based ohmic contacts on 200 mm AlGaN/GaN epilayers for power devices. Materials and processing used are fully compatible for integration of GaN-based devices in a Si platform. Contact resistance values as low as 0.62 Ω·mm were measured for an optimum alloy temperature as low as 550 °C. [ABSTRACT FROM AUTHOR]

The reliability of Au-free Ohmic contacts has been evaluated under a constant current stress (500 mA/mm) in a high temperature environment (150 °C, 175 °C, and 200 °C). Two Ohmic contact schemes with different Ti/Al thicknesses (5 nm/100 nm and 10 nm/100 nm) have been tested. The results showed that the degradation of the resistance ( R increase ) is accelerated at a higher temperature condition. Moreover, R increase has a square root dependence with the time. This indicates that a diffusion process could be responsible for the observed degradation. This has been confirmed by means of physical failure analyses (FIB/TEM) performed on a highly degraded device: an apparent roughness of the interface between TiN and the Ohmic metal layer was observed. On top of this, Nitrogen out-diffusion into the Ohmic metal was observed in the EDS/EELS analyses, suggesting that a material diffusion phenomenon might play a role. In addition, we observed that the devices with a lower initial contact resistance ( R c ) showed lower degradation with respect to devices with a larger initial R c . This suggests that obtaining lower R c is beneficial not only for the performance but also for the reliability. [ABSTRACT FROM AUTHOR]